subject:"Re\: \[edk2\] \[PATCH edk2\-platforms v2 02\/15\] Hisilicon\/D05\: Add PPTT support"

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

2018-02-02 Thread Jeremy Linton


Hi,

On 02/01/2018 09:42 PM, Huangming (Mark) wrote:



On 2018/2/1 9:11, Jeremy Linton wrote:

Hi,


On 01/26/2018 02:00 AM, Ming Huang wrote:

Add Processor Properties Topology Table, PPTT include


(trimming)


+STATIC
+VOID
+InitCacheInfo (
+  VOID
+  )
+{
+  UINT8Index;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+  CSSELR_DATA  CsselrData;
+  CCSIDR_DATA  CcsidrData;
+
+  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+CsselrData.Data = 0;
+CcsidrData.Data = 0;
+SetMem (
+  ,
+  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+  0
+  );
+
+if (Index == 0) { //L1I
+  CsselrData.Bits.InD = 1;
+  CsselrData.Bits.Level = 0;
+  Type1Attributes.CacheType  = 1;
+} else if (Index == 1) {
+  Type1Attributes.CacheType  = 0;
+  CsselrData.Bits.Level = Index - 1;
+} else {
+  Type1Attributes.CacheType  = 2;
+  CsselrData.Bits.Level = Index - 1;
+}
+
+CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+if (CcsidrData.Bits.Wa == 1) {
+  Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_WRITE;
+  if (CcsidrData.Bits.Ra == 1) {
+Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_READ_WRITE;
+  }
+}
+
+if (CcsidrData.Bits.Wt == 1) {
+  Type1Attributes.WritePolicy = 1;


Note a few cases where you have mixed PPTT #define definitions for some 
of the fields (AllocateType, WritePolicy, CacheType) with numeric values.




+}
+DEBUG ((DEBUG_INFO,
+"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+CsselrData.Bits.Level,
+CcsidrData.Data));
+
+mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
+mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
+mPpttCacheType1[Index].Reserved[0] = 0;
+mPpttCacheType1[Index].Reserved[1] = 0;
+mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
+mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
+mPpttCacheType1[Index].Flags.AssociativityValid = 1;
+mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
+mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
+mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
+mPpttCacheType1[Index].Flags.LineSizeValid = 1;
+mPpttCacheType1[Index].Flags.Reserved = 0;
+mPpttCacheType1[Index].NextLevelOfCache = 0;
+
+if (Index != PPTT_CACHE_NO - 1) {
+  mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 
1;
+  mPpttCacheType1[Index].Associativity = 
(UINT16)CcsidrData.Bits.Associativity + 1;
+  mPpttCacheType1[Index].LineSize = (UINT16)( 1 << 
(CcsidrData.Bits.LineSize + 4));
+  mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize *  \
+mPpttCacheType1[Index].Associativity * \
+mPpttCacheType1[Index].NumberOfSets;
+  CopyMem (
+[Index].Attributes,
+,
+sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
+);
+} else {
+  // L3 cache
+  mPpttCacheType1[Index].Size = 0x100;   // 16m
+  mPpttCacheType1[Index].NumberOfSets = 0x2000;
+  mPpttCacheType1[Index].Associativity = 0x10;   // CacheAssociativity16Way
+  SetMem (
+[Index].Attributes,
+sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+0x0A
+);
+  mPpttCacheType1[Index].LineSize = 0x80;// 128byte
+}
+  }


(trimming)


+#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
+#define PPTT_TYPE0_SCCL_FLAG   0
+#define PPTT_TYPE0_CLUSTER_FLAG0
+#define PPTT_TYPE0_CORE_FLAG   PPTT_TYPE0_PROCESSORID_VALID
+
+#define PPTT_TYPE1_ALLOCATION_WRITE   0x1
+#define PPTT_TYPE1_ALLOCATION_READ_WRITE  0x2


Its more clear for these two, they should be in the acpi header file. While 
your at it the write policy and cache type should also probably be defined and 
used in your init routing.




I plan to move these two macro to Acpi62.h.

"While your at it the write policy and cache type should also probably be defined 
and used in your init routing"
I don't really understand the mean above.


I was simply suggesting that you define/use new #defines to describe 
acpi standardized values you place in the policy and type (and any more 
you think might be helpful) fields. For example, I found it a bit odd 
that you defined PPTT_TYPE1_ALLOCATION_* but not 'PPTT_TYPE1_WRITE_POLICY_*'



Thanks,
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Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

2018-02-01 Thread Huangming (Mark)



On 2018/2/1 9:11, Jeremy Linton wrote:
> Hi,
> 
> 
> On 01/26/2018 02:00 AM, Ming Huang wrote:
>> Add Processor Properties Topology Table, PPTT include
>> Processor hierarchy node, Cache Type Structure and ID structure.
>>
>> PPTT is needed for lscpu command to show socket information correctly.
>> https://bugs.linaro.org/show_bug.cgi?id=3206
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ming Huang 
>> Signed-off-by: Heyi Guo 
>> ---
>>   Platform/Hisilicon/D05/D05.dsc |   1 +
>>   Platform/Hisilicon/D05/D05.fdf |   1 +
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   | 540 
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   |  88 
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf |  48 ++
>>   5 files changed, 678 insertions(+)
>>
>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
>> index 77a89fd..710339c 100644
>> --- a/Platform/Hisilicon/D05/D05.dsc
>> +++ b/Platform/Hisilicon/D05/D05.dsc
>> @@ -506,6 +506,7 @@
>> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>>   Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>>   #
>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
>> index 78ab0c8..97de4d2 100644
>> --- a/Platform/Hisilicon/D05/D05.fdf
>> +++ b/Platform/Hisilicon/D05/D05.fdf
>> @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
>> INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>>   INF RuleOverride=ACPITABLE 
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>>   #
>> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c 
>> b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
>> new file mode 100644
>> index 000..71c456c
>> --- /dev/null
>> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
>> @@ -0,0 +1,540 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of the 
>> BSD License
>> +*  which accompanies this distribution.  The full text of the license may 
>> be found at
>> +*  http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
>> IMPLIED.
>> +*
>> +*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
>> +*
>> +**/
>> +
>> +#include "Pptt.h"
>> +
>> +EFI_ACPI_TABLE_PROTOCOL   *mAcpiTableProtocol = NULL;
>> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol   = NULL;
>> +
>> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
>> +  ARM_ACPI_HEADER (
>> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
>> +EFI_ACPI_DESCRIPTION_HEADER,
>> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
>> +  );
>> +
>> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
>> +{
>> +  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
>> +};
> 
> I missed this the first time. I think at a minimum the VENDOR_ID needs to 
> contain something other than 0 if your populating a type2 structure. Did I 
> miss it getting overridden somewhere?
> 
> Checking the ACPI id, registry there is an existing entry for Hisilicon 
> Technologies Co.., LTD and its 'HISI'.
> 
> I would suggest you use that, and come up with a plan for how the remaining 
> fields are provided.
> 
> 

VENDOR_ID uses the value of 'HISI', there is no a appropriate value for 
remaining fields now.

>> +
>> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
>> +
>> +
>> +STATIC
>> +VOID
>> +InitCacheInfo (
>> +  VOID
>> +  )
>> +{
>> +  UINT8Index;
>> +  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
>> +  CSSELR_DATA  CsselrData;
>> +  CCSIDR_DATA  CcsidrData;
>> +
>> +  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
>> +CsselrData.Data = 0;
>> +CcsidrData.Data = 0;
>> +SetMem (
>> +  ,
>> +  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
>> +  0
>> +  );
>> +
>> +if (Index == 0) { //L1I
>> +  CsselrData.Bits.InD = 1;
>> +  CsselrData.Bits.Level = 0;
>> +  Type1Attributes.CacheType  = 1;
>> +} else if (Index == 1) {
>> +  Type1Attributes.CacheType  = 0;
>> +  CsselrData.Bits.Level = Index - 1;
>> +} else {
>> +  Type1Attributes.CacheType  = 2;
>> +  CsselrData.Bits.Level = Index - 1;
>> +}
>> +
>> +CcsidrData.Data = ReadCCSIDR

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

2018-01-31 Thread Jeremy Linton


Hi,


On 01/26/2018 02:00 AM, Ming Huang wrote:

Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.

PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
---
  Platform/Hisilicon/D05/D05.dsc |   1 +
  Platform/Hisilicon/D05/D05.fdf |   1 +
  Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   | 540 
  Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   |  88 
  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf |  48 ++
  5 files changed, 678 insertions(+)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 77a89fd..710339c 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -506,6 +506,7 @@
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
  
Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf

+  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
  
#

diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 78ab0c8..97de4d2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
  
INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf

+  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
  
#

diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c 
b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
new file mode 100644
index 000..71c456c
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
@@ -0,0 +1,540 @@
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+#include "Pptt.h"
+
+EFI_ACPI_TABLE_PROTOCOL   *mAcpiTableProtocol = NULL;
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol   = NULL;
+
+EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
+  ARM_ACPI_HEADER (
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+EFI_ACPI_DESCRIPTION_HEADER,
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+  );
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
+{
+  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
+};


I missed this the first time. I think at a minimum the VENDOR_ID needs 
to contain something other than 0 if your populating a type2 structure. 
Did I miss it getting overridden somewhere?


Checking the ACPI id, registry there is an existing entry for Hisilicon 
Technologies Co.., LTD and its 'HISI'.


I would suggest you use that, and come up with a plan for how the 
remaining fields are provided.




+
+EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
+
+
+STATIC
+VOID
+InitCacheInfo (
+  VOID
+  )
+{
+  UINT8Index;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+  CSSELR_DATA  CsselrData;
+  CCSIDR_DATA  CcsidrData;
+
+  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+CsselrData.Data = 0;
+CcsidrData.Data = 0;
+SetMem (
+  ,
+  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+  0
+  );
+
+if (Index == 0) { //L1I
+  CsselrData.Bits.InD = 1;
+  CsselrData.Bits.Level = 0;
+  Type1Attributes.CacheType  = 1;
+} else if (Index == 1) {
+  Type1Attributes.CacheType  = 0;
+  CsselrData.Bits.Level = Index - 1;
+} else {
+  Type1Attributes.CacheType  = 2;
+  CsselrData.Bits.Level = Index - 1;
+}
+
+CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+if (CcsidrData.Bits.Wa == 1) {
+  Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_WRITE;
+  if (CcsidrData.Bits.Ra == 1) {
+Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_READ_WRITE;
+  }
+}
+
+if (CcsidrData.Bits.Wt == 1) {
+  Type1Attributes.WritePolicy = 1;
+}
+DEBUG ((DEBUG_INFO,
+"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+CsselrData.Bits.Level,
+CcsidrData.Data));
+
+

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

2018-01-30 Thread graeme . gregory

On Fri, Jan 26, 2018 at 04:00:37PM +0800, Ming Huang wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
> 
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?id=3206
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang 
> Signed-off-by: Heyi Guo 
> ---

Code looks sane enough to me, but I cant give an indepth review of the
PPTT bit.


Reviewed-by: Graeme Gregory 


>  Platform/Hisilicon/D05/D05.dsc |   1 +
>  Platform/Hisilicon/D05/D05.fdf |   1 +
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   | 540 
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   |  88 
>  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf |  48 ++
>  5 files changed, 678 insertions(+)
> 
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index 77a89fd..710339c 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -506,6 +506,7 @@
>MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>  
>Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>#
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 78ab0c8..97de4d2 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
>INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>INF RuleOverride=ACPITABLE 
> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>  
>#
> diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c 
> b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> new file mode 100644
> index 000..71c456c
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
> @@ -0,0 +1,540 @@
> +/** @file
> +*
> +*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +EFI_ACPI_TABLE_PROTOCOL   *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol   = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> +  ARM_ACPI_HEADER (
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> +EFI_ACPI_DESCRIPTION_HEADER,
> +EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> +  );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> +  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, 0, 0, 0, 0, 0, 0}
> +};
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> +  VOID
> +  )
> +{
> +  UINT8Index;
> +  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> +  CSSELR_DATA  CsselrData;
> +  CCSIDR_DATA  CcsidrData;
> +
> +  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> +CsselrData.Data = 0;
> +CcsidrData.Data = 0;
> +SetMem (
> +  ,
> +  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> +  0
> +  );
> +
> +if (Index == 0) { //L1I
> +  CsselrData.Bits.InD = 1;
> +  CsselrData.Bits.Level = 0;
> +  Type1Attributes.CacheType  = 1;
> +} else if (Index == 1) {
> +  Type1Attributes.CacheType  = 0;
> +  CsselrData.Bits.Level = Index - 1;
> +} else {
> +  Type1Attributes.CacheType  = 2;
> +  CsselrData.Bits.Level = Index - 1;
> +}
> +
> +CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> +if (CcsidrData.Bits.Wa == 1) {
> +  Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_WRITE;
> +  if (CcsidrData.Bits.Ra == 1) {
> +Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_READ_WRITE;
> +  }
> +}
> +
> +if (CcsidrData.Bits.Wt == 1) {
> +  Type1Attributes.WritePolicy = 1;
> +}
> +DEBUG ((DEBUG_INFO,
> +"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
> +CsselrData.Bits.Level,
> +CcsidrData.Data));
> +
> +

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

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