WL statement or PWL File instead:
>
>
> http://www.analog.com/en/technical-articles/ltspice-piecewise-linear-functions-for-voltage-current-sources.html
>
> On 4/2/2018 1:33 PM, Salar Parast wrote:
>
> Hello Justin,
>
> Thanks so much for your quick reply.
> I kn
Hi there,
How can generate the Netlist for a project?
Thanks a lot for your help.
Cheers,
Salar
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Hi all,
For my project I have to make a SIPO shift register using D-FF and
transmission gates.
I have made the schematic of the D-FF, and now I would like to test my
design and see if my shift register is working properly.
How can I make a pulse for my clk with fixed duration?
Also I would like
> Cheers!
> Justin
>
> On Sunday, 1 April 2018 10:34:10 UTC+8, Salar Parast wrote:
>>
>> Hi all,
>>
>> For my project I have to make a SIPO shift register using D-FF and
>> transmission gates.
>> I have made the schematic of the D-FF, and now I would
Hello All,
I am doing a project for a class where I have to do both front-end and
back-end of a design. I am designing a 16-bit Multiplier. I already have
wrote the verilog code (btw complete noob in front-end design and any HDL
coding). I need to do the schematic and layout of the whole
Hello All,
For a project I would like to analysis the effect of different technologies
(50nm vs 300nm) on a low pass filter. My biggest confusion is, how do I
implement the low pass filter and do the layout of it. What variable
(length, width, etc) is changing on the capacitor and the
