I got it to work. I was selecting the wrong Serial Port.
Ashwith J. Rego
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Hi,
I can open the application and compile programs. But I am unable to
upload programs to my Uno board. The Tx Rx lights don't blink when I
click upload so I guess it's not communicating at all. I get the
following error in the IDE: avrdude: stk500_recv(): programmer is not
responding.
When I
Hi,
I have the following code for an inverter:
--inverter (NOT) gate
entity invg is port
(
a : in bit;
x : out bit;
vdd : in bit;
vss : in bit
);
end invg;
architecture vbe of invg is begin
x = not (a);
end vbe;
I saved
Hi,
I was trying a structural simulation using asimut (I've attached the
files in mux.tar). The files andg.vst, org.vst and invg.vst were
generated by boog.I ran the following command:
asimut mux mux_in mux_out
The output I got is the following:
###- processing pattern 0 : 0 ps -###
Hi Shakti,
File a bug at bugzilla.redhat.com against the alliance package.
Chitlesh currently maintains the package.
I filed the bug now (# 823228).
Any reason for using F15? You might atleast want to upgrade to F16, or
you can try to use a F16 VM using virt-manager (for example).
Hi,
I have two questions.
1. Are there any alternatives to Xilinx's System generator? Possibly
something that converts octave or scilab (preferably xcos) code to
VHDL or Verilog.
2. What sort of support is available for SystemVerilog in FEL?
Thanks
Ashwith J. Rego
-
My Webpage:
Hi
I have another question. In gspiceui, with ngspice as the selected
simulator, how do you get the current though a branch? The checkbox
for current in the Parameters section is always disabled. Even
selecting just a voltage source and no other component doesn't seem to
work.
Thanking You
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