Re: [PSES] Ground Fingers routed in CPU pin fields

I should add that the pwb is designed with a ground plane 4mils from the diff pair. On Mon, Nov 29, 2021 at 12:57 PM Istvan Novak < 0e1e25a317ad-dmarc-requ...@listserv.ieee.org> wrote: > This message originated outside of DISH and was sent by: > owner-emc-p...@listserv.ieee.org > > Hi

[PSES] Ground Fingers routed in CPU pin fields

Hello all and I hope your Thanksgiving went well! I am seeking some guidance on the effect (detrimental or otherwise) on adding short (say 250mils) ground fingers in between high speed differential pairs at their source. i.e at the IC pin field. The ground finger only has a via at the entrance to

Re: [PSES] Ground Fingers routed in CPU pin fields

Hi Charles, Having a trace shorted to ground at one end and leaving open at the other end creates a quarter-wave resonator. If for sake of example the propagation delay on the particular layer is 160ps/", 250mils has 40ps and the period at the quarter-wave resonance is 4*40ps=160ps, which

[PSES] Is there is any advantage by using 0 ohm for ESD and EMC

Hello Experts, Is there any advantage by using 0 ohm series resistors in PCB for ESD and emission? Akhil - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list,