Yes indeed it is and just a few hours GMT before we will enter a new year it
all seems to work fine.
Last problem was rather simple, EEPROM configuration had to fit sofware
expectation and with the esi file it all worked.
I use soem, siitol, LAN9252 via SPI and there is no need for twincat from
> Wow... that's great!
>
> Dave
Yes, found one more malloc(...) there software stopped since it's not
implemented in my environment but replacing read_write() function with read()
function since only read was necessary and malloc(...) function could be
removed.
I think everything is OK. I hav
> Not sure I follow what you are saying "by pin" but I think it is because
> they use a development system that abstracts some details. I know that I
> almost never use the low level registers to configure pins. One reason is
> to keep my code portable if I move to a different ARM chip.
Proble
Not sure I follow what you are saying "by pin" but I think it is because
they use a development system that abstracts some details. I know that I
almost never use the low level registers to configure pins. One reason is
to keep my code portable if I move to a different ARM chip.
On Sun, Dec 24
Wow... that's great!
Dave
On 12/24/2017 6:44 AM, Nicklas Karlsson wrote:
I just got SPI started on my Ethercat LAN9252 board. It turned out SPI MISO
where configured twice.
For some reason I think almost all manufacturers choose to configure by pin so
for peripheral input pins it is possible
I just got SPI started on my Ethercat LAN9252 board. It turned out SPI MISO
where configured twice.
For some reason I think almost all manufacturers choose to configure by pin so
for peripheral input pins it is possible to configure more than one pin and get
a collision. I remember Microchip go
