One common solution is you have a sizable FPGA and just add a soft core
into it.
RISC-V is an open-source, royalty-free core specifically architected to
efficiently implement as FPGA gates that Keil can compile for, and the
common Segger JTAG programmer can program AND debug the code.
At tha
A CPU with Ethernet and a builtin FPGA/CPLD to implement the SPI ports would
probably be a very good device for an SPI router, probably also very cheap.
Packets could routed to ordinary computer running Linuxcnc as is today or split
so that real time part is in the simple device. It is not to di
