One common solution is you have a sizable FPGA and just add a soft core
into it.
RISC-V is an open-source, royalty-free core specifically architected to
efficiently implement as FPGA gates that Keil can compile for, and the
common Segger JTAG programmer can program AND debug the code.
At that point, you're pretty seamless. You can write your own
peripherals that just memory map onto the data bus without touching the
core. You can have a custom hardware neural network that has registers
and DMA that you just let run independent of the instruction core.
Danny
On 3/31/2019 3:14 AM, Nicklas Karlsson wrote:
A CPU with Ethernet and a builtin FPGA/CPLD to implement the SPI ports would
probably be a very good device for an SPI router, probably also very cheap.
Packets could routed to ordinary computer running Linuxcnc as is today or split
so that real time part is in the simple device. It is not to different from a
PLC I have on my workplace, it is mounted on a din rail without any user
interface except a reset start/stop/reset button, there is an Ethernet
connecter used for the programming, it is also possible to connect user
interface if needed but I have not investigated how it communicate.
I remember someone here talked about someone implementing PWM on a PRU. I did
on an ordinary Micro controller once, I guess code could be reused but I do not
want to do it again. A timer with compare registers plus a few other things
usually available in micro controllers is really good at this.
On Thu, 28 Mar 2019 08:05:26 +0700
TJoseph Powderly wrote:
Gene hello
On 03/27/2019 08:13 PM, Gene Heskett wrote:
On Wednesday 27 March 2019 08:12:48 TJoseph Powderly wrote:
( list apology, I seem to have replied to posters rather than to the
list, and several times :-(
re SPI comms Linuxcnc SBC microcontrollers ...
it has been said on this mail list,
that SPI is a good candidate for a bus technology to work _with_
realtime.
heres some work in that vein (maybe overlooked)
yeltrow's work:
a generic spi hal module so you can use other SPI devices ( rpi,
arduino, mcp23s17, ENC28J60, theres a lot of spi stuff to hang onto
such a bus )
https://www.forum.linuxcnc.org/24-hal-components/28851-spi-bus-generic
-driver-and-st-l6480
Interesting driver for the big stuffs. However, I wonder if yeltrow is
aware of rpspi.ko, now part of LCNC. Not parport based but gpio,
written specificly for the rpi3b. And I'm using it, writing to a Mesa
7i90 at 42 megabaud, and reading back from the 7i90 at 25 megabaud
useing only 4 gpio pins for 2 or 3 target devices.
I dont find source rpspi.c in my sources.
cant google it except to find messages from you.
My RIP source tree is DGarr's external offset branch.
I dont have raspi.kp either.
Where are these files?
The files I was speaking of were generic spi utilities,
not RPi to Mesa communication modules,
They were attempts to make SPI available on any hardware platform to any
SPI device.
They are attempts only ( one uses a parport but i guess that could be
altered to gpio )
But from the parport, the author connects to many different SPI devices.
What file builds rpspi.ko ?
Maybe its private/unpublished work from Matsche ?
I cant find it on https://github.com/LinuxCNC/linuxcnc either.
Plz lemmeno
TomP
Perusal of that code might be of help to yeltrow. gpio seems to be about
10x faster than trying to simulate SPI over a parport. The 7i90 has
both modes depending on the firmware loaded.
the files are on the forum for members linuxcnc-upload-2015-12-03.tar
So this work handily predates rpspi.ko. Still, theres obviously things to
be learned from the rpi version.
erste's work:
for ethernet circumventing usb ( via spi
interesting as spi and ethernet seem to be future avenues
http://erste.de/ethraw/README
theres other efforts but less coupled to the spi grail
tomp
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Cheers, Gene Heskett
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