Hi,
since the request to turn flashrom into a library pops up from time to
time, we have to make sure the flashrom code doesn't have any nasty
surprises.
- We have to decide on a design for fatal errors after initalization is
over. Some code uses exit(1) for any fatal errors after init, but that
, Stefan Reinauer wrote:
this patch fixes all 27 flashrom source code issues reported by
LLVM/clang's scan-build (r79326, new build on the way).
Signed-off-by: Stefan Reinauer ste...@coresystems.de
The following parts of the patch are
Acked-by: Carl-Daniel Hailfinger c
think about outsourcing ft2232spi probing and libpci
probing and make variable setting to a small configure script.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-external_compileout/flash.h
On 16.09.2009 13:48, Stefan Reinauer wrote:
Carl-Daniel Hailfinger wrote:
Compile out wiki output on request and move wiki stuff into a separate file.
This is useful for libflashrom (you don't need wiki output in a coreboot
payload).
Signed-off-by: Carl-Daniel Hailfinger c
.
If any bit would have to be set to 1, we need to erase.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-need_erase/flash.h
===
--- flashrom-need_erase/flash.h (Revision 725)
+++ flashrom
On 16.09.2009 17:49, FENG Yu Ning wrote:
Carl-Daniel Hailfinger wrote:
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-ich9_multicommand_preop/ichspi.c
===
--- flashrom
Hi Mike,
On 18.09.2009 18:55, Spangler, Mike T wrote:
I've corrected my email and am now sending to the group.
Thanks.
Of course I'd prefer it if you tried to flash coreboot (new name of
LinuxBIOS) to these boards, but that's your choice. Anyway, you said you
have the factory BIOS
this in the
most-approved manner.
As stated above, the patch is missing PCI IDs for the board enable array
and the exact GPIO number (XX). That's it.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-boardenable_cleanup_arima_hdama/board_enable.c
Hi,
here's the script I'm using to set the status of flashrom patches in
patchwork to Accepted.
The web interface only allows you to set the status, but it does not
allow you to set a commit ID. With pwclient (part of patchwork) you can
do that.
My script simply retrieves a patch (-p0) for a
Hi Mateusz,
are there any updates on this patch? It is the oldest unmerged patch and
I'd like to close the issue.
On 06.07.2009 19:26, Luc Verhaegen wrote:
Resending this patch to the newly formed flashrom ml. Ron already
kindly acked this patch.
Mateusz, the owner of this board gave me a
On 07.07.2009 17:12, Robert Millan wrote:
On Tue, Jul 07, 2009 at 03:10:32PM +0200, Luc Verhaegen wrote:
This is code from a an old board enable that i sent in 3 weeks ago. This
board enable was not necessary (as flashing worked just fine without it
too). But this function was also used
On 25.09.2009 01:55, Uwe Hermann wrote:
On Wed, Sep 23, 2009 at 08:39:01PM -0600, Marko Kraljevic wrote:
I put my flashing machine back together, and installed two
3C905CX-TX-M cards[...]
( i'm unsure whether the 512kbit addr
line(s) are drawn out to the flash or not ).
The
Hi Allan,
On 30.09.2009 02:31, Allan Björklund wrote:
On Tuesday 29 September 2009, Carl-Daniel Hailfinger, wrote:
I looked at the messages you got and also at the great debugging you did
Thank you. I used to do front line IT support, and currently do third
level support
On 06.10.2009 15:00, s...@flashrom.org wrote:
Author: uwe
New Revision: 748
Modified:
trunk/board_enable.c
trunk/print.c
Log:
Upon popular request, move board support tables to print.c.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Hi Andrea,
don't worry, we can help you recover.
It looks like your chip may have ignored the erase command.
Can you please tell us the exact mainboard name and also send the output of
lspci -nnvvvxxx
(as root) to this list? Simply hit reply all in your mail program.
On 06.10.2009 19:21,
is the KS6A (v1.0) board, pene also looked
(my eyes are not as good as they were) and she confirmed 1.0 and
_/*not 1.0A*/_ regards, (dja.)
Carl-Daniel Hailfinger wrote:
Hi Dave,
On 13.10.2009 21:53, David J Aldridge wrote:
Ran flashrom and it reports No EEPROM/flash device found, same
with -m
.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-lock_refactor/flash.h
===
--- flashrom-lock_refactor/flash.h (Revision 750)
+++ flashrom-lock_refactor/flash.h (Arbeitskopie)
@@ -175,6
Hi Maurizio,
thank you for your report. I will add your chip to the supported list.
On 16.10.2009 10:03, Maurizio Cavalli wrote:
I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom.
Board: ROE RIVER Evaluation Board from Intel
(Reference: Intel® AtomTM Processor
Hi Yuri,
here's the patch I'd like you to try. It will also show up at
http://patchwork.coreboot.org/project/flashrom/list/
Handle LPC mode of Pm49FL004 correctly.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-pm49fl004_lpc/pm49fl00x.c
On 22.10.2009 02:56, Luc Verhaegen wrote:
Ok, big change here which will require several of the people on the list
below to test and Ack this patch. But one has to admit; the result is
worth it.
Before anybody tests:
AFAICS the patch has a bug in the bitmask code which was already
On 06.10.2009 16:54, Luc Verhaegen wrote:
On Tue, Oct 06, 2009 at 04:27:52PM +0200, Carl-Daniel Hailfinger wrote:
On 07.07.2009 15:10, Luc Verhaegen wrote:
+ /* dual function that need special enable. */
+ if ((gpo = 22) (gpo = 26)) {
+ tmp = pci_read_long(dev, 0xB0
On 22.10.2009 15:16, Luc Verhaegen wrote:
We are writing flashrom here. We are dealing with bits and pci-ids. Lots
of them. If we cannot see the important things because we abstracted too
far or too little, then we fail.
I agree that finding the right abstraction level is key.
I
On 22.10.2009 23:44, Uwe Hermann wrote:
On Thu, Oct 22, 2009 at 03:16:16PM +0200, Luc Verhaegen wrote:
I agree we should drop the totally useless 0x48 register index, 0x0c
offset, and 0xffc0 bitmask from the function prototype.
Absolutely.
Also, IMHO name is pretty useless, it's on my
On 23.10.2009 01:41, Carl-Daniel Hailfinger wrote:
On 22.10.2009 15:16, Luc Verhaegen wrote:
Also, we are no longer fully on par with the previous board enables
which used to touch one bit only per gpio line. Now we touch three.
Idwer has a board which requires us to set the first bit
On 06.10.2009 13:52, Uwe Hermann wrote:
I'm thankful for better suggestions to track which chipsets and
especially boards can decode how much.
Could you please change chipset_max_rom_decode_kb to a struct with one
value per bustype? All Intel chipsets with SPI support have two
independent
of debugging on some board already, until he
figured out what was going on, we should try warn our users where
possible about this (yes, this is best effort, but still better than
not to warn at all).
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom
On 23.10.2009 16:27, Luc Verhaegen wrote:
On Fri, Oct 23, 2009 at 01:41:41AM +0200, Carl-Daniel Hailfinger wrote:
On 22.10.2009 15:16, Luc Verhaegen wrote:
I prefer to see this:
{
struct pci_dev *dev;
dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC
On 26.10.2009 16:51, ron minnich wrote:
http://www.blackhat.com/presentations/bh-usa-09/WOJTCZUK/BHUSA09-Wojtczuk-AtkIntelBios-SLIDES.pdf
interesting. Install a shell by changing the OEM logo. Would this be
an external flasher in flashrom :-)
No, because the external flasher interface
Updated patch because the board enable table changed too much. No code
changes, so I'm reusing the original commit message and acks.
Board enable for Shuttle AK31.
All AK31 versions, 1.x, 2.x and 3.x are supported by this board enable.
Sadly this board can not be autodetected.
Re-uses the epox
Mateusz tested this and probe of his chip worked fine. Erase didn't
work, but that's probably due to some block locking or a broken erase
function. Not sure yet.
I asked Mateusz to ack this patch as well, but in the meantime you have
my ack.
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2
this code a run too?
Carl-Daniel Hailfinger wrote:
Ron, can you please send lspci -vvnnxxx for the Dell S1850 to this list?
Thanks to everyone for your cooperation, it helps us make flashrom better.
Regards,
Carl-Daniel
--
Developer quote of the week:
We are juggling too many chainsaws and flaming
On 21.10.2009 23:33, Luc Verhaegen wrote:
Board: Make Acorp 6A815EPD autodetectable.
Add subsystem id for hostbridge match for Acorp 6A815EPD; even though
it reads intel, NULL, this, together with the promise ultra100 chip
and subsystem ids, should form a unique enough match for us to depend
OK, here's the current megapatch. Will split later, right now I just
want to get this out for review.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-rom_decode_check/flash.h
===
--- flashrom
Hi Guillaume,
On 29.10.2009 21:01, guillaumeg wrote:
i installed fedora 11 in my laptop Intel pentium III coppermine
i'd like to flash the bios using flashrom
I'm sorry, we do not support flashing on laptops (too dangerous).
the objectif is ( i hope) to fix a display problem - stripes on
a warning during probe (which does fail for some
chips if the size is too big) and abort before the first real
read/write/erase action.
That way, a user can find out why probe might not have worked, and will
be stopped before he/she gets incorrect results.
Signed-off-by: Carl-Daniel Hailfinger c
@@
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann u...@hermann-uwe.de
+ * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under
On 31.10.2009 02:52, Carl-Daniel Hailfinger wrote:
I agree with the changes. On top of your changes, I fixed one memory
leak and changed kB vs. KB (for consistency), patch is below for reference.
Add infrastructure to check and report to the user the maximum supported
decode size for chipsets
--verify and --noverify at the same time.
- Check for extra parameters which don't fit commandline syntax.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-mainloop_cleanup/flash.h
===
--- flashrom
On 09.11.2009 23:35, ron minnich wrote:
On Mon, Nov 9, 2009 at 2:00 PM, NotLim not...@gmail.com wrote:
Hi there. I'm at #flashrom at freenode, but no one responds... so...
can you give me a hand?
Here's the problem: http://pastebin.com/m11614dbc
uh, you were doing this on a spare
Hi Fraser,
On 10.11.2009 05:45, Fraser Hanson wrote:
I flashed my bios with flashrom tonight and got the scary warning
message saying erase failed and do not reboot.
I haven't rebooted.
As far as I can tell from using flashrom itself, everything is
actually fine.
We're working on
were picked because they are 0101 and 1010 binary.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-testpattern/flashrom.c
===
--- flashrom-testpattern/flashrom.c (Revision 756)
+++ flashrom
Hi Johannes,
On 12.11.2009 23:27, Johannes Sjölund wrote:
I wanted to update the proprietary firmware on an Asus M2V mainboard [...]
It worked prefectly!
Thanks for your report.
After that I was told that I should have read out what I had written on the
chip and compared the md5sum with
-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-sis_all/flash.h
===
--- flashrom-sis_all/flash.h(Revision 758)
+++ flashrom-sis_all/flash.h(Arbeitskopie)
@@ -389,6 +389,7 @@
/* internal.c
SiS chipsets and IT87 SPI translation, so tests in
verbose mode would be appreciated. In theory, functionality should be
unchanged.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-superio_ite_refactor/flash.h
in case pkg-config is not available
or not working.
Signed-off-by: Jörg Mayer jma...@loplof.de
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-libftdi_pkgconfig/Makefile
===
--- flashrom
Jörg checked it, and told me to go ahead.
Committed in r762.
Regards,
Carl-Daniel
--
Developer quote of the week:
We are juggling too many chainsaws and flaming arrows and tigers.
___
flashrom mailing list
flashrom@flashrom.org
On 16.11.2009 02:53, Idwer Vollering wrote:
Add URLs for boards ASUS K8V, ASUS K8V SE Deluxe, Elitegroup K7S5A.
FIxes a typo, adds a note for ASUS M2N-E.
Signed-off-by: Idwer Vollering vid...@gmail.com
Thanks,
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
If a SPI command taking an address does fail, we want to know the
address for easier debugging.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-spi_command_failure_verbose/spi.c
Hi Vincent,
On 16.11.2009 16:00, vinc...@cojot.name wrote:
This patch provided help to debug the issue..
Acked-by: Vincent S. Cojot openl...@cojot.name
thanks for testing. Committed in r764.
Regards,
Carl-Daniel
--
Developer quote of the week:
We are juggling too many chainsaws and flaming
Show ICH flash descriptor info only if valid. Otherwise it is just
confusing the developers.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-ich_spi_descriptor/chipset_enable.c
On 16.11.2009 16:16, Carl-Daniel Hailfinger wrote:
Show ICH flash descriptor info only if valid. Otherwise it is just
confusing the developers.
Before anyone hollers: This patch needs to be checked for ICH version
dependencies.
Regards,
Carl-Daniel
--
Developer quote of the week:
We
On 16.11.2009 22:05, Benjamin BELLEC wrote:
Hello,
I was reading the Makefile (r764) and I saw at line 92-92 :
92 - # Always enable wiki printing for now.
93 - CONFIG_PRINT_WIKI ?= no
Given the precedent lines I think this is not coherent, right ?
Thanks, fixed in r765.
Regards,
On 31.10.2009 03:23, Carl-Daniel Hailfinger wrote:
To prepare for libflashrom I wanted to make the main loop more readable
and more correct and factor out stuff which can be useful in libflashrom.
- Factor out printing of supported devices to print.c.
- Adjust name of wiki printing function
On 17.11.2009 10:08, Stefan Reinauer wrote:
Acked-by: Stefan Reinauer ste...@coresystems.de
Thanks, r766.
Regards,
Carl-Daniel
--
Developer quote of the week:
We are juggling too many chainsaws and flaming arrows and tigers.
___
flashrom
On 17.09.2009 12:41, Carl-Daniel Hailfinger wrote:
On 16.09.2009 23:40, Stefan Reinauer wrote:
Carl-Daniel Hailfinger wrote:
On 16.09.2009 19:07, Stefan Reinauer wrote:
Carl-Daniel Hailfinger wrote:
For optimal partial reflashing, we have to find out which parts
On 20.10.2009 23:38, Carl-Daniel Hailfinger wrote:
New version.
Chip locking has three actions you can do with it:
- Print/read the current locking status
- Lock the chip
- Unlock the chip.
Currently, the code usually does lock printing inside the probe
function, and unlocking somewhere
respond with
Acked-by: Your Name y...@email
On 10.11.2009 04:07, Carl-Daniel Hailfinger wrote:
Pretty much everybody who used the FT2232 SPI driver in flashrom had
problems with incorrect reads from time to time.
One reason was that the hardware is pretty timing sensitive even for reads
).
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: flashrom-serprog_share/flash.h
===
--- flashrom-serprog_share/flash.h (Revision 767)
+++ flashrom
: Either internal or dummy programmer needs to be compiled in due to
the current behaviour of always picking a default programmer if -p is
not specified. Picking an arbitrary external programmer as default
wouldn't make sense.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index
Jeremy, thanks for testing.
Paul, thanks for the review.
Patch committed in r769.
Regards,
Carl-Daniel
--
Developer quote of the month:
We are juggling too many chainsaws and flaming arrows and tigers.
___
flashrom mailing list
On 19.11.2009 17:51, Carl-Daniel Hailfinger wrote:
On 17.09.2009 12:41, Carl-Daniel Hailfinger wrote:
On 16.09.2009 23:40, Stefan Reinauer wrote:
Carl-Daniel Hailfinger wrote:
On 16.09.2009 19:07, Stefan Reinauer wrote:
Carl-Daniel Hailfinger
On 23.11.2009 16:33, Uwe Hermann wrote:
On Sat, Nov 21, 2009 at 01:29:11PM +0100, Carl-Daniel Hailfinger wrote:
Move serial handling from serprog.c to serial.c.
This is the first step in enabling platform independent serprog and it
also allows other drivers to use serial port functionality
code) it is possible to
#define FAKE_COMMUNICATION in buspirate_spi.c.
Thanks to Sean Nelson for the SPI mode settings code. I tweaked it a bit
to make configuration from a commandline easier should anybody want that
feature.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
On 24.11.2009 01:09, Sean Nelson wrote:
The Bus Pirate code works, but flashrom might hang if the chip has a
personal problem; none of the Bus Pirate's fault.
I think it has to do with the chip not being reset, internally.
Interesting. In theory, this should not happen for read/probe, but
On 24.11.2009 01:29, Stefan Reinauer wrote:
s...@flashrom.org wrote:
+ifeq ($(CONFIG_BUSPIRATESPI), yes)
+FEATURE_CFLAGS += -D'BUSPIRATE_SPI_SUPPORT=1'
+OBJS += buspirate_spi.o
+endif
+
+# Ugly, but there's no elif/elseif.
ifeq ($(CONFIG_SERPROG), yes)
OBJS += serial.o
+else
+ifeq
On 24.11.2009 02:48, Sean Nelson wrote:
Add Generic SPI detect for Sanyo chips.
Signed-off-by: Sean Nelson audiohac...@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Thanks, r774.
Add LF25FW203A support.
Signed-off-by: Sean Nelson audiohac...@gmail.com
size from 8 to 12 bytes (current single-transaction
limit of the Bus Pirate raw SPI protocol).
Add Bus Pirate to the list of programmers supporting 4 byte RDID.
Add Bus Pirate syntax to the man page.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom
Hi,
I'd like to get some input on using the correct patch state in Patchwork.
1. Patches which have been acked and are waiting for commit.
2. Patches which are not intended for merging, but which should stay
easily available in case someone needs them. This includes debug patches
and emergency
Hi,
I'm sorry for cross-posting this to coreboot@ and flashrom@, but
flashrom is suffering badly from reviewer shortage.
If you have some spare time and feel like reviewing stuff, please take a
look at a few patches which have accumulated over the last few months.
Below is the list, together
On 24.11.2009 17:43, Sean Nelson wrote:
Send Ack to list. And send Tested-by while I'm at it.
Acked-by: Sean Nelson audiohac...@gmail.com
Tested-by: Sean Nelson audiohac...@gmail.com
Thanks, r776.
Regards,
Carl-Daniel
--
Developer quote of the month:
We are juggling too many chainsaws
On 24.11.2009 15:51, Maciej Pijanka wrote:
On Mon, 23 Nov 2009, Carl-Daniel Hailfinger wrote:
Kill hardcoded block erase on ICH SPI.
The existing code does not work for all SPI chips, and it just was a
band-aid to cope with locked down chipsets back in a time when there was
no eraseblock
Hi,
flashrom currently doesn't have a coherent policy about failed writes.
Some chip drivers abort on the first failed write, others keep going
until the end. Either variant makes sense, but mixing them is suboptimal.
The following policies are available:
- hardcode abort early (on first error)
jedec.c was missing error handling in a few cases. Fix.
jedec.c error handling used double negation in too many places for no
good reason. Clean up.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-jedec_errorhandling/jedec.c
Next try, this time with fixed error location printing.
jedec.c was missing error handling in a few cases. Fix.
jedec.c error handling used double negation in too many places for no
good reason. Clean up.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom
that this patch makes sure to have zero impact on the binary
(because it is compiled out by default) and because it lowers the
barrier for someone else to come and implement the rest of cheetah
support, I'm for merging.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom
is available for download here:
http://patchwork.coreboot.org/patch/596/raw/
Regards,
Carl-Daniel
On 25.11.2009 15:16, Carl-Daniel Hailfinger wrote:
I wrote this Cheetah support stub months ago and carried it forward over
various interface changes. I don't have the hardware, so I'm not really
On 25.11.2009 16:36, Sean Nelson wrote:
On 11/25/2009 4:28 AM, Carl-Daniel Hailfinger wrote:
jedec.c was missing error handling in a few cases. Fix.
jedec.c error handling used double negation in too many places for no
good reason. Clean up.
Signed-off-by: Carl-Daniel
Hailfingerc
On 25.11.2009 16:31, Paul Fox wrote:
carl-daniel wrote:
Reduce realloc syscall overhead for FT2232 and bitbang.
FT2232 ran realloc() for every executed command. Start with a big enough
buffer and don't touch buffer size unless it needs to grow.
Bitbang was slightly better: It only
saying the
same.
If anybody has contacts at Intel and can check, I'd be happy to add the
rest of the IDs.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-intel_3400series_5series/chipset_enable.c
On 26.11.2009 19:34, Stefan Reinauer wrote:
Any ideas?
superiotool finds nothing on this machine. It's i945/ICH7
Hm, yes. It seems we're missing a probe sequence for your superio or EC.
flashrom v0.9.1-r783
Found chipset Intel ICH7M, enabling flash write...
BIOS Lock Enable:
On 27.11.2009 01:05, Stefan Reinauer wrote:
On 11/27/09 12:54 AM, Carl-Daniel Hailfinger wrote:
- Handling chips with varying sizes (based on some config byte) is
broken by this change.
Which chips are that?
They have a comment in flashchips.c:
/* Size can only be determined
[CC flashrom because this is a flashrom topic. Please don't drop it from
CC.]
On 27.11.2009 01:04, Peter Stuge wrote:
ron minnich wrote:
Serialice could have the capability to flash the normal.
Yes, but I say forget about using flashrom as-is for this. The code
is still pretty much
[Please keep flashrom@flashrom.org in CC so others can learn as well.
Thanks.]
On 27.11.2009 04:29, Cory Cline wrote:
This is indeed a laptop. I did not realize the limitations extended that
far. With all my research, I should of known that.
Hey, it's not your fault that you own a laptop.
On 27.11.2009 13:03, Stefan Reinauer wrote:
On 11/26/09 7:46 PM, Stefan Reinauer wrote:
On 11/26/09 7:34 PM, Stefan Reinauer wrote:
superiotool finds nothing on this machine. It's i945/ICH7
The flash part is one of:
* EON EN29LV800AB
* AMD M29LV800BE
* Spansion
On 27.11.2009 15:01, Stefan Reinauer wrote:
On 11/27/09 1:23 PM, Carl-Daniel Hailfinger wrote:
You could sniff LPC and SPI buses during reflashing with the vendor
flash tool and correlate the dumps.
How?
There is not SPI involved, however.
Sorry, my bad. I was writing two
On 27.11.2009 17:43, ron minnich wrote:
Have we crossed some boundary where we're going to need tools to
systematically reverse engineer the EC now? Maybe we need to start
accumulating EC knowledge on a new coreboot.org page ... I am
realizing I don't understand them at all.
coreboot.org
On 27.11.2009 01:00, Michael Karcher wrote:
Use common jedec functionality where appropriate.
Thanks, looks good.
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Committed in r785.
Regards,
Carl-Daniel
--
Developer quote of the month:
We are juggling too many
this chipset
to get flashrom -V output.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-mcp67_spi_detect/chipset_enable.c
===
--- flashrom-mcp67_spi_detect/chipset_enable.c (Revision 792
Hi Alex,
I found a few high-resolution photos for the M2N68-VM.
It is the 8-pin chip in a socket with a yellow dot in the middle of the
lower edge of the board here:
http://img24.imageshack.us/img24/7444/m2n68vmfull2.jpg
It is the 8-pin chip in a socket with a blue dot in the lower left
corner
On 23.11.2009 03:26, Carl-Daniel Hailfinger wrote:
Fix eraseblock walking and add a few more checks to make sure such bugs
get caught in the future. I found this bug during a code review.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Ping?
Regards,
Carl-Daniel
as
a server, tests with this patch are still useful in theory, but the
results might be garbage. Not sure yet. I can't make any guarantees, but
the patch should be safe to test (unless the GPIO read has side effects,
but that is unlikely).
Regards,
Carl-Daniel
Carl-Daniel Hailfinger wrote:
First
On 04.12.2009 17:48, Alessandro Polverini wrote:
I got latest sources from trunk, applied the provided patch,
cold-booted and saved the output of flashrom -V (attached).
flashrom v0.9.1-r791
No coreboot table found.
Found chipset NVIDIA MCP67, enabling flash write... ISA bridge reg 0x8a
Hi Zachary,
thanks for your patch and the machine data. I will merge the patch soon.
On 04.12.2009 23:48, Zachary Dillard wrote:
BIOS flash successful on this motherboard ASRock M3A790GXH/128M.
Would you mind replying to this mail with a Signed-off-by line as
outlined in
On 21.11.2009 15:38, Carl-Daniel Hailfinger wrote:
Internal (onboard) programming was the only feature which could not be
disabled.
Make various pieces of code conditional on support for internal
programming. Code shared between PCI device programmers and onboard
programming is now
On 05.12.2009 00:59, Luc Verhaegen wrote:
On Mon, Nov 30, 2009 at 02:47:33PM +0100, Carl-Daniel Hailfinger wrote:
Ah, that. Many BIOSes out there change a few bytes in the ROM on each
boot. They store boot date/time and some configuration data. Such
changes are expected. As long
On 05.12.2009 00:54, Michael Spang wrote:
On Fri, Dec 4, 2009 at 6:41 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
Hi Luc,
I almost committed this patch, then I found a line which you might
object to. We have a lspci for exactly this board from another user
On 12.12.2009 08:04, Sean Nelson wrote:
[...] we need to figure out why patchwork thinks my patches are
unrelated and creates separate entries for each changed patch.
Actually, that's expected because patchwork can't know if two patches
are related. I'm thinking of a Supersedes: tag, but right
in all 1024 possible build combinations. The
only failures are by design as mentioned above.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by: Sean Nelson audiohac...@gmail.com
Index: flashrom-programmer_internal_optional/flash.h
On 13.12.2009 21:07, Carl-Daniel Hailfinger wrote:
Internal (onboard) programming was the only feature which could not be
disabled.
It is now possible to build only with dummy support:
make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no
CONFIG_DRKAISER=no CONFIG_SERPROG
Hi Adam,
On 24.11.2009 16:52, Carl-Daniel Hailfinger wrote:
On 24.11.2009 16:46, Adam Jurkowski wrote:
Don't print out supported PCI devices header if all following lines
are excluded from build.
Your patch unfortunately conflicts with
http://patchwork.coreboot.org/patch/576
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