Is there a reason why MM_MaskInvalidOp is not set in mxcsr in rtl/x86_64/x86_64.inc?
I have a 3rd party application that depends on InvalidOp to be masked out. I want to extend this application with a FPC library. But the initialization code of the library (SysInitFPU) unmasks the InvalidOp exception. I now call "SetSSECSR(GetSSECSR or $0080);" in the initialization section of my main unit to mask out the InvalidOp exception again. But I wonder if this could break something (in rtl or internal FPC functions). I fear it is unmasked on purpose in SysInitFPU because according to the Intel documentation (Intel Software Developers Manual 2A) "The default MXCSR value at reset is 1F80H." _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
