> > From: J. Gareth Moreton
> > To:
> >> Are you able to dump the nodes as well with -an? (You'll need to define
> >> -dEXTDEBUG though) That might give some clues behind the presence of
> >> that movslq instruction.
> >
> You will need to also add ALLOW_WARNINGS=1 to the make call.
Ok, ALLOW_W
Le 05/02/2020 à 07:17, Marģers . via fpc-devel a écrit :
>
>
> From: J. Gareth Moreton
> To:
>> Are you able to dump the nodes as well with -an? (You'll need to define
>> -dEXTDEBUG though) That might give some clues behind the presence of
>> that movslq instruction.
>
> building compiler
Hmmm, well that's inconvenient! Means we can't easily test things with
that feature.
Gareth aka. Kit
On 05/02/2020 06:17, Marģers . via fpc-devel wrote:
From: J. Gareth Moreton
To:
Are you able to dump the nodes as well with -an? (You'll need to define
-dEXTDEBUG though) That might g
From: J. Gareth Moreton
To:
> Are you able to dump the nodes as well with -an? (You'll need to define
> -dEXTDEBUG though) That might give some clues behind the presence of
> that movslq instruction.
building compiler with -dEXTDEBUG does not work for me
make singlezipinstall OS_TARGET=linu
devel] generate assembler with no clear purpose MOV
Date: otrd., 4 febr. 2020, 22:24
From: J. Gareth Moreton
To:
To hazard a guess, it's sign-extending to the CPU word size as an
intermediate step. It's not something the peephole optimizer can easily
eliminate. Do the register alloc
- Reply to message -
Subject: Re: [fpc-devel] generate assembler with no clear purpose MOV
Date: otrd., 4 febr. 2020, 22:24
From: J. Gareth Moreton
To:
> To hazard a guess, it's sign-extending to the CPU word size as an
> intermediate step. It's not something the pe
To hazard a guess, it's sign-extending to the CPU word size as an
intermediate step. It's not something the peephole optimizer can easily
eliminate. Do the register allocations give any clues before that
instruction?
Gareth aka. Kit
On 04/02/2020 18:50, Marģers . via fpc-devel wrote:
p.s
p.s. tested execution speed and there is no measurable difference.
> asm code
> # [109] bit:= longint(1) shl k;
> movslq %ecx,%rdx
> # Register r8d allocated
> movl $1,%r8d
> # Register edx,edx allocated
> shlx %edx,%r8d,%edx
> # Register r8d released
> # Reg
