Hello FPC, Tuesday, June 28, 2011, 3:39:29 PM, you wrote:
AB> Sort of right. 6 core system. Core 1 locks code block. Code block AB> should still use interlocked statements to make memory assignments so AB> that when Core 1 releases lock - Core 2 can have a real-time image of AB> variable. Otherwise Core 2 may see a stale copy of the variable. Core 2 should only access those variables using the same lock (critical section) as core 1 or data integrity is not garanteed. Critical sections garantee a full fence, pipe lines as invalidated. The only possible problem is the variable caching in a register, but as stated here the call to the function that perform the critical section forces fpc to store the variables in a register to its memory address and the critical section activity forces the fence ensuring all cores see the same data at the same time. You can not protect a code with a critical section and access the data without using the same critical section, so you can not protect code with a critical section and operate over the data in other thread with interlock operations. This is not threading 101, do not ? -- Best regards, José _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel