Create some hooks for IO APIC operations that will diverge from bare
metal when implemented for Xen Dom0.
This patch should not introduce any changes in functionality, it's a
preparatory patch for the implementation of the Xen IO APIC hooks.
---
sys/amd64/include/apicvar.h | 13
sys/i386/include/apicvar.h | 13
sys/x86/include/apicreg.h | 12
sys/x86/x86/io_apic.c | 65 ++-
4 files changed, 71 insertions(+), 32 deletions(-)
diff --git a/sys/amd64/include/apicvar.h b/sys/amd64/include/apicvar.h
index 84e01d4..a48a76b 100644
--- a/sys/amd64/include/apicvar.h
+++ b/sys/amd64/include/apicvar.h
@@ -161,6 +161,19 @@ struct apic_enumerator {
SLIST_ENTRY(apic_enumerator) apic_next;
};
+struct ioapic_intsrc {
+ struct intsrc io_intsrc;
+ u_int io_irq;
+ u_int io_intpin:8;
+ u_int io_vector:8;
+ u_int io_cpu:8;
+ u_int io_activehi:1;
+ u_int io_edgetrigger:1;
+ u_int io_masked:1;
+ int io_bus:4;
+ uint32_t io_lowreg;
+};
+
inthand_t
IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
diff --git a/sys/i386/include/apicvar.h b/sys/i386/include/apicvar.h
index 24c99f0..c8ee9bc 100644
--- a/sys/i386/include/apicvar.h
+++ b/sys/i386/include/apicvar.h
@@ -160,6 +160,19 @@ struct apic_enumerator {
SLIST_ENTRY(apic_enumerator) apic_next;
};
+struct ioapic_intsrc {
+ struct intsrc io_intsrc;
+ u_int io_irq;
+ u_int io_intpin:8;
+ u_int io_vector:8;
+ u_int io_cpu:8;
+ u_int io_activehi:1;
+ u_int io_edgetrigger:1;
+ u_int io_masked:1;
+ int io_bus:4;
+ uint32_t io_lowreg;
+};
+
inthand_t
IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
diff --git a/sys/x86/include/apicreg.h b/sys/x86/include/apicreg.h
index 283d50e..4629470 100644
--- a/sys/x86/include/apicreg.h
+++ b/sys/x86/include/apicreg.h
@@ -204,6 +204,18 @@ struct IOAPIC {
typedef struct IOAPIC ioapic_t;
+struct ioapic_intsrc;
+/*
+ * Struct containing pointers to IO APIC management functions whose
+ * implementation is run time selectable.
+ */
+struct ioapic_ops {
+ u_int(*read)(volatile ioapic_t *, int);
+ void (*write)(volatile ioapic_t *, int, u_int);
+ void (*register_intr)(struct ioapic_intsrc *);
+};
+extern struct ioapic_ops ioapic_ops;
+
#undef PAD4
#undef PAD3
diff --git a/sys/x86/x86/io_apic.c b/sys/x86/x86/io_apic.c
index 6d62b1e..125d06a 100644
--- a/sys/x86/x86/io_apic.c
+++ b/sys/x86/x86/io_apic.c
@@ -81,19 +81,6 @@ static MALLOC_DEFINE(M_IOAPIC, io_apic, I/O APIC
structures);
* ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
*/
-struct ioapic_intsrc {
- struct intsrc io_intsrc;
- u_int io_irq;
- u_int io_intpin:8;
- u_int io_vector:8;
- u_int io_cpu:8;
- u_int io_activehi:1;
- u_int io_edgetrigger:1;
- u_int io_masked:1;
- int io_bus:4;
- uint32_t io_lowreg;
-};
-
struct ioapic {
struct pic io_pic;
u_int io_id:8; /* logical ID */
@@ -106,8 +93,9 @@ struct ioapic {
struct ioapic_intsrc io_pins[0];
};
-static u_int ioapic_read(volatile ioapic_t *apic, int reg);
-static voidioapic_write(volatile ioapic_t *apic, int reg, u_int val);
+static u_int native_ioapic_read(volatile ioapic_t *apic, int reg);
+static voidnative_ioapic_write(volatile ioapic_t *apic, int reg, u_int
val);
+static voidnative_ioapic_register_intr(struct ioapic_intsrc *pin);
static const char *ioapic_bus_string(int bus_type);
static voidioapic_print_irq(struct ioapic_intsrc *intpin);
static voidioapic_enable_source(struct intsrc *isrc);
@@ -139,6 +127,13 @@ SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint,
CTLFLAG_RDTUN, enable_extint, 0,
Enable the ExtINT pin in the first I/O APIC);
TUNABLE_INT(hw.apic.enable_extint, enable_extint);
+/* Default ioapic_ops implementation. */
+struct ioapic_ops ioapic_ops = {
+ .read = native_ioapic_read,
+ .write =native_ioapic_write,
+ .register_intr =native_ioapic_register_intr,
+};
+
static __inline void
_ioapic_eoi_source(struct intsrc *isrc)
{
@@ -146,7 +141,7 @@ _ioapic_eoi_source(struct intsrc *isrc)
}
static u_int
-ioapic_read(volatile ioapic_t *apic, int reg)
+native_ioapic_read(volatile ioapic_t *apic, int reg)
{
mtx_assert(icu_lock, MA_OWNED);
@@ -155,7 +150,7 @@ ioapic_read(volatile ioapic_t *apic, int reg)
}
static void
-ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
+native_ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
{
mtx_assert(icu_lock, MA_OWNED);
@@ -163,6 +158,12 @@ ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
apic-iowin =
