In message: [EMAIL PROTECTED]
Craig Boston [EMAIL PROTECTED] writes:
: On Fri, 2003-06-13 at 14:17, Tony Naggs wrote:
: Yes, I think you should also do this for Uhci. There are probably not
: many straight Uhci USB 1.1 Cardbus cards, but it is likely some of the
: USB 2.0 cards
In message [EMAIL PROTECTED], Craig
Boston [EMAIL PROTECTED] wrote
On Thu, 2003-06-12 at 08:14, Anthony Naggs wrote:
Sorry, I don't understand this comment. All OHCI, UHCI EHCI USB
controllers need PCI bus mastering in order to read update their
various lists of pending completed
On Fri, 2003-06-13 at 14:17, Tony Naggs wrote:
Yes, I think you should also do this for Uhci. There are probably not
many straight Uhci USB 1.1 Cardbus cards, but it is likely some of the
USB 2.0 cards have an UHCI controller rather than OHCI for USB 1.x
support.
Never mind, it seems Warner
Craig Boston wrote this message on Wed, Jun 11, 2003 at 22:44 -0500:
Believe it or not, after futzing with the debugger for hours, reading the OHCI
spec, and trying to figure out why writing to the control registers works
exactly as it should but the card seems to ignore the ED list, I
On Thu, Jun 12, 2003 at 01:10:24AM -0700, John-Mark Gurney wrote:
Craig Boston wrote this message on Wed, Jun 11, 2003 at 22:44 -0500:
Believe it or not, after futzing with the debugger for hours, reading the OHCI
spec, and trying to figure out why writing to the control registers works
On Thu, 2003-06-12 at 03:10, John-Mark Gurney wrote:
Craig Boston wrote this message on Wed, Jun 11, 2003 at 22:44 -0500:
Hey, thanks for the great work. This got me past the same problem on
the sparc box I have...
Don't look at me -- thank Warner for all his hard work on Cardbus and
the
In article [EMAIL PROTECTED], Craig Boston
[EMAIL PROTECTED] writes
Believe it or not, after futzing with the debugger for hours, reading the OHCI
spec, and trying to figure out why writing to the control registers works
exactly as it should but the card seems to ignore the ED list, I decided to
On Thu, 2003-06-12 at 08:14, Anthony Naggs wrote:
Sorry, I don't understand this comment. All OHCI, UHCI EHCI USB
controllers need PCI bus mastering in order to read update their
various lists of pending completed transfers.
That was speculation on my part as to why bus mastering was not
Bernd Walter wrote this message on Thu, Jun 12, 2003 at 14:30 +0200:
On Thu, Jun 12, 2003 at 01:10:24AM -0700, John-Mark Gurney wrote:
Craig Boston wrote this message on Wed, Jun 11, 2003 at 22:44 -0500:
pci_enable_busmaster(self);
near the top of ohci_attach() in ohci_pci.c
Believe it or not, after futzing with the debugger for hours, reading the OHCI
spec, and trying to figure out why writing to the control registers works
exactly as it should but the card seems to ignore the ED list, I decided to
try something completely crazy and put the line
Cut-and-paste of the patch since the attachment disappeared... Probably won't
apply cleanly because of tabs.
--- ohci_pci.c.orig 2003-06-11 22:32:42.0 -0500
+++ ohci_pci.c 2003-06-11 22:01:43.0 -0500
@@ -173,6 +173,8 @@
/* XXX where does it say so in the spec? */
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