Re: Dynamic reads without locking.

2003-10-13 Thread Harti Brandt
On Fri, 10 Oct 2003, Tim Kientzle wrote: TKHarti Brandt wrote: TK Yes. When I read the C standard TKfoo = data mask; TK wouldn't also help, because there is no sequence point in this statement TK except at the ;. TK TKBefore anyone takes this particular line of reasoning seriously, TKI feel

Re: Determining CPU features / cache organization from userland

2003-10-13 Thread Peter Jeremy
On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote: [ Andrew: Perhaps you can shed some light on how the necessary information can be gathered on Alpha? My search was incomplete and I could not find a reliable source for DEC's development manuals. ] L1 cache information is in the CPU

On-board Promise controller is not detected

2003-10-13 Thread Kees Jan Koster
Dear FreeBSD hackers, I have posted this question to FreeBSD-questions earlier, but got no reply. So I try here. I'm having trouble getting my on-board Promise controller to work. I can use atacontrol to build an array, but sysinstall won't detect the disk pack. Could this be a problem with the

Re: afaapps port committed to FreeBSD

2003-10-13 Thread Helge Oldach
Hi, I may sound ignorant, but what is wrong with the FreeBSD-native aaccli utility that can be downloaded from Adaptec (5400s_fbsd_cli_v10.zip)? I have been using this for some time now with success. May I suggest to make a port out of this as well? Helge Bruce M Simpson: Hi, I'm a FreeBSD

Re: afaapps port committed to FreeBSD

2003-10-13 Thread Bruce M Simpson
On Mon, Oct 13, 2003 at 05:20:31PM +0200, Helge Oldach wrote: I may sound ignorant, but what is wrong with the FreeBSD-native aaccli utility that can be downloaded from Adaptec (5400s_fbsd_cli_v10.zip)? I have been using this for some time now with success. May I suggest to make a port out

Re: Determining CPU features / cache organization from userland

2003-10-13 Thread Sean Winn
Peter Jeremy wrote: On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote: [ Andrew: Perhaps you can shed some light on how the necessary information can be gathered on Alpha? My search was incomplete and I could not find a reliable source for DEC's development manuals. ] L1 cache

Re: Determining CPU features / cache organization from userland

2003-10-13 Thread Bruce M Simpson
All, Here are detailed design documents for determining cache and TLB geometry across our currently supported processor architectures, with recommendations outlined for implementation. What I haven't addressed yet is how indirect consumers of the API might use it, e.g. mutex consumers vs. UMA,

Re: Determining CPU features / cache organization from userland

2003-10-13 Thread Bob Bishop
Hi, ISTR that AMD 486 had different cache arrangements from Intel. Just threw one out - I'll see if I can find another around here. -- Bob Bishop +44 (0)118 977 4017 [EMAIL PROTECTED] fax +44 (0)118 989 4254 ___ [EMAIL