On Fri, 10 Oct 2003, Tim Kientzle wrote:
TKHarti Brandt wrote:
TK Yes. When I read the C standard
TKfoo = data mask;
TK wouldn't also help, because there is no sequence point in this statement
TK except at the ;.
TK
TKBefore anyone takes this particular line of reasoning seriously,
TKI feel
On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote:
[ Andrew: Perhaps you can shed some light on how the necessary information
can be gathered on Alpha? My search was incomplete and I could not find
a reliable source for DEC's development manuals. ]
L1 cache information is in the CPU
Dear FreeBSD hackers,
I have posted this question to FreeBSD-questions earlier, but got no
reply. So I try here.
I'm having trouble getting my on-board Promise controller to work. I can
use atacontrol to build an array, but sysinstall won't detect the disk
pack.
Could this be a problem with the
Hi,
I may sound ignorant, but what is wrong with the FreeBSD-native aaccli
utility that can be downloaded from Adaptec (5400s_fbsd_cli_v10.zip)?
I have been using this for some time now with success.
May I suggest to make a port out of this as well?
Helge
Bruce M Simpson:
Hi,
I'm a FreeBSD
On Mon, Oct 13, 2003 at 05:20:31PM +0200, Helge Oldach wrote:
I may sound ignorant, but what is wrong with the FreeBSD-native aaccli
utility that can be downloaded from Adaptec (5400s_fbsd_cli_v10.zip)?
I have been using this for some time now with success.
May I suggest to make a port out
Peter Jeremy wrote:
On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote:
[ Andrew: Perhaps you can shed some light on how the necessary information
can be gathered on Alpha? My search was incomplete and I could not find
a reliable source for DEC's development manuals. ]
L1 cache
All,
Here are detailed design documents for determining cache and TLB
geometry across our currently supported processor architectures,
with recommendations outlined for implementation.
What I haven't addressed yet is how indirect consumers of the API might
use it, e.g. mutex consumers vs. UMA,
Hi,
ISTR that AMD 486 had different cache arrangements from Intel. Just threw
one out - I'll see if I can find another around here.
--
Bob Bishop +44 (0)118 977 4017
[EMAIL PROTECTED] fax +44 (0)118 989 4254
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