Hi Bruce,
A few thoughts on your API:
1) Rather than naming the struct's as l1, l2 etc, it may be more
orthogonal to use an array of cache entries like so
struct entry { ... } entries[MAX_ENTRIES]; where MAX_ENTRIES would be say,
8.
2) We could pass information back about whether the
Bruce M Simpson wrote this message on Mon, Oct 13, 2003 at 20:32 +0100:
i386 pc98 amd64
---
Action: Add code to identcpu.c to fill out hw_cacheinfo.
Cache discovery: Extended CPUID.
Static tables if 486-class machine. No cache on 386.
TLB discovery: Extended CPUID.
Static
On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote:
[ Andrew: Perhaps you can shed some light on how the necessary information
can be gathered on Alpha? My search was incomplete and I could not find
a reliable source for DEC's development manuals. ]
L1 cache information is in the CPU
Peter Jeremy wrote:
On Sun, Oct 12, 2003 at 08:57:52PM +0100, Bruce M Simpson wrote:
[ Andrew: Perhaps you can shed some light on how the necessary information
can be gathered on Alpha? My search was incomplete and I could not find
a reliable source for DEC's development manuals. ]
L1 cache
All,
Here are detailed design documents for determining cache and TLB
geometry across our currently supported processor architectures,
with recommendations outlined for implementation.
What I haven't addressed yet is how indirect consumers of the API might
use it, e.g. mutex consumers vs. UMA,
Hi,
ISTR that AMD 486 had different cache arrangements from Intel. Just threw
one out - I'll see if I can find another around here.
--
Bob Bishop +44 (0)118 977 4017
[EMAIL PROTECTED] fax +44 (0)118 989 4254
___
[EMAIL
All,
I came up with the attached text file today to summarize some of my
findings, after looking at various open source trees to see how they
handle run-time cache geometry detection.
Many will find it ironic that i386 is the easiest platform to deal with.
[ Andrew: Perhaps you can shed some
On Sat, Oct 11, 2003 at 01:58:27PM +1000, Peter Jeremy wrote:
If you do this, it may make sense to use the same names as MacOSX.
What if your hardware has different linesizes for different caches?
I noticed whilst peering in Apple Developer Notes that G5 has 128 byte
cache line size, and
On Sat, Oct 11, 2003 at 09:27:11AM +0100, Bruce M Simpson wrote:
OS X definitions considered too PowerPC centric. I think the best way
to handle all cases is thus:-
- Support 3 levels of cache.
Out of interest, do any systems other than the big-iron Alpha's use L3
cache? A quick look at the
On Sat, Oct 11, 2003 at 08:12:31PM +1000, Peter Jeremy wrote:
Out of interest, do any systems other than the big-iron Alpha's use L3
cache? A quick look at the code suggests that only L2 is coloured.
L3 cache is present on many MIPS and Pentium Xeon systems, as well as
PowerPC G4.
Do any
Hi -hackers,
I'm looking for ways that a userland program can determine the CPU
features available on an SMP machine -- processor model, stepping
numbers, supported features, cache organization etc.
For example, on some x86 processors the CPUID instruction could be
used to determine some of
On Fri, 10 Oct 2003, Joseph Koshy wrote:
Hi -hackers,
I'm looking for ways that a userland program can determine the CPU
features available on an SMP machine -- processor model, stepping
numbers, supported features, cache organization etc.
For example, on some x86 processors the CPUID
On Fri, Oct 10, 2003 at 03:36:40AM -0700, Joseph Koshy wrote:
I'm looking for ways that a userland program can determine the CPU
features available on an SMP machine -- processor model, stepping
numbers, supported features, cache organization etc.
What Silby said and have a look at the
On Fri, Oct 10, 2003 at 02:44:00PM +0100, Bruce M Simpson wrote:
On Fri, Oct 10, 2003 at 03:36:40AM -0700, Joseph Koshy wrote:
I'm looking for ways that a userland program can determine the CPU
features available on an SMP machine -- processor model, stepping
numbers, supported features,
Bruce M Simpson writes:
I've been thinking we should definitely make the cache organization
info available via sysctl. I am thinking we should do this to make
the UMA_ALIGN_CACHE definition mean something...
If you do this, it may make sense to use the same names as MacOSX.
Eg:
g51%
On Fri, Oct 10, 2003 at 03:09:47PM -0400, Andrew Gallatin wrote:
Bruce M Simpson writes:
I've been thinking we should definitely make the cache organization
info available via sysctl. I am thinking we should do this to make
the UMA_ALIGN_CACHE definition mean something...
If you do
On Fri, Oct 10, 2003 at 03:09:47PM -0400, Andrew Gallatin wrote:
Bruce M Simpson writes:
I've been thinking we should definitely make the cache organization
info available via sysctl. I am thinking we should do this to make
the UMA_ALIGN_CACHE definition mean something...
If you do this,
17 matches
Mail list logo
