Re: Fwd: 5-STABLE kernel build with icc broken

2005-04-02 Thread Bruce Evans
On Fri, 1 Apr 2005, Matthew Dillon wrote: :The use of the XMM registers is a cpu optimization. Modern CPUs, :especially AMD Athlon and Opterons, are more efficient with 128 bit :moves then with 64 bit moves. I experimented with all sorts of :configurations, including the use of

Re: Fwd: 5-STABLE kernel build with icc broken

2005-04-01 Thread Bruce Evans
On Thu, 31 Mar 2005, Matthew Dillon wrote: I didn't mean to get into the kernel's use of the FPU, but... All I really did was implement a comment that DG had made many years ago in the PCB structure about making the FPU save area a pointer rather then hardwiring it into the PCB. ISTR

Re: Fwd: 5-STABLE kernel build with icc broken

2005-04-01 Thread Matthew Dillon
:The use of the XMM registers is a cpu optimization. Modern CPUs, :especially AMD Athlon and Opterons, are more efficient with 128 bit :moves then with 64 bit moves. I experimented with all sorts of :configurations, including the use of special data caching instructions, :

Re: Fwd: 5-STABLE kernel build with icc broken

2005-04-01 Thread Matthew Dillon
Here is the core of the FPU setup and restoration code for the kernel bcopy in DragonFly, from i386/bcopy.s. DragonFly uses the TD_SAVEFPU-is-a-pointer method that was outlined in the original comment in the FreeBSD code. I further enhance the algorithm to guarentee that the

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-31 Thread Peter Jeremy
On Thu, 2005-Mar-31 17:17:58 +1000, Bruce Evans wrote: On the i386 (and probably most other CPUs), you can place the FPU into am unavailable state. This means that any attempt to use it will trigger a trap. The kernel will then restore FPU state and return. On a normal system call, if the FPU

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-31 Thread Bruce Evans
On Wed, 30 Mar 2005, David Schultz wrote: On Wed, Mar 30, 2005, Peter Jeremy wrote: On Tue, 2005-Mar-29 22:57:28 -0500, jason henson wrote: Later in that thread they discuss skipping the restore state to make things faster. The minimum buffer size they say this will be good for is between 2-4k.

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-31 Thread Bruce Evans
On Thu, 31 Mar 2005, Peter Jeremy wrote: On Thu, 2005-Mar-31 17:17:58 +1000, Bruce Evans wrote: I still think fully lazy switching (c2) is the best general method. I think it depends on the FP workload. It's a definite win if there is exactly one FP thread - in this case the FPU state never

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-31 Thread Matthew Dillon
All I really did was implement a comment that DG had made many years ago in the PCB structure about making the FPU save area a pointer rather then hardwiring it into the PCB. This greatly reduces the complexity of work required to allow the kernel to 'borrow' the FPU. It

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-30 Thread Peter Jeremy
On Tue, 2005-Mar-29 22:57:28 -0500, jason henson wrote: Later in that thread they discuss skipping the restore state to make things faster. The minimum buffer size they say this will be good for is between 2-4k. Does this make sense, or am I showing my ignorance?

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-30 Thread David Schultz
On Wed, Mar 30, 2005, Peter Jeremy wrote: On Tue, 2005-Mar-29 22:57:28 -0500, jason henson wrote: Later in that thread they discuss skipping the restore state to make things faster. The minimum buffer size they say this will be good for is between 2-4k. Does this make sense, or am I

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-29 Thread Peter Jeremy
On Mon, 2005-Mar-28 23:23:19 -0800, David Leimbach wrote: meant to send this to the list too... sorry Are you implying DragonFly uses FPU/SIMD? For that matter does any kernel? I believe it does use SIMD for some of it's fast memcopy stuff for it's messaging system actually. I remember Matt

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-29 Thread David Malone
On Tue, Mar 29, 2005 at 09:11:07PM +1000, Peter Jeremy wrote: That's almost a year ago and specifically for the amd64. Does anyone know what the results were? I had a quick dig around on cvsweb this morning:

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-29 Thread Devon H. O'Dell
On Tue, Mar 29, 2005 at 02:12:53PM +0100, David Malone wrote: On Tue, Mar 29, 2005 at 09:11:07PM +1000, Peter Jeremy wrote: That's almost a year ago and specifically for the amd64. Does anyone know what the results were? I had a quick dig around on cvsweb this morning:

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-29 Thread David Leimbach
On Tue, 29 Mar 2005 21:11:07 +1000, Peter Jeremy [EMAIL PROTECTED] wrote: On Mon, 2005-Mar-28 23:23:19 -0800, David Leimbach wrote: meant to send this to the list too... sorry Are you implying DragonFly uses FPU/SIMD? For that matter does any kernel? I believe it does use SIMD for some of

Re: Fwd: 5-STABLE kernel build with icc broken

2005-03-29 Thread jason henson
Peter Jeremy wrote: On Mon, 2005-Mar-28 23:23:19 -0800, David Leimbach wrote: meant to send this to the list too... sorry Are you implying DragonFly uses FPU/SIMD? For that matter does any kernel? I believe it does use SIMD for some of it's fast memcopy stuff for it's messaging

Fwd: 5-STABLE kernel build with icc broken

2005-03-28 Thread David Leimbach
meant to send this to the list too... sorry Are you implying DragonFly uses FPU/SIMD? For that matter does any kernel? I believe it does use SIMD for some of it's fast memcopy stuff for it's messaging system actually. I remember Matt saying he was working on it.