Re: Possible instruction pipelining problem between HT's on the same die ? (fwd)

Hi, I did a fair amount of lock-free programming during my PhD and for Xen, so I may be able to shed some light on this situation. OTOH I may also be confused: the x86 memory model is poorly specified and the reference manuals are often badly written and misleading. I'll address the points

Possible instruction pipelining problem between HT's on the same die ?

I've been tracking down a crash one of our users gets occassionally. He has a quad Intel(R) XEON(TM) CPU 2.00GHz (1996.61-MHz 686-class CPU) system. After getting a few of these crashes he pulled three of the four cpus out. But with just one physical cpu, with HTT turned on

Re: Possible instruction pipelining problem between HT's on the same die ?

Matthew Dillon wrote: I'm even more confused because this bug is occuring between two logical cpus on the same physical die. Is write ordering not guarenteed with respect to the other logical cpu? Can one logical cpu prefetch data early then then becomes obsolete by the time

Re: Possible instruction pipelining problem between HT's on the same die ?

On Fri, 2005-06-03 at 16:57, Matthew Dillon wrote: I've been tracking down a crash one of our users gets occassionally. He has a quad Intel(R) XEON(TM) CPU 2.00GHz (1996.61-MHz 686-class CPU) system. After getting a few of these crashes he pulled three of the four cpus

Re: Possible instruction pipelining problem between HT's on the same die ?

:This is normal behaviour. :Take a look at IA-32 Intel Developers ... Vol 3, :Section: 7.2.2 for details + solutions. : :Stephan Ok.. that section seems to indicate that speculative reads can pass writes, but it also says that the pipeline sniffs the address within the processor

Re: Possible instruction pipelining problem between HT's on the same die ?

Matthew Dillon wrote this message on Fri, Jun 03, 2005 at 13:57 -0700: I've been tracking down a crash one of our users gets occassionally. He has a quad Intel(R) XEON(TM) CPU 2.00GHz (1996.61-MHz 686-class CPU) system. After getting a few of these crashes he pulled three of

Re: Possible instruction pipelining problem between HT's on the same die ?

On Fri, 2005-06-03 at 18:47, Matthew Dillon wrote: :This is normal behaviour. :Take a look at IA-32 Intel Developers ... Vol 3, :Section: 7.2.2 for details + solutions. : :Stephan Ok.. that section seems to indicate that speculative reads can pass writes, but it also says that

Re: Possible instruction pipelining problem between HT's on the same die ?

:have you put a SFENCE between write A and write B? You never tell us :where you've tried to put the various fence instructions... : :-- : John-Mark Gurney Voice: +1 415 225 5579 No, I haven't tried doing that because both the AMD and Intel manuals make it

Re: Possible instruction pipelining problem between HT's on the same die ?

Matthew Dillon wrote: [...] It seems so unlikely that this could occur across physical cpus that I was not surprised at all by this. But 16 instructions seemed unlikely to me. The only scenario I can come up with is that the READ SIDE on the HT cpu (logical cpu #1) did a