On Wed, Jun 25, 2003, David Gilbert wrote:
Matthew == Matthew Dillon [EMAIL PROTECTED] writes:
Matthew The primes are designed such that the page allocation
Matthew code covers *ALL* the free lists in the array, so it will
Matthew still be able to find any available free pages if its
David Schultz wrote:
On Wed, Jun 25, 2003, David Gilbert wrote:
Matthew == Matthew Dillon [EMAIL PROTECTED] writes:
Matthew The primes are designed such that the page allocation
Matthew code covers *ALL* the free lists in the array, so it will
Matthew still be able to find any
Bruce M Simpson wrote:
Something occurred to me whilst I was re-reading the 'Design Elements'
article over the weekend; our page coloring algorithm, as it stands,
might not be optimal for non-Intel CPUs.
Actually, it does very well for most architectures, and was originally
developed into
Bruce M Simpson wrote:
Yes, that was what I was really getting at; if you look at how PQ_L2_SIZE
is computed from PQ_CACHESIZE, it implies 4-way set associative is
the default optimization. This is fine for Intel chips but not for AMD ones.
FWIW, I'd like to see this automatically optimized,
Matthew == Matthew Dillon [EMAIL PROTECTED] writes:
Matthew The primes are designed such that the page allocation
Matthew code covers *ALL* the free lists in the array, so it will
Matthew still be able to find any available free pages if its first
Matthew choice(s) are empty.
Matthew
On Tue, Jun 24, 2003, Bruce M Simpson wrote:
Hi all,
Something occurred to me whilst I was re-reading the 'Design Elements'
article over the weekend; our page coloring algorithm, as it stands,
might not be optimal for non-Intel CPUs.
Spiel:
- Dillon's VM article talks about L1 cache
On Tue, Jun 24, 2003 at 06:17:48AM -0700, David Schultz wrote:
The coloring is based on the size and associativity of the cache,
not its speed relative to the processor's.
Yes. My comments were originally aimed at the fact the article seemed to
imply we were coloring for L1 rather than L2,
: - The page queue structures are sized according to these
:defines at boot-time.
:
: - If someone could fill me in on how the primes are arrived at that
:would be very helpful.
:
:Comments/discussion/correction welcomed, it would be good to get some
:feedback on this before I start
On Tue, Jun 24, 2003 at 02:38:13PM +0100, Bruce M Simpson wrote:
The names of the definitions as they stand are perhaps slightly misleading
in this respect. PQ_L2_SIZE might be better renamed PQ_SETSIZE and defined
in terms of PQ_CACHESIZE/PQ_NSETS.
[snip]
Bikeshed, but it would still be nice
Matthew Dillon wrote:
For example, prime number 3 an array size 8 will scan the array in
the following order N = (N + PRIME) (ARRAY_SIZE_MASK).
N = (N + 3) 7:
0 3 6 1 4 7 2 5 ... 0
As you can see, all the array entries are covered before the sequence
repeats. Only
:
:Matthew Dillon wrote:
: For example, prime number 3 an array size 8 will scan the array in
: the following order N = (N + PRIME) (ARRAY_SIZE_MASK).
: N = (N + 3) 7:
:
: 0 3 6 1 4 7 2 5 ... 0
:
: As you can see, all the array entries are covered before the sequence
:
Hi,
:U Actually, Matt, the property you've stated is much more
:common than you seem to believe. If you generate a sequence
:N = ( N + Stride ) % ArraySize
:then you will visit every element of (0 ... ArraySize-1) as long as
I was just answering a question. Most people
12 matches
Mail list logo
