Re: boot hang without xhci [updated patch]

2011-07-22 Thread Hans Petter Selasky
On Friday 22 July 2011 16:43:51 Mike Tancsa wrote:
> On 7/22/2011 4:22 AM, Hans Petter Selasky wrote:
> > Please try the attached patch for /sys/dev/pci:
> Looks good! Its able to boot up with and without xhci loaded.

Committed! Thanks for testing.

--HPS
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Re: boot hang without xhci [updated patch]

2011-07-22 Thread Mike Tancsa
On 7/22/2011 4:22 AM, Hans Petter Selasky wrote:
> 
> Please try the attached patch for /sys/dev/pci:


Looks good! Its able to boot up with and without xhci loaded.

0(ich10)# patch < p
Hmm...  Looks like a unified diff to me...
The text leading up to this was:
--
|=== pci.c
|==
|--- pci.c  (revision 224243)
|+++ pci.c  (local)
--
Patching file pci.c using Plan A...
Hunk #1 succeeded at 62.
Hunk #2 succeeded at 2782 (offset -175 lines).
Hunk #3 succeeded at 2890 (offset -175 lines).
Hmm...  Ignoring the trailing garbage.
done
0(ich10)# 


none3@pci0:0:31:3:  class=0x0c0500 card=0x20088086 chip=0x1c228086 rev=0x04 
hdr=0x00
vendor = 'Intel Corporation'
class  = serial bus
subclass   = SMBus
bar   [10] = type Memory, range 64, base 0xfe624000, size 256, enabled
bar   [20] = type I/O Port, range 32, base 0xf040, size 32, enabled
none4@pci0:2:0:0:   class=0x0c0330 card=0x20088086 chip=0x01941033 rev=0x03 
hdr=0x00
vendor = 'NEC Electronics Hong Kong'
class  = serial bus
subclass   = USB
cap 01[50] = powerspec 3  supports D0 D3  current D0
cap 05[70] = MSI supports 8 messages, 64 bit 
cap 11[90] = MSI-X supports 8 messages in map 0x10
cap 10[a0] = PCI-Express 2 endpoint max data 128(128) link x1(x1)
ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected
ecap 0003[140] = Serial 1 
ecap 0018[150] = unknown 1


I can do a kldload post boot of xhci as well as boot with it loaded at boot 
time from /boot/loader.conf.


xhci0@pci0:2:0:0:   class=0x0c0330 card=0x20088086 chip=0x01941033 rev=0x03 
hdr=0x00
vendor = 'NEC Electronics Hong Kong'
class  = serial bus
subclass   = USB
cap 01[50] = powerspec 3  supports D0 D3  current D0
cap 05[70] = MSI supports 8 messages, 64 bit 
cap 11[90] = MSI-X supports 8 messages in map 0x10
cap 10[a0] = PCI-Express 2 endpoint max data 128(128) link x1(x1)
ecap 0001[100] = AER 1 0 fatal 0 non-fatal 1 corrected
ecap 0003[140] = Serial 1 
ecap 0018[150] = unknown 1


---Mike


-- 
---
Mike Tancsa, tel +1 519 651 3400
Sentex Communications, m...@sentex.net
Providing Internet services since 1994 www.sentex.net
Cambridge, Ontario Canada   http://www.tancsa.com/
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Re: boot hang without xhci [updated patch]

2011-07-22 Thread Hans Petter Selasky
On Friday 22 July 2011 01:38:33 Mike Tancsa wrote:
> More for the archives in case anyone else runs into this.
> 
> We got a new desktop board in that we were testing out netbooting and
> noticed that without xhci loaded in the kernel the box hangs with the
> last thing being initialized em0 (full dmesg etc at
> http://www.tancsa.com/xhci.txt)
> 
> Its an Intel DQ67SW
> 
> 
> ata2: [ITHREAD]
> ata3:  on atapci0
> ata3: [ITHREAD]
> pci0:  at device 22.3 (no driver attached)
> em0:  port 0xf080-0xf09f mem
> 0xfe60-0xfe61,0xfe628000-0xfe628fff irq 20 at device 25.0 on pci0
> em0: Using an MSI interrupt
> em0: [FILTER]
> em0: Ethernet address: 00:22:4d:52:04:46
> 
> with usb 3 disabled in the BIOS, or with xhci loaded, all boots fine as
> shown below.

Please try the attached patch for /sys/dev/pci:

--HPS
=== pci.c
==
--- pci.c	(revision 224243)
+++ pci.c	(local)
@@ -62,6 +62,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -2956,6 +2957,68 @@
 	bus_release_resource(self, SYS_RES_MEMORY, rid, res);
 }
 
+/* Perform early XHCI takeover from SMM. */
+static void
+xhci_early_takeover(device_t self)
+{
+	struct resource *res;
+	uint32_t cparams;
+	uint32_t eec;
+	uint8_t eecp;
+	uint8_t bios_sem;
+	uint8_t offs;
+	int rid;
+	int i;
+
+	rid = PCIR_BAR(0);
+	res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (res == NULL)
+		return;
+
+	cparams = bus_read_4(res, XHCI_HCSPARAMS0);
+
+	eec = -1;
+
+	/* Synchronise with the BIOS if it owns the controller. */
+	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
+	eecp += XHCI_XECP_NEXT(eec) << 2) {
+		eec = bus_read_4(res, eecp);
+
+		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
+			continue;
+
+		bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
+		if (bios_sem == 0)
+			continue;
+
+		if (bootverbose)
+			printf("xhci early: "
+			"SMM active, request owner change\n");
+
+		bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
+
+		/* wait a maximum of 5 second */
+
+		for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
+			DELAY(1000);
+			bios_sem = bus_read_1(res, eecp +
+			XHCI_XECP_BIOS_SEM);
+		}
+
+		if (bios_sem != 0) {
+			if (bootverbose)
+printf("xhci early: "
+"SMM does not respond\n");
+		}
+
+		/* Disable interrupts */
+		offs = bus_read_1(res, XHCI_CAPLENGTH);
+		bus_write_4(res, offs + XHCI_USBCMD, 0);
+		bus_read_4(res, offs + XHCI_USBSTS);
+	}
+	bus_release_resource(self, SYS_RES_MEMORY, rid, res);
+}
+
 void
 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
 {
@@ -3002,7 +3065,9 @@
 
 	if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
 	pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
-		if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
+		if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
+			xhci_early_takeover(dev);
+		else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
 			ehci_early_takeover(dev);
 		else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
 			ohci_early_takeover(dev);
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