[Freedreno] [PATCH 0/6] Preemption support for A6xx targets

This is a revised preemption support patchset follows Jordan's recent "drm/msm: Add A6XX device support" patch series. Preemption allows the GPU to switch to a higher priority ringbuffer when one is ready, thereby improving user experience. A6xx hardware supports various preemption levels each

[Freedreno] [PATCH 6/6] drm/msm/A6xx: Enable L1 preemption level

This patch enables L1 level which is a finer grained preemption at either a draw call or a bin boundary. The worst case switching latency is higher in this case but that is a trade off we make for enabling faster preemption. Signed-off-by: Sharat Masetty ---

[Freedreno] [PATCH 3/6] drm/msm/A6xx: Implement preemption for A6XX targets

This patch implements preemption feature for A6xx targets, this allows the GPU to switch to a higher priority ringbuffer if one is ready. A6XX hardware as such supports multiple levels of preemption granularities, ranging from coarse grained(ringbuffer level) to a more fine grained such as

[Freedreno] [PATCH 4/6] drm/msm/A6xx: Enable preemption for A6xx targets

This patch simply increases the number of available ringbuffers, therefore enabling preemption. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Freedreno] [PATCH 5/6] drm/msm/Adreno: Refactor some preemption code

The preemption state machine related code is same across Adreno targets, so move the common code to a common header file to avoid code duplication. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 26 ---

[Freedreno] [PATCH 1/6] drm/msm: Add submitqueue setup and close

This patch adds a bit of infrastructure to give the different Adreno targets the flexibility to setup the submitqueues per their needs. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/msm_gpu.h | 7 +++ drivers/gpu/drm/msm/msm_submitqueue.c | 15

[Freedreno] [PATCH 2/6] drm/msm: Add new PM4 type7 opcodes

This patch adds the following two opcodes: CP_SET_MARKER opcode is a way to tell CP the current mode of GPU operation(useful if preemption is in use). CP_SET_PSEUDO_REG opcode will instruct CP to set a bunch of internal CP registers, again useful for the preemption save/restore sequence.