Hi Sravanthi,
On Wed, Oct 10, 2018 at 02:54:33PM +0530, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where
On Tue, Nov 06, 2018 at 03:11:48PM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-02 14:45:34)
> > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm
> > *pll_10nm)
> > char clk_name[32], parent[32], vco_name[32];
> > c
On Tue, Nov 06, 2018 at 03:09:40PM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-02 14:45:33)
> > Allow the 10nm PHY driver to get the ref clock from the DT.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Documentation/devicetree
On Thu, Nov 08, 2018 at 02:04:31PM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Nov 2, 2018 at 2:45 PM Matthias Kaehlcke wrote:
> >
> > Get the PHY ref clock from the device tree instead of hardcoding
> > its name and rate.
> >
> > Signed-off-by: Matthias
On Mon, Nov 05, 2018 at 12:33:04PM -0500, Sean Paul wrote:
> On Fri, Nov 02, 2018 at 02:45:34PM -0700, Matthias Kaehlcke wrote:
> > Get the PHY ref clock from the device tree instead of hardcoding
> > its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke
>
Get the PHY ref clock from the device tree instead of hardcoding
its name and rate.
Signed-off-by: Matthias Kaehlcke
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b
Allow the 10nm PHY driver to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b/Documentation/devicetree
On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > index 71fe60e5f01f1..032bf3e8614bd 100644
> >
On Tue, Nov 27, 2018 at 09:56:46PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
>
> In the case of the 14nm P
PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8):
dt-bindings: msm/dsi: Add ref clock for PHYs
drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
drm/msm/dsi: 28nm PHY: Get ref clock from
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
arch
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
---
Changes in V3:
- added note that the ref clock is only required for new DTS
files/entries
Changes in v2:
- add the ref clock for all PHYs, not only the 10nm one
- updated commit message
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- patch added to the series
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added note
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
(https://patchwork.kernel
On Tue, Dec 04, 2018 at 08:48:22AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
> > Add 'xo_board' as ref clock for the DSI PHY, it was previously
> > hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
>
> Why is driver in quotes?
It's not
On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate. Use default values if the ref
> > clock is not specified
On Tue, Nov 27, 2018 at 09:41:39PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Allow the PHY drivers to get the ref clock from the DT.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > C
On Tue, Nov 27, 2018 at 10:00:50PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> > @@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll
> > *pll)
> > static int pll_28nm_register(st
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- patch added to the series
---
arch/arm
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
Chnages in v4:
- added "Reviewed-by" tags from Stephen and Doug
Changes in v3:
- added note that the ref clock is only required f
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- added 'Reviewed
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
in v3:
- keep supporting DTs without ref clock for the 28nm and the 28nm
8960 PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8):
dt-bindings: msm/dsi: Add ref clock for PHYs
drm/msm/dsi: 28nm 8960
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v4:
- none
Changes in v3:
- fixed check
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 29 +++---
1 file changed, 20 insertions(+), 9 deletions
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions
The MSM DSI PHY drivers currently hardcode the name and the rate of
the PHY ref clock. Get the ref clock from the device tree instead.
Note: testing of this series was limited to SDM845 and the 10nm PHY
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (7
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- add the ref clock for all PHYs, not only the 10nm one
- updated commit message
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- patch added to the series
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
(https://patchwork.kernel.org/patch/10666253/)
Changes in v
Hi Niklas,
On Wed, Dec 12, 2018 at 11:07:17PM +0100, Niklas Cassel wrote:
> On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
> >
> > Signe
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
Changes in v5:
- none
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- none
Changes in v4:
- added 'Reviewed-by: Stephen Boyd ' tag
Changes in v3:
- patch added
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
Reviewed-by: Stephen Boyd
---
based on "[v6] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
:
- always use parent rate for 28nm and 28nm 8960 PHYs
Major changes in v3:
- keep supporting DTs without ref clock for the 28nm and the 28nm
8960 PHYs
- added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2:
- apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
-
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Changes in v5:
- added "Reviewed-by: Rob Herring " tag
Changes in v4:
- added "Reviewed-by" tags f
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd tag
---
Changes in v5:
- added missing return keyword in msm_dsi_pll_28nm_init()
- added "Reviewed-by: Stephen Boyd " tag
Cha
Hi,
this series has gone through multiple rounds of review and there are
no outstanding comments. It seems it should be ready to land, or is
there anything left that needs to be addressed?
Thanks
Matthias
On Wed, Dec 19, 2018 at 03:55:20PM -0800, Matthias Kaehlcke wrote:
> The MSM DSI
Hi Sharat,
on which tree is this patch based on? It does not apply against
qcom/arm64-for-5.6-to-be-rebased.
In one of my repos which has a non-upstream Qualcomm tree as remote git can
make sense of the hashes in the index line, however the parent of your patch
looks quite different from the
Hi,
On Fri, Nov 29, 2019 at 12:35:05PM +0530, Harigovindan P wrote:
> Changes in v1:
> -Modify commit text to indicate DSI version and SOC detail(Jeffrey
> Hugo).
> -Splitting visionox panel driver code out into a
>different patch(set), since panel drivers are merged into
>
On Mon, Dec 02, 2019 at 01:48:57PM +, Chandan Uddaraju wrote:
> Add the needed displayPort files to enable DP driver
> on msm target.
>
> "dp_display" module is the main module that calls into
> other sub-modules. "dp_drm" file represents the interface
> between DRM framework and DP driver.
>
On Mon, Dec 02, 2019 at 01:48:27PM +, Chandan Uddaraju wrote:
> Add the needed DP PLL specific files to support
> display port interface on msm targets.
>
> The DP driver calls the DP PLL driver registration.
> The DP driver sets the link and pixel clock sources.
>
> Changes in v2:
> --
On Thu, Feb 27, 2020 at 01:54:33PM -0800, Matthias Kaehlcke wrote:
> On Mon, Dec 02, 2019 at 01:48:57PM +, Chandan Uddaraju wrote:
> > Add the needed displayPort files to enable DP driver
> > on msm target.
> >
> > "dp_display" module is the main module
Hi,
On Thu, Jan 02, 2020 at 04:32:07PM +0530, Sharat Masetty wrote:
> From: Jordan Crouse
>
> Pass the propposed io_pgtable_cfg to the implementation specific
> init_context() function to give the implementation an opportunity to
> to modify it before it gets passed to io-pgtable.
>
>
Hi Jordan,
On Thu, Jan 23, 2020 at 09:42:36AM -0700, Jordan Crouse wrote:
> Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") missed
> updating the VBIF flush in a6xx_gmu_shutdown and instead
> inserted the new sequence into a6xx_pm_suspend along with a redundant
> GMU idle.
>
> Move
Hi,
On Tue, Jan 28, 2020 at 06:54:44PM +0530, Harigovindan P wrote:
> Add display, DSI hardware DT nodes for sc7180.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v1:
> -Added display DT nodes for sc7180
> Changes in v2:
> -Renamed node names
> -Corrected code
Hi,
On Tue, Jan 28, 2020 at 07:06:57PM +0530, Harigovindan P wrote:
> Adding dsi controller and phy entries for idp dt.
>
> Signed-off-by: Harigovindan P
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 56
> +
> 1 file changed, 56 insertions(+)
>
> diff
On Thu, Feb 20, 2020 at 01:42:22PM +0530, Sharat Masetty wrote:
> This patch adds a clock definition needed for powering on the GPU TBUs
> and the GPU TCU.
>
> Signed-off-by: Sharat Masetty
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
> 1 file changed, 3 insertions(+)
On Tue, Feb 11, 2020 at 05:07:35PM +0530, Harigovindan P wrote:
> subject: arm64: dts: sc7180: add dsi controller and phy entries for idp dts
nit: 'dts' at the end is redundant, the prefixes make it clear that this
is about DT entries.
Also the message isn't really concise. The main entries for
Hi,
On Tue, Jan 07, 2020 at 04:59:56PM +0530, Harigovindan P wrote:
> Subject: dt-bindings: display: add sc7180 panel variant
>
> Add a compatible string to support sc7180 panel version.
The sc7180 is a SoC, I suppose you are referring to the sc7180-idp, a
board based on this SoC. But even with
Hi,
On Fri, Mar 06, 2020 at 04:06:28PM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
>
be to add
something like this before 'err_dsi_attach':
err_set_load:
mipi_dsi_detach(dsi);
and then just do 'goto err_set_load' in the error paths.
> +
> + ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
> + if (ret) {
> + mipi_dsi_det
Hi,
checkpatch finds multiple errors with this patch, as Sam reported on
https://patchwork.kernel.org/cover/11461945/. Please fix those and
send a new version (not sure which version number this should be (v11?),
this series is a bit confusing in this aspect).
Please also double check if there
On Mon, Mar 16, 2020 at 09:46:47AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
Reviewed-by: Matthias Kaehlcke
___
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On Mon, Mar 30, 2020 at 09:25:11PM +0200, Sam Ravnborg wrote:
> Hi Matthias.
>
> On Sun, Mar 29, 2020 at 10:44:17AM -0700, Matthias Kaehlcke wrote:
> > Hi Sam,
> >
> > On Sat, Mar 28, 2020 at 09:40:47PM +0100, Sam Ravnborg wrote:
> > > Hi Harigovindan
> &
Hi Sam,
On Sat, Mar 28, 2020 at 09:40:47PM +0100, Sam Ravnborg wrote:
> Hi Harigovindan
>
> On Fri, Mar 27, 2020 at 01:06:34PM +0530, Harigovindan P wrote:
> > Adding support for visionox rm69299 panel driver and adding bindings for
> > the same panel.
> >
> > Harigovindan P (2):
> >
On Wed, Apr 01, 2020 at 02:47:45PM +0530, Krishna Manikandan wrote:
> Subject: arm64: dts: sc7180: define interconnects for sc7180 target
Please be more specific about which interconnect entries are added.
Also no need to repeat 'sc7180', it is already clear from the prefix.
error: corrupt patch at line 379
Patch failed at 0001 drm/panel: add support for rm69299 visionox panel driver
Besides the broken format:
Reviewed-by: Matthias Kaehlcke
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On Fri, Feb 14, 2020 at 10:49:37AM -0800, Matthias Kaehlcke wrote:
> On Tue, Feb 11, 2020 at 05:07:35PM +0530, Harigovindan P wrote:
>
> > subject: arm64: dts: sc7180: add dsi controller and phy entries for idp dts
>
> nit: 'dts' at the end is redundant, the pref
On Thu, May 14, 2020 at 05:39:57PM -0700, Matthias Kaehlcke wrote:
> On Thu, May 14, 2020 at 04:24:17PM +0530, Sharat Masetty wrote:
> > This patch changes the plumbing to send the devfreq recommended opp rather
> > than the frequency. Also consolidate and rearrange the code
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> This patches replaces the previously used static DDR vote and uses
> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> GPU frequency.
>
> Signed-off-by: Sharat Masetty
> ---
>
On Thu, May 14, 2020 at 04:24:16PM +0530, Sharat Masetty wrote:
> From: Sibi Sankar
>
> Add and export 'dev_pm_opp_set_bw' to set the bandwidth
> levels associated with an OPP for a given frequency.
Wait, this looks very much like Sibi's patch from v4 of the "DDR/L3
Scaling support on SDM845
On Thu, May 14, 2020 at 04:24:17PM +0530, Sharat Masetty wrote:
> This patch changes the plumbing to send the devfreq recommended opp rather
> than the frequency. Also consolidate and rearrange the code in a6xx to set
> the GPU frequency and the icc vote in preparation for the upcoming
> changes
; ;
> + opp-peak-kBps = <3072000>;
> };
ditto
> opp-18000 {
> opp-hz = /bits/ 64 <18000>;
>
Hi Sharat,
On Thu, May 14, 2020 at 04:24:14PM +0530, Sharat Masetty wrote:
> Subject: arm64: dts: qcom: sc7180: Add interconnect bindings for GPU
>
> This patch adds the interconnect bindings to the GPU node. This enables
> the GPU->DDR path bandwidth voting.
This patch doesn't add any
On Thu, May 14, 2020 at 04:24:13PM +0530, Sharat Masetty wrote:
> Subject: [PATCH 0/6] Add support for GPU DDR BW scaling
For anything but the first version the subject (for all patches) should
include the version (i.e. [v2, 0/6], etc for this series).
> This is a rework of my previous series
Hi,
On Mon, Mar 09, 2020 at 10:53:04AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
>
Hi,
On Thu, Oct 15, 2020 at 12:07:01AM +0530, man...@codeaurora.org wrote:
> On 2020-10-14 18:59, Akhil P Oommen wrote:
> > On 10/9/2020 10:27 PM, Matthias Kaehlcke wrote:
> > > On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
> > > > Hi,
> > &g
On Fri, Oct 09, 2020 at 08:05:10AM -0700, Doug Anderson wrote:
> Hi,
>
> On Thu, Oct 8, 2020 at 10:10 AM Akhil P Oommen wrote:
> >
> > Add cooling-cells property and the cooling maps for the gpu tzones
> > to support GPU cooling.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> >
Hi Jonathan,
On Tue, Jun 30, 2020 at 11:08:41PM -0400, Jonathan Marek wrote:
> Check for EPROBE_DEFER instead of silently not using icc if the msm driver
> probes before the interconnect driver.
Agreed with supporting deferred ICC probing.
> Only check for EPROBE_DEFER because of_icc_get can
On Wed, Jul 01, 2020 at 01:13:34PM -0400, Jonathan Marek wrote:
> On 7/1/20 1:12 PM, Matthias Kaehlcke wrote:
> > Hi Jonathan,
> >
> > On Tue, Jun 30, 2020 at 11:08:41PM -0400, Jonathan Marek wrote:
> > > Check for EPROBE_DEFER instead of silently not using icc
On Thu, Jun 18, 2020 at 07:38:41PM +0530, Kalyan Thota wrote:
> This change adds support to scale src clk and bandwidth as
> per composition requirements.
>
> Interconnect registration for bw has been moved to mdp
> device node from mdss to facilitate the scaling.
>
> Changes in v1:
> - Address
On Tue, Jul 14, 2020 at 04:39:47PM +0530, kalya...@codeaurora.org wrote:
> On 2020-07-14 06:42, Matthias Kaehlcke wrote:
> > On Thu, Jun 18, 2020 at 07:38:41PM +0530, Kalyan Thota wrote:
> > > This change adds support to scale src clk and bandwidth as
> > > p
ew iterations without
this patch.
Reported-by: Matthias Kaehlcke
Tested-by: Matthias Kaehlcke
On which tree is this patch based on? I had to apply it manually because
'git am' is unhappy when I try to apply it:
error: sha1 information is lacking or useless
(drivers/gpu/drm/msm/adreno/a6xx_g
Hi,
On Thu, Jun 18, 2020 at 10:52:09AM -0700, Rob Clark wrote:
> On Fri, Jun 5, 2020 at 9:26 PM Sharat Masetty wrote:
> >
> > This patch changes the plumbing to send the devfreq recommended opp rather
> > than the frequency. Also consolidate and rearrange the code in a6xx to set
> > the GPU
xi_clk already unprepared
Tested-by: Matthias Kaehlcke
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reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x280>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
I'm not an expect, but this looks sane to me and it's very similar to the
SC7180 config.
Reviewed-by: Matthias Kaehlcke
On Wed, Aug 18, 2021 at 03:57:04PM +0530, Krishna Manikandan wrote:
> From: Sankeerth Billakanti
>
> Add edp controller and phy DT nodes for sc7280.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 127
> ++-
> 1 file
On Thu, Aug 12, 2021 at 05:38:01AM +0530, Sankeerth Billakanti wrote:
> The eDP controller on SC7280 is similar to the eDP/DP controllers
> supported by the current driver implementation.
>
> SC7280 supports one EDP and one DP controller which can operate
> concurrently.
>
> The following are
On Thu, Aug 12, 2021 at 05:38:02AM +0530, Sankeerth Billakanti wrote:
> The Qualcomm SC7280 platform supports an eDP controller, add
> compatible string for it to msm/binding.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3
On Tue, Feb 08, 2022 at 08:48:43PM +0530, Sankeerth Billakanti wrote:
> Enable the eDP display panel support without HPD on sc7280 platform.
>
> Signed-off-by: Sankeerth Billakanti
> ---
>
> Changes in v2:
> - sort node references alphabetically
> - improve readability
> - move the pwm
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