Some drivers need to apply some workarounds
> - * for gpu-specific vblank irq quirks if flag is set.
> + * in_vblank_irq:
> + * True when called from drm_crtc_handle_vblank(). Some drivers
> + * need to apply some workarounds for gpu-specific vblank irq quirks
> + * if flag is set.
>*
>* Returns:
>*
> @@ -322,7 +321,7 @@ struct drm_driver {
> bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe,
>int *max_error,
>struct timeval *vblank_time,
> - unsigned flags);
> + bool in_vblank_irq);
>
> /* these have to be filled in */
>
> diff --git a/include/drm/drm_irq.h b/include/drm/drm_irq.h
> index f0d5ccf9b282..445406efb8dc 100644
> --- a/include/drm/drm_irq.h
> +++ b/include/drm/drm_irq.h
> @@ -156,7 +156,7 @@ u32 drm_accurate_vblank_count(struct drm_crtc *crtc);
> bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
> unsigned int pipe, int *max_error,
> struct timeval *vblank_time,
> -unsigned flags,
> +bool in_vblank_irq,
> const struct drm_display_mode *mode);
> void drm_calc_timestamping_constants(struct drm_crtc *crtc,
>const struct drm_display_mode *mode);
>
Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
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rtc_get_scanoutpos(struct drm_device *dev,
> unsigned int crtc_id,
> unsigned int flags, int *vpos, int *hpos,
> ktime_t *stime, ktime_t *etime,
> const struct drm_display_mode *mode);
> -bool
c4/vc4_drv.h | 2 +-
> include/drm/drmP.h| 1 -
> include/drm/drm_drv.h | 7 ++---
> include/drm/drm_irq.h | 10 +++
> 14 files changed, 64 insertions(+), 79 deletions(-)
>
[...]
With the commi
could
> + * not be read out.
>*
>* FIXME:
>*
> @@ -280,10 +274,10 @@ struct drm_driver {
>* move it to drm_crtc_helper_funcs, like all the other
>* helper-internal hooks.
>*/
> - int (*get_scanout_position) (struct drm_device *dev, unsigned
n.org>
> Cc: Sean Paul <seanp...@chromium.org>
> Cc: Philipp Zabel <p.za...@pengutronix.de>
> Cc: CK Hu <ck...@mediatek.com>
> Cc: Neil Armstrong <narmstr...@baylibre.com>
> Cc: Rob Clark <robdcl...@gmail.com>
> Cc: Ben Skeggs <bske...@redhat.com
k/mtk_dpi.c| 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 2 +-
> drivers/gpu/drm/mediatek/mtk_drm_fb.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_dsi.c| 2 +-
> drivers/gpu/drm/mediatek/m
S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __DRM_PROBE_HELPER_H__
> +#de
On 31/07/2019 15:10, Andrzej Pietrasiewicz wrote:
> W dniu 31.07.2019 o 12:40, Sam Ravnborg pisze:
>> Hi Neil.
>>
>> On Wed, Jul 31, 2019 at 10:00:14AM +0200, Neil Armstrong wrote:
>>> Hi Sam,
>>>
>>> On 26/07/2019 20:55, Sam Ravnborg wrote:
>
Hi Andrzej,
On 31/07/2019 16:22, Neil Armstrong wrote:
> On 31/07/2019 15:10, Andrzej Pietrasiewicz wrote:
>> W dniu 31.07.2019 o 12:40, Sam Ravnborg pisze:
>>> Hi Neil.
>>>
>>> On Wed, Jul 31, 2019 at 10:00:14AM +0200, Neil Armstrong wrote:
>>>
Hi,
On 19/09/2019 05:30, jsa...@codeaurora.org wrote:
> Hello All,
>
> I bumped into the below check [1] enforced in drm_framebuffer creation which
> checks the requested framebuffer width/height parameters against the drm mode
> config width/height limits. As I understand, drm_mode_config:
eturn PTR_ERR(vga->connector.ddc);
> }
> }
>
> @@ -216,8 +215,8 @@ static int dumb_vga_remove(struct platform_device *pdev)
>
> drm_bridge_remove(>bridge);
>
> - if (!IS_ERR(vga->ddc))
> - i2c_put_adapter(vga->ddc);
> + if (!IS_ERR(vga->connector.ddc))
> + i2c_put_adapter(vga->connector.ddc);
>
> return 0;
> }
>
Reviewed-by: Neil Armstrong
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t; + ret = drm_connector_init_with_ddc(bridge->dev, >connector,
> + _vga_con_funcs,
> + DRM_MODE_CONNECTOR_VGA,
> + vga->ddc);
> if (ret) {
> DRM_ERROR("
= NULL;
> + hdmi->connector.ddc = NULL;
> }
>
> if (hdmi->cec_notifier)
> @@ -2788,7 +2788,7 @@ __dw_hdmi_probe(struct platform_device *pdev,
> err_isfr:
> clk_disable_unprepare(hdmi->isfr_clk);
> err_res:
> - i2c_put_adapter
gt;dev, >connector,
> + _con_funcs,
> + dvi->connector_type,
> + dvi->ddc);
> if (ret) {
> dev_err(dvi->dev, &qu
return ret;
> @@ -382,8 +381,8 @@ static int tfp410_fini(struct device *dev)
>
> drm_bridge_remove(>bridge);
>
> - if (dvi->ddc)
> - i2c_put_adapter(dvi->ddc);
> + if (dvi->connector.ddc)
> + i2c_put_adapter(dvi->connector.ddc);
> if (dvi->hpd)
> gpiod_put(dvi->hpd);
>
>
Reviewed-by: Neil Armstrong
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Hi Sam,
On 26/07/2019 20:55, Sam Ravnborg wrote:
> Hi all.
>
> Andrzej have done a good job following up on feedback and this series is
> now ready.
>
> We need ack on the patches touching the individual drivers before we can
> proceed.
> Please check your drivers and get back.
I can apply all
Hi,
On 30/07/2019 19:30, Sam Ravnborg wrote:
> Hi Neil.
>
>>> Signed-off-by: Andrzej Pietrasiewicz
>>> ---
>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 40 +++
>>> 1 file changed, 20 insertions(+), 20 deletions(-)
&
Hi Andrzej,
I had to revert the previous patch, so you should re-spin it entirely :
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/radeon/radeon_connectors.c: In function
Hi Mihail,
On 04/12/2019 12:48, Mihail Atanassov wrote:
> Hi all,
>
> I've dropped the fun parts of this series since they need more work, but
> figured drm_bridge_init() as a concept is still valuable on its own (and
> I think I'll need it to roll out device links for registered bridges),
> so
noticed that Neil landed my other patches to this driver
> recently (thanks!) and wondered why he didn't land this one. Then, I
> realized that you didn't send it to him or the other bridge
> maintainer. :( Have you tried running get_maintainer?
>
> $ ./scripts/get_maintainer.pl
;
> Signed-off-by: Thomas Zimmermann
> ---
...
> drivers/gpu/drm/meson/meson_drv.c | 2 +-
Acked-by: Neil Armstrong
...
>
> diff --git a/drivers/gpu/drm/meson/meson_drv.c
> b/drivers/gpu/drm/meson/meson_drv.c
> index a7388bf7c838..3d0ccc7eef1b
Hi,
On Thu, 31 Aug 2023 15:57:36 -0700, Jessica Zhang wrote:
> As I participate more actively in the drm/panel subsystem, I would
> like to get notified about new changes in this area.
>
> Since I have contributed and continue to contribute to drm/panel,
> add myself as a reviewer for the DRM
M:Neil Armstrong
+R: Jessica Zhang
R:Sam Ravnborg
L:dri-de...@lists.freedesktop.org
S:Maintained
You're welcome !
Acked-by: Neil Armstrong
Thanks,
Neil
On 12/09/2023 19:39, Dmitry Baryshkov wrote:
On 12/09/2023 14:05, Heikki Krogerus wrote:
On Tue, Sep 12, 2023 at 12:15:10AM +0300, Dmitry Baryshkov wrote:
On 06/09/2023 16:38, Heikki Krogerus wrote:
On Wed, Sep 06, 2023 at 03:48:35PM +0300, Dmitry Baryshkov wrote:
On Wed, 6 Sept 2023 at
On 14/09/2023 11:26, Heikki Krogerus wrote:
Hi Dmitry,
On Wed, Sep 13, 2023 at 04:47:12PM +0300, Dmitry Baryshkov wrote:
On Wed, 13 Sept 2023 at 16:15, Heikki Krogerus
wrote:
On Wed, Sep 13, 2023 at 01:26:14PM +0300, Dmitry Baryshkov wrote:
Hi Heikki,
On Wed, 13 Sept 2023 at 12:27, Heikki
Document the DPU Display Controller on the SM8650 Platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8650-dpu.yaml | 127 +
1 file changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings
Add DPU version 10.0 support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
.../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h| 457 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 26 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1
Add DSI PHY support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++
3 files
Add DSI Controller version 2.8.0 support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm
Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8650-mdss.yaml | 322 +
1 file changed, 322 insertions(+)
diff --git
a/Documentation/devicetree
Add Mobile Display Subsystem (MDSS) support for the SM8650 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
le at:
https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ
Signed-off-by: Neil Armstrong
---
Changes in v2:
- Rebased on top of https://patchwork.freedesktop.org/series/119804/
- Enabled SDMA
- Fixed sm8650_rt_pri_lvl table
- Collected Reviewed-by tags
- Link t
Document the DSI PHY on the SM8650 Platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
b
Document the DSI Controller on the SM8650 Platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi
On 25/10/2023 10:03, Dmitry Baryshkov wrote:
On Wed, 25 Oct 2023 at 10:35, Neil Armstrong wrote:
Add DSI PHY support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers
Add DSI Controller version 2.8.0 support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers
On 25/10/2023 09:49, Dmitry Baryshkov wrote:
On Wed, 25 Oct 2023 at 10:35, Neil Armstrong wrote:
Add DPU version 10.0 support for the SM8650 platform.
Signed-off-by: Neil Armstrong
Thanks for your patch. Could you please rebase it on top of
https://patchwork.freedesktop.org/series/119804
Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8650-mdss.yaml | 322 +
1 file changed, 322 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8650
Add DPU version 10.0 support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
.../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h| 458 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1
Add Mobile Display Subsystem (MDSS) support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 6865db1e3ce8..33947a2e313c 100644
Add DSI PHY support for the SM8650 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++
3 files changed, 30 insertions(+)
diff
Document the DPU Display Controller on the SM8650 Platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8650-dpu.yaml | 127 +
1 file changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
b
le at:
https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm85650/upstream/integ
Signed-off-by: Neil Armstrong
---
Neil Armstrong (8):
dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY
dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI
Control
Document the DSI PHY on the SM8650 Platform.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
b/Documentation/devicetree/bindings
Document the DSI Controller on the SM8650 Platform.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
b
Hi,
On 28/09/2023 13:35, Dmitry Baryshkov wrote:
From: Konrad Dybcio
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
other connection paths:
- a path that connects rotator block to the DDR.
- a path that needs to be handled to ensure MDSS register access
functions
Hi Paloma,
On 28/07/2023 03:26, Paloma Arellano wrote:
Enable display compression (DSC v1.2) and CMD mode for 1080x2400 Visionox
VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
to command mode with DSC enabled.
Note: This patch has only been validated DSC over command
Enable WB2 hardware block, enabling writeback support on this platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the
duplicate clock controls from the MDP top.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20
1 file changed, 20 deletions(-)
diff
-a -s 40@103:1024x768 -o test.d -P 47@103:1024x768
Signed-off-by: Neil Armstrong
---
Changes in v3:
- Collected reviews
- Add static const to clk_ctrl struct in sspp/wb
- Link to v2:
https://lore.kernel.org/r/20231011-topic-sm8550-graphics-sspp-split-clk-v2-0-b219c945d...@linaro.org
Changes in v2:
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
Implement setup_clk_force_ctrl() only starting from major version 9
which corresponds to SM8550 MDSS.
Reviewed-by: Dmitry Baryshkov
Signe
Now SSPP and WB can have setup_force_clk_ctrl() ops, it's simpler to call
them from the plane and wb code and call into the mdp ops if not present.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 37
gister(struct drm_device *dev, unsigned long
flags)
goto out_unlock;
+err_unload:
+ if (dev->driver->unload)
+ dev->driver->unload(dev);
err_minors:
remove_compat_control_link(dev);
drm_minor_unregister(dev, DRM_MINOR_ACCEL);
Looks san
er {
const struct drm_encoder_funcs *funcs;
const struct drm_encoder_helper_funcs *helper_private;
+
+ /**
+* @debugfs_entry:
+*
+* Debugfs directory for this CRTC.
+*/
+ struct dentry *debugfs_entry;
};
#define obj_to_encoder(x) container_of(x,
bc3f99c2a 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -950,6 +950,4 @@ static inline struct drm_bridge *drmm_of_get_bridge(struct
drm_device *drm,
}
#endif
-void drm_bridge_debugfs_init(struct drm_minor *minor);
-
#endif
It would be nice to have a review from Tomi since he pushed the bridge chains
debugfs.
Apart that it looks fine:
Reviewed-by: Neil Armstrong
Thanks,
Neil
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
An optional clk_ctrl struct is added to the SSPP & WB caps,
which can be used by the setup_clk_force_ctrl() op.
Signed-off-by: Neil Armstrong
Move the actual call to the MDP setup_clk_force_ctrl() op to
an helper which will call the correct op depending on the caps.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers
Now clk_ctrl IDs can be optional and the clk_ctrl_reg can be specified
on the SSPP & WB caps directly, pass the SSPP & WB hw struct to the
qos & limit params then call the clk_force_ctrl() op accordingly.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_
Starting with the SM8550 platform, the SSPP & WB Clock Controls are
no more in the MDP TOP registers, but in the SSPP & WB register space.
Add the corresponding SSPP & WB ops and use them from the vbif QoS
and OT limit setup functions.
Signed-off-by: Neil Armstrong
---
Neil
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +
drivers/gpu/drm/msm/disp
alt_port->bridge.type = DRM_MODE_CONNECTOR_USB;
+ alt_port->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
ret = devm_drm_bridge_add(dev, _port->bridge);
if (ret) {
Reviewed-by: Neil Armstrong
On 09/10/2023 19:07, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
Now clk_ctrl IDs can be optional and the clk_ctrl_reg can be specified
on the SSPP & WB caps directly, pass the SSPP & WB hw struct to the
qos & limit params then call the clk_force_ctrl() op
On 09/10/2023 19:10, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1
On 09/10/2023 19:10, Dmitry Baryshkov wrote:
On 09/10/2023 19:36, Neil Armstrong wrote:
The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them
out of the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++
1
On 10/10/2023 10:10, Marijn Suijten wrote:
On 2023-10-09 18:36:11, Neil Armstrong wrote:
Starting with the SM8550 platform, the SSPP & WB Clock Controls are
no more in the MDP TOP registers, but in the SSPP & WB register space.
Add the corresponding SSPP & WB ops and use them from
On 16/10/2023 18:53, Dmitry Baryshkov wrote:
The MIPI DSI links do not fully fall into the DRM callbacks model. The
drm_bridge_funcs abstraction. Instead of having just two states (off and
on) the DSI hosts have separate LP-11 state. In this state the host is
on, but the video stream is not yet
Starting with the SM8550 platform, the SSPP & WB Clock Controls are
no more in the MDP TOP registers, but in the SSPP & WB register space.
Add the corresponding SSPP & WB ops and use them before/after calling the
QoS and OT limit setup functions.
Signed-off-by: Neil Armstrong
---
C
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
Implement setup_clk_force_ctrl() only starting from major version 9
which corresponds to SM8550 MDSS.
Signed-off-by: Neil Armstrong
---
drive
Now SSPP and WB can have setup_force_clk_ctrl() ops, it's simpler to call
them from the plane and wb code and call into the mdp ops if not present.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 37 +--
drivers/gpu/drm/msm/disp/dpu1
The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the
duplicate clock controls from the MDP top.
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20
1 file changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
b
On 11/10/2023 14:45, Dmitry Baryshkov wrote:
On Wed, 11 Oct 2023 at 14:59, Neil Armstrong wrote:
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
Implement setup_clk_force_ctrl() only start
branch with the drm commit, which is
then merged into PHY and USB subsystems together with the corresponding
patch.
Changes since v3:
- Moved bridge driver to gpu/drm/bridge (Neil Armstrong)
- Renamed it to aux-bridge (since there is already a simple_bridge driver)
- Made CONFIG_OF ma
On 04/01/2023 18:48, Dmitry Baryshkov wrote:
On Wed, 4 Jan 2023 at 12:08, Neil Armstrong wrote:
On 04/01/2023 10:45, Dmitry Baryshkov wrote:
On 04/01/2023 11:08, Neil Armstrong wrote:
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
nector->display_info.is_hdmi);
lt9611_hdmi_tx_phy(lt9611);
Reviewed-by: Neil Armstrong
regmap_write(lt9611->regmap, 0x8348, hact / 256);
+ regmap_write(lt9611->regmap, 0x8349, hact % 256);
+ }
regmap_write(lt9611->regmap, 0x8326, pcr_m);
Reviewed-by: Neil Armstrong
able,
.atomic_post_disable = lt9611_bridge_atomic_post_disable,
Reviewed-by: Neil Armstrong
On 09/01/2023 00:09, Dmitry Baryshkov wrote:
On 06/01/2023 17:41, Krzysztof Kozlowski wrote:
On 04/01/2023 10:08, Neil Armstrong wrote:
Document the SM8550 DSI PHY which is very close from the 7nm
and 5nm DSI PHYs found in earlier platforms.
Signed-off-by: Neil Armstrong
---
Documentation
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm
Document the MDSS hardware found on the Qualcomm SM8550 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +
1 file changed, 331 insertions(+)
diff --git
a/Documentation/devicetree
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index f9ef5085041d
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
...@vger.kernel.org
Signed-off-by: Neil Armstrong
---
Changes in v3:
- Patch 1,2,3: Added Acked-by/Reviewed-by
- Patch 6: Fixed compatible to qcom,sm8550-dsi-phy-4nm
- Link to v2:
https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v2-0-87f1c16d7...@linaro.org
Changes in v2:
- Rebased on msm
Document the SM8550 DSI PHY which is very close from the 7nm
and 5nm DSI PHYs found in earlier platforms.
Acked-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Document the DPU hardware found on the Qualcomm SM8550 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +
1 file changed, 134 insertions(+)
diff --git a/Documentation/devicetree/bindings
On 09/01/2023 10:26, Neil Armstrong wrote:
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4
...@vger.kernel.org
Signed-off-by: Neil Armstrong
---
Changes in v2:
- Rebased on msm-next-lumag & msm-next-lumag-dpu
- Fixed cover letter title to SM8550
- Patch 1: renamed compatible to qcom,sm8550-dsi-phy-4nm
- Patch 2: split in 2 patches, switch to renamed qcom,sm8550-dsi-phy-4nm
- Patch 3: switch
Document the SM8550 DSI PHY which is very close from the 7nm
and 5nm DSI PHYs found in earlier platforms.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings
Document the DPU hardware found on the Qualcomm SM8550 platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +
1 file changed, 134 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
Document the MDSS hardware found on the Qualcomm SM8550 platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +
1 file changed, 331 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8550
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index f9ef5085041d
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
On 08/01/2023 17:56, Dmitry Baryshkov wrote:
The lt9611 bridge can support different modes, it makes no sense to list
them in the table. Drop the table and check the number of interfaces
using the fixed value.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/lontium-lt9611.c | 41
611->sleep)
return;
- lt9611_reset(lt9611);
- regmap_write(lt9611->regmap, 0x80ee, 0x01);
+ regmap_multi_reg_write(lt9611->regmap,
+ reg_cfg, ARRAY_SIZE(reg_cfg));
lt9611->sleep = false;
}
Reviewed-by: Neil Armstrong
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