Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-13 Thread Wang Pengli 
I think beaglebone black should ok for this case.

2018-04-11 3:36 GMT+08:00 Alan Beard :

> Hi all,
>
> Well, I've compiled up FreeDV on my Banana Pi here and it runs.
>
> As I see it, the Banana Pi with a SATA disk is a realistic
> low power ( < 5W ) general purpose Linux box.
>
> When I started in the Unix world, you could run X11R6 the GUI on the
> Motorola 68020 CPU as I did on an Integrated Solution Inc. box.
> But on the MIPS M120 (20MHz MIPS CPU) with 32Mb ram and 600Mb disk
> it all ran very well.
>
> So Glen, I've been there.
>
> The Odroid XU4 is perhaps much better in your eyes but at the cost
> of much more power consumption, note the heatsink and cooler fan option.
> And, much more expensive storage. a 32Gb eMMC costs as much as a 1Tb
> SATA disk. And #2, there's none in MY junk box.
>
> Keep smiling
>
> Alan VK2ZIW
>
> On Sun, 8 Apr 2018 14:53:02 +1000, Alan Beard wrote
> > Hi,
> > I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now
> > (1999).
> >
> > Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?
> >
> > Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk
> > interface. This allows real swap space and huge disk throughput.
> >
> > At about $70 AU is a bargain for a FULL linux box.
> > (Fedora 25 or later is my choice)
> > (and an SSD or hard disk of course)
> >
> > I read the specs on the ESP32, DMA only points at the internal memory
> > so a High Speed disk interface is a problem.
> >
> > BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
> > the linux software support is not there yet. No GUI on the HDMI
> > video. Debian boots but I can't get XRDP to work. Also Debian uses
> > the 3.10.xx kernel which is old now, as does other Debian based
> > distributions for ARM. WHAT A PAIN.
> >
> > Fedora 25 on the original Banana Pi works, a dream.
> >
> > 73 - isn't that an old electron tube? (HV triode)
> >
> > Alan VK2ZIW
> >
> > On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote
> > > I generally assume for estimations, FPU ops = INT ops per clock, and
> > > if you are careful you can do simultaneous INt/FPU ops...
> > >
> > > Just watch out for non aligned floating point accesses. bang... not
> > > lots of __aligned__ used.
> > >
> > > I used to be a full-on SHARC guy. but I wonder where that market is
> > > now with M7 and M4F around , and NEON which if you know what you are
> > > doing can run rings around a SHARC.
> > >
> > > Just diehards i think. The simple thigns with SHARC have disappeared
> > > with cache involvement.
> > >
> > > On 8/04/2018 10:51 AM, Dana Myers wrote:
> > > > On 4/7/2018 5:22 PM, Bruce Perens wrote:
> > > >> It could also be the use of memory barrier instructions. I'd like
> to
> > > >> benchmark Codec2 rather than a simple floating point loop with
> > > >> volatile variables. But if we are to believe the times on the
> screen
> > > >> of the esp32 in the video, he was getting acceptable performance.
> > > >
> > > > From what I've seen, the Cortex-M FPUs basically give
> single-precision
> > > > FP add/sub/mul in the same number of clocks as integer operations.
> > > >
> > > > With a proper program store cache, Cortex-M4F is quite the rocket,
> > > > really.
> > > >
> > > > Now I want to hunt down the appropriate Tensilica reference for the
> core
> > > > in the ESP32; it occurs to me the two cores may be sharing one FPU,
> > > > though I don't immediately see how the simple test would incur
> context
> > > > switching frequently.
> > > >
> > > > 73,
> > > > Dana  K6JQ
> > > >
> > > >
> > > > 
> 
> --
> > 
> > > >
> > > > Check out the vibrant tech community on one of the world's most
> > > > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > > > ___
> > > > Freetel-codec2 mailing list
> > > > [email protected]
> > > > https://lists.sourceforge.net/lists/listinfo/freetel-codec2
> > >
> > > 
> --
> --
> > --
> > > Check out the vibrant tech community on one of the world's most
> > > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > > ___
> > > Freetel-codec2 mailing list
> > > [email protected]
> > > https://lists.sourceforge.net/lists/listinfo/freetel-codec2
> >
> > Alan
> >
> > Evil flourishes when good men do nothing.
> > Consider the Christmas child.
> > 
> ---
> > Alan Beard   Unix Support Technician from 1984 to today
> > 70 Wedmore Rd.   Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
> > Emu Heights N.S.W. 2750  Routers, terminal servers, printers,
> >  terminals etc.. +61 2 47353013 (h)   Support Programming, shell
> > scripting, "C", assembler 0414 353013 (mobile) After uni,
> >  electronics tech
> >
> > -

Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-10 Thread Alan Beard 
Hi all,

Well, I've compiled up FreeDV on my Banana Pi here and it runs.

As I see it, the Banana Pi with a SATA disk is a realistic
low power ( < 5W ) general purpose Linux box.

When I started in the Unix world, you could run X11R6 the GUI on the
Motorola 68020 CPU as I did on an Integrated Solution Inc. box. 
But on the MIPS M120 (20MHz MIPS CPU) with 32Mb ram and 600Mb disk
it all ran very well.

So Glen, I've been there.

The Odroid XU4 is perhaps much better in your eyes but at the cost
of much more power consumption, note the heatsink and cooler fan option.
And, much more expensive storage. a 32Gb eMMC costs as much as a 1Tb
SATA disk. And #2, there's none in MY junk box.

Keep smiling

Alan VK2ZIW

On Sun, 8 Apr 2018 14:53:02 +1000, Alan Beard wrote
> Hi,
> I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now 
> (1999).
> 
> Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?
> 
> Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk 
> interface. This allows real swap space and huge disk throughput.
> 
> At about $70 AU is a bargain for a FULL linux box.
> (Fedora 25 or later is my choice)
> (and an SSD or hard disk of course)
> 
> I read the specs on the ESP32, DMA only points at the internal memory
> so a High Speed disk interface is a problem.
> 
> BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
> the linux software support is not there yet. No GUI on the HDMI 
> video. Debian boots but I can't get XRDP to work. Also Debian uses 
> the 3.10.xx kernel which is old now, as does other Debian based 
> distributions for ARM. WHAT A PAIN.
> 
> Fedora 25 on the original Banana Pi works, a dream.
> 
> 73 - isn't that an old electron tube? (HV triode)
> 
> Alan VK2ZIW
> 
> On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote
> > I generally assume for estimations, FPU ops = INT ops per clock, and 
> > if you are careful you can do simultaneous INt/FPU ops...
> > 
> > Just watch out for non aligned floating point accesses. bang... not 
> > lots of __aligned__ used.
> > 
> > I used to be a full-on SHARC guy. but I wonder where that market is 
> > now with M7 and M4F around , and NEON which if you know what you are 
> > doing can run rings around a SHARC.
> > 
> > Just diehards i think. The simple thigns with SHARC have disappeared 
> > with cache involvement.
> > 
> > On 8/04/2018 10:51 AM, Dana Myers wrote:
> > > On 4/7/2018 5:22 PM, Bruce Perens wrote:
> > >> It could also be the use of memory barrier instructions. I'd like to 
> > >> benchmark Codec2 rather than a simple floating point loop with 
> > >> volatile variables. But if we are to believe the times on the screen 
> > >> of the esp32 in the video, he was getting acceptable performance.
> > >
> > > From what I've seen, the Cortex-M FPUs basically give single-precision
> > > FP add/sub/mul in the same number of clocks as integer operations.
> > >
> > > With a proper program store cache, Cortex-M4F is quite the rocket, 
> > > really.
> > >
> > > Now I want to hunt down the appropriate Tensilica reference for the core
> > > in the ESP32; it occurs to me the two cores may be sharing one FPU,
> > > though I don't immediately see how the simple test would incur context
> > > switching frequently.
> > >
> > > 73,
> > > Dana  K6JQ
> > >
> > >
> > > 
--
>  
> > >
> > > Check out the vibrant tech community on one of the world's most
> > > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > > ___
> > > Freetel-codec2 mailing list
> > > [email protected]
> > > https://lists.sourceforge.net/lists/listinfo/freetel-codec2
> > 
> > --
--
> --
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > ___
> > Freetel-codec2 mailing list
> > [email protected]
> > https://lists.sourceforge.net/lists/listinfo/freetel-codec2
> 
> Alan
> 
> Evil flourishes when good men do nothing.
> Consider the Christmas child.
> ---
> Alan Beard   Unix Support Technician from 1984 to today
> 70 Wedmore Rd.   Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
> Emu Heights N.S.W. 2750  Routers, terminal servers, printers,
>  terminals etc.. +61 2 47353013 (h)   Support Programming, shell 
> scripting, "C", assembler 0414 353013 (mobile) After uni,
>  electronics tech
> 
> 
--
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> ___
> Freetel-codec2 mailing list
> [email protected]

Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread glen english 

Alan

I think you are about 15 years behind the current hardware :-)

Best small linux boxes are Odroid with say 16GB eMMC. AUD$70.

beats the crap out of a Banana  Pi or , "a Dual Core armv7hl" no matter 
what hard disk you think of.


probably by a factor of 10 on every benchmark on the planet for about 
the same or less  power consumption.


and has a gigabit NW interface and supports 90% utilization

HOWEVER yes, it should be fine on OpenDV.

g


On 8/04/2018 2:53 PM, Alan Beard wrote:

Hi,
I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now (1999).

Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?

Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk interface.
This allows real swap space and huge disk throughput.

At about $70 AU is a bargain for a FULL linux box.
(Fedora 25 or later is my choice)
(and an SSD or hard disk of course)

I read the specs on the ESP32, DMA only points at the internal memory
so a High Speed disk interface is a problem.

BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
the linux software support is not there yet. No GUI on the HDMI video.
Debian boots but I can't get XRDP to work. Also Debian uses the 3.10.xx
kernel which is old now, as does other Debian based distributions for ARM.
WHAT A PAIN.

Fedora 25 on the original Banana Pi works, a dream.


73 - isn't that an old electron tube? (HV triode)

Alan VK2ZIW


  


On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote

I generally assume for estimations, FPU ops = INT ops per clock, and
if you are careful you can do simultaneous INt/FPU ops...

Just watch out for non aligned floating point accesses. bang... not
lots of __aligned__ used.

I used to be a full-on SHARC guy. but I wonder where that market is
now with M7 and M4F around , and NEON which if you know what you are
doing can run rings around a SHARC.

Just diehards i think. The simple thigns with SHARC have disappeared
with cache involvement.

On 8/04/2018 10:51 AM, Dana Myers wrote:

On 4/7/2018 5:22 PM, Bruce Perens wrote:

It could also be the use of memory barrier instructions. I'd like to
benchmark Codec2 rather than a simple floating point loop with
volatile variables. But if we are to believe the times on the screen
of the esp32 in the video, he was getting acceptable performance.

 From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket,
really.

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


--



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Alan

Evil flourishes when good men do nothing.
Consider the Christmas child.
---
Alan Beard   Unix Support Technician from 1984 to today
70 Wedmore Rd.   Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
Emu Heights N.S.W. 2750  Routers, terminal servers, printers, terminals etc..
+61 2 47353013 (h)   Support Programming, shell scripting, "C", assembler
0414 353013 (mobile) After uni, electronics tech


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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread glen english 

SHARC not SPARC


On 8/04/2018 2:53 PM, Alan Beard wrote:

Hi,
I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now (1999).

Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?

Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk interface.
This allows real swap space and huge disk throughput.

At about $70 AU is a bargain for a FULL linux box.
(Fedora 25 or later is my choice)
(and an SSD or hard disk of course)

I read the specs on the ESP32, DMA only points at the internal memory
so a High Speed disk interface is a problem.

BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
the linux software support is not there yet. No GUI on the HDMI video.
Debian boots but I can't get XRDP to work. Also Debian uses the 3.10.xx
kernel which is old now, as does other Debian based distributions for ARM.
WHAT A PAIN.

Fedora 25 on the original Banana Pi works, a dream.


73 - isn't that an old electron tube? (HV triode)

Alan VK2ZIW


  


On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote

I generally assume for estimations, FPU ops = INT ops per clock, and
if you are careful you can do simultaneous INt/FPU ops...

Just watch out for non aligned floating point accesses. bang... not
lots of __aligned__ used.

I used to be a full-on SHARC guy. but I wonder where that market is
now with M7 and M4F around , and NEON which if you know what you are
doing can run rings around a SHARC.

Just diehards i think. The simple thigns with SHARC have disappeared
with cache involvement.

On 8/04/2018 10:51 AM, Dana Myers wrote:

On 4/7/2018 5:22 PM, Bruce Perens wrote:

It could also be the use of memory barrier instructions. I'd like to
benchmark Codec2 rather than a simple floating point loop with
volatile variables. But if we are to believe the times on the screen
of the esp32 in the video, he was getting acceptable performance.

 From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket,
really.

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


--



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Alan

Evil flourishes when good men do nothing.
Consider the Christmas child.
---
Alan Beard   Unix Support Technician from 1984 to today
70 Wedmore Rd.   Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
Emu Heights N.S.W. 2750  Routers, terminal servers, printers, terminals etc..
+61 2 47353013 (h)   Support Programming, shell scripting, "C", assembler
0414 353013 (mobile) After uni, electronics tech


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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Alan Beard 
Hi,
I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now (1999).

Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?

Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk interface.
This allows real swap space and huge disk throughput.

At about $70 AU is a bargain for a FULL linux box.
(Fedora 25 or later is my choice)
(and an SSD or hard disk of course)

I read the specs on the ESP32, DMA only points at the internal memory
so a High Speed disk interface is a problem.

BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
the linux software support is not there yet. No GUI on the HDMI video.
Debian boots but I can't get XRDP to work. Also Debian uses the 3.10.xx
kernel which is old now, as does other Debian based distributions for ARM.
WHAT A PAIN.

Fedora 25 on the original Banana Pi works, a dream.


73 - isn't that an old electron tube? (HV triode)

Alan VK2ZIW


 

On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote
> I generally assume for estimations, FPU ops = INT ops per clock, and 
> if you are careful you can do simultaneous INt/FPU ops...
> 
> Just watch out for non aligned floating point accesses. bang... not 
> lots of __aligned__ used.
> 
> I used to be a full-on SHARC guy. but I wonder where that market is 
> now with M7 and M4F around , and NEON which if you know what you are 
> doing can run rings around a SHARC.
> 
> Just diehards i think. The simple thigns with SHARC have disappeared 
> with cache involvement.
> 
> On 8/04/2018 10:51 AM, Dana Myers wrote:
> > On 4/7/2018 5:22 PM, Bruce Perens wrote:
> >> It could also be the use of memory barrier instructions. I'd like to 
> >> benchmark Codec2 rather than a simple floating point loop with 
> >> volatile variables. But if we are to believe the times on the screen 
> >> of the esp32 in the video, he was getting acceptable performance.
> >
> > From what I've seen, the Cortex-M FPUs basically give single-precision
> > FP add/sub/mul in the same number of clocks as integer operations.
> >
> > With a proper program store cache, Cortex-M4F is quite the rocket, 
> > really.
> >
> > Now I want to hunt down the appropriate Tensilica reference for the core
> > in the ESP32; it occurs to me the two cores may be sharing one FPU,
> > though I don't immediately see how the simple test would incur context
> > switching frequently.
> >
> > 73,
> > Dana  K6JQ
> >
> >
> > --
 
> >
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > ___
> > Freetel-codec2 mailing list
> > [email protected]
> > https://lists.sourceforge.net/lists/listinfo/freetel-codec2
> 
> 
--
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> ___
> Freetel-codec2 mailing list
> [email protected]
> https://lists.sourceforge.net/lists/listinfo/freetel-codec2


Alan

Evil flourishes when good men do nothing.
Consider the Christmas child.
---
Alan Beard   Unix Support Technician from 1984 to today
70 Wedmore Rd.   Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
Emu Heights N.S.W. 2750  Routers, terminal servers, printers, terminals etc..
+61 2 47353013 (h)   Support Programming, shell scripting, "C", assembler
0414 353013 (mobile) After uni, electronics tech


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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Dana Myers 

On 4/7/2018 5:51 PM, Dana Myers wrote:

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.


The Xtensa LX6 core is highly configurable - it's not clear to me that
Espressif actually included the FPU hardware in ESP32 SoC, but boiler-
plated the Xtensa LX6 datasheet into their own.

Given the times observed in the blog post, I think it's
soft FPU emulation.

Single-precision addition was 8.7uS at 240MHz; I think that's
~2100 clock cycles. Single-precision multiplication was
around 1000 clocks. That's not a slow FPU IMO, that's
software emulation.

73,
Dana  K6JQ



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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread glen english 
I generally assume for estimations, FPU ops = INT ops per clock, and if 
you are careful you can do simultaneous INt/FPU ops...


Just watch out for non aligned floating point accesses. bang... not lots 
of __aligned__ used.


I used to be a full-on SHARC guy. but I wonder where that market is now 
with M7 and M4F around , and NEON which if you know what you are doing 
can run rings around a SHARC.


Just diehards i think. The simple thigns with SHARC have disappeared 
with cache involvement.




On 8/04/2018 10:51 AM, Dana Myers wrote:

On 4/7/2018 5:22 PM, Bruce Perens wrote:
It could also be the use of memory barrier instructions. I'd like to 
benchmark Codec2 rather than a simple floating point loop with 
volatile variables. But if we are to believe the times on the screen 
of the esp32 in the video, he was getting acceptable performance.


From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket, 
really.


Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


-- 


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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Dana Myers 

On 4/7/2018 5:22 PM, Bruce Perens wrote:
It could also be the use of memory barrier instructions. I'd like to benchmark Codec2 rather than a simple floating point loop 
with volatile variables. But if we are to believe the times on the screen of the esp32 in the video, he was getting acceptable 
performance.


From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket, really.

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Bruce Perens 
It could also be the use of memory barrier instructions. I'd like to
benchmark Codec2 rather than a simple floating point loop with volatile
variables. But if we are to believe the times on the screen of the esp32 in
the video, he was getting acceptable performance.

On Sat, Apr 7, 2018, 3:41 PM glen english  wrote:

> Of interest is this blog on the ESP32 FP perofrmance, versus the STM32F7
> (which can easily run  simultaneous encode/decode on my setup).
>
> the author appears to have done his homework
>
> https://blog.classycode.com/esp32-floating-point-performance-6e9f6f567a69
>
> The STM32F7 appears to be between 10 and 100  times faster on various
> jobs, the author concluded the ESP32 may be software emulating.
>
> more:
>
> https://www.esp32.com/viewtopic.php?f=14&t=800
>
> others interpreted as just a very slow FPU, OR the scheduler was getting
> in the way of the ESP32 performance, and tuning was required to get
> perfornamce.
>
>
>
> On 8/04/2018 6:45 AM, Bruce Perens wrote:
> > > The ESP only has a 12 bit ADC and an 8 bit A
>
>
>
>
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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread glen english 
Of interest is this blog on the ESP32 FP perofrmance, versus the STM32F7 
(which can easily run  simultaneous encode/decode on my setup).


the author appears to have done his homework

https://blog.classycode.com/esp32-floating-point-performance-6e9f6f567a69

The STM32F7 appears to be between 10 and 100  times faster on various 
jobs, the author concluded the ESP32 may be software emulating.


more:

https://www.esp32.com/viewtopic.php?f=14&t=800

others interpreted as just a very slow FPU, OR the scheduler was getting 
in the way of the ESP32 performance, and tuning was required to get 
perfornamce.




On 8/04/2018 6:45 AM, Bruce Perens wrote:

> The ESP only has a 12 bit ADC and an 8 bit A




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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread David Rowe 

  > The ESP only has a 12 bit ADC and an 8 bit ADC.


12-bit dual ADC and 8-bit DAC. And I have not tested the ADC speed. 
Might be good enough to do Codec2, but since the ESP32 has a DMA 
interface for codec chips, it's easy to connect one.


The internal 12 bit ADC would be worth trying - we use a similar ADC on 
the STM32F4.  The 8 bit DAC as well, especially if it can run a a high 
sample rate.


Remarkable amount of functionality/$, hardware just keeps getting 
cheaper :-)


Given it's a 200MHz-ish CPU with FPU, it should run Codec 2, and indeed 
the entire FreeDV stack, just fine.


- David

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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Dana Myers 

On 4/7/2018 1:41 PM, Bruce Perens wrote:

Cool videos by Thai ham HS5TQA. https://www.youtube.com/user/HS5TQA 

I would assume he is using only one of the two cores, and still gets decode speed that looks just fine. For what that processor 
costs, I'm not sure we /need/ anything slower.


I have the ESP32 running the server I wrote for Algoram Whitebox, and thus you can connect to it with your phone, tablet, or 
laptop and control it using any HTML5 browser, using the phone mike and speaker. Or control your rig from anywhere in the world. 
It is simultaneously a WiFi AP and client. I've not touched the Bluetooth code, but you can do that too. Pretty good for $5 
ready to plug into your breadboard and $3.80 for the /module /(not just a chip) single quantity. I am using the native 
programming interface rather than the Arduino one. But for people who have an Arduino code base, you can port it ESP32 and have 
the network connectivity.


ESP32 and the associated IDE really knock it out of the park for
a connected device. Particularly nice they did necessary SMP
enhancements to the FreeRTOS scheduler and most of the IDE
libraries.

I haven't done any DSP on the ESP32; I've been too happy
with the Cortex-M4F core - particularly the STM32F4xx which
runs 0 wait-state.

73,
Dana  K6JQ

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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Bruce Perens 
> The ESP only has a 12 bit ADC and an 8 bit ADC.

12-bit dual ADC and 8-bit DAC. And I have not tested the ADC speed. Might
be good enough to do Codec2, but since the ESP32 has a DMA interface for
codec chips, it's easy to connect one.

On Sat, Apr 7, 2018 at 1:41 PM, Bruce Perens  wrote:

> Cool videos by Thai ham HS5TQA. https://www.youtube.com/user/HS5TQA
> I would assume he is using only one of the two cores, and still gets
> decode speed that looks just fine. For what that processor costs, I'm not
> sure we *need* anything slower.
>
> I have the ESP32 running the server I wrote for Algoram Whitebox, and thus
> you can connect to it with your phone, tablet, or laptop and control it
> using any HTML5 browser, using the phone mike and speaker. Or control your
> rig from anywhere in the world. It is simultaneously a WiFi AP and client.
> I've not touched the Bluetooth code, but you can do that too. Pretty good
> for $5 ready to plug into your breadboard and $3.80 for the *module *(not
> just a chip) single quantity. I am using the native programming interface
> rather than the Arduino one. But for people who have an Arduino code base,
> you can port it ESP32 and have the network connectivity.
>
> The ESP only has a 12 bit ADC and an 8 bit ADC. But a 24-bit stereo codec
> chip is only a few bucks. So, you can make a pretty cheap box to remote
> control your rig and run the codec or DSP software of your choice. The
> ESP32-WROOM version has about half a megabyte of RAM and 4 MB FLASH, the
> ESP32-WROVER ads another 4 MB RAM and still costs about $5 for the module.
>
> Because of its network connectivity, low cost, and ease of building around
> a module that is already a working computer, it could blow SM1000 out of
> the water. And it's got two cores, a real OS, touch sensors so you can
> build a keyer out of a piece of double-sided PCB, various hardware
> accelerators, and other sorts of I/O. There is also an ultra-low-power
> processor that can wake up the main CPU, so it can do audio squelch with
> low power drain, etc.
>
> The low-level WiFi and Bluetooth code is proprietary, and the
> WiFi/Bluetooth radio is an SDR that is just begging to be reverse
> engineered, but all high-level code is taken from existing Open Source
> projects.
>
> It's so convenient to put one of those modules on a hardware project and
> then talk to the project with your web browser.
>
> Thanks
>
> Bruce
>
> On Sat, Apr 7, 2018 at 6:31 AM, tom sparks 
> wrote:
>
>> I am wondering what is the slowest CPU that can decode codec2 in
>> real-time?
>>
>> I saw a video on youtube of somebody using a ESP32 to decode codec2
>>
>> 
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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Bruce Perens 
Cool videos by Thai ham HS5TQA. https://www.youtube.com/user/HS5TQA
I would assume he is using only one of the two cores, and still gets decode
speed that looks just fine. For what that processor costs, I'm not sure we
*need* anything slower.

I have the ESP32 running the server I wrote for Algoram Whitebox, and thus
you can connect to it with your phone, tablet, or laptop and control it
using any HTML5 browser, using the phone mike and speaker. Or control your
rig from anywhere in the world. It is simultaneously a WiFi AP and client.
I've not touched the Bluetooth code, but you can do that too. Pretty good
for $5 ready to plug into your breadboard and $3.80 for the *module *(not
just a chip) single quantity. I am using the native programming interface
rather than the Arduino one. But for people who have an Arduino code base,
you can port it ESP32 and have the network connectivity.

The ESP only has a 12 bit ADC and an 8 bit ADC. But a 24-bit stereo codec
chip is only a few bucks. So, you can make a pretty cheap box to remote
control your rig and run the codec or DSP software of your choice. The
ESP32-WROOM version has about half a megabyte of RAM and 4 MB FLASH, the
ESP32-WROVER ads another 4 MB RAM and still costs about $5 for the module.

Because of its network connectivity, low cost, and ease of building around
a module that is already a working computer, it could blow SM1000 out of
the water. And it's got two cores, a real OS, touch sensors so you can
build a keyer out of a piece of double-sided PCB, various hardware
accelerators, and other sorts of I/O. There is also an ultra-low-power
processor that can wake up the main CPU, so it can do audio squelch with
low power drain, etc.

The low-level WiFi and Bluetooth code is proprietary, and the
WiFi/Bluetooth radio is an SDR that is just begging to be reverse
engineered, but all high-level code is taken from existing Open Source
projects.

It's so convenient to put one of those modules on a hardware project and
then talk to the project with your web browser.

Thanks

Bruce

On Sat, Apr 7, 2018 at 6:31 AM, tom sparks  wrote:

> I am wondering what is the slowest CPU that can decode codec2 in real-time?
>
> I saw a video on youtube of somebody using a ESP32 to decode codec2
>
> 
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Re: [Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread Steve 
On Sat, Apr 7, 2018 at 8:31 AM, tom sparks  wrote:
> I am wondering what is the slowest CPU that can decode codec2 in real-time?
>

The computer has to decode 80 PCM 12 to 16-bit samples at 8 kHz into voice
models in less than 10 ms, and it has to interpolate four of these, and output
52 bits of digital data in less than 40 ms.

It must be capable of 32-bit floating point math in RAM.

The ESP-32 seems to have all that. There is some customization needed to insure
floating point is being done in the 64k cache RAM. You also have to pre-load a
floating point computation as the OS defaults off, but switches to on when an
operation is detected. Something like that, as I'm no expert.

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[Freetel-codec2] whats the slowest cpu that can decode codec2 in realtime

2018-04-07 Thread tom sparks 

I am wondering what is the slowest CPU that can decode codec2 in real-time?

I saw a video on youtube of somebody using a ESP32 to decode codec2

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