Re: Targets still needing stdint.h type information

> * DJGPP Committed. 2009-08-13 DJ Delorie * config/i386/djgpp-stdint.h: New. * config.gcc (djgpp): Use it. Index: config.gcc === --- config.gcc (revision 150731) +++ config.gcc (working copy) @@ -1169,12 +116

Re: Implementing C++1x and C1x atomics

On Thu, 13 Aug 2009, Lawrence Crowl wrote: > Now a processor D for this architecture comes out. All code for A, > B and C will work on D, but D also has 8-byte atomic operations. > GCC 4.7, with -march=D, generates code that uses these operations > inline. If code built with GCC 4.7 -mar

Re: Implementing C++1x and C1x atomics

On 8/13/09, Joseph S. Myers wrote: > On Thu, 13 Aug 2009, Lawrence Crowl wrote: > > > In that it defines functions, is unlike all the > > > headers presently required of freestanding implementations, > > > > But , , and all define functions. > > I'm not familiar with the C++ requirements for fre

Re: Implementing C++1x and C1x atomics

On Thu, 13 Aug 2009, Lawrence Crowl wrote: > > In that it defines functions, is unlike all the > > headers presently required of freestanding implementations, > > But , , and all define functions. I'm not familiar with the C++ requirements for freestanding implementations, so am just comparin

gcc-4.5-20090813 is now available

Snapshot gcc-4.5-20090813 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/4.5-20090813/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 4.5 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/trunk

Re: Implementing C++1x and C1x atomics

On 8/12/09, Joseph S. Myers wrote: > On Wed, 12 Aug 2009, Lawrence Crowl wrote: > > > The C1x atomics specification > > > > > > does not mention any amendment to the list of headers to be > > > provided by freestanding implementations (cl

Re: [IRA, regresssion] code size regression with IRA

Hariharan Sandanagobalane wrote: Hi Vlad, I am attaching a test function which has just a huge switch statement with multiple cases doing different things. This function register allocates on GCC 4.3.2 with no spills at all (at -Os). The function has lots of live ranges that span function call

Re: Address as HImode when Pmode is QImode?

Markus L writes: > I run into an assert in convert_memory_address not beeing able to > convert the address rtx (beeing HImode) into to Pmode (i.e. QImode). A > few frames up the I can dump the tree node and it looks like the > address calculations are done in HImode. Why is the address beeing > ca

rs6000, SPU: vcond pattern can not FAIL

Hello! I would like to warn rs6000 and SPU maintainers, that vcond patterns can _not_ FAIL. Please see PR41019 [1] for the proposed fix for x86. The same problem can be triggered on rs6000 and SPU, it can happen that the vcond pattern is only partially expanded. The problem is, that middle e

Re: Notes toward re-implementing EH in gimple

On 08/13/2009 06:48 AM, Jan Hubicka wrote: In gimple, the landing pad will be generated as L.N: exc_ptr.1 = EXC_PTR_EXPR (N); filter.1 = FILTER_EXPR (N); ie, copied into normal variables for use. These can be moved about, or deleted, as the optimizer desires. All of this seems much clea

Re: Help on loop peeling

On Thu, Aug 13, 2009 at 4:41 PM, Sebastian Pop wrote: > Hi, > > On Thu, Aug 13, 2009 at 04:02, Eric Fisher wrote: >> The error is reported in build2_stat, by >> >> gcc_assert (POINTER_TYPE_P (tt) && POINTER_TYPE_P (TREE_TYPE (arg0)) >>                && INTEGRAL_TYPE_P (TREE_TYPE (arg1)) >>        

Re: Help on loop peeling

Hi, On Thu, Aug 13, 2009 at 04:02, Eric Fisher wrote: > The error is reported in build2_stat, by > > gcc_assert (POINTER_TYPE_P (tt) && POINTER_TYPE_P (TREE_TYPE (arg0)) >                && INTEGRAL_TYPE_P (TREE_TYPE (arg1)) >                && useless_type_conversion_p (sizetype, TREE_TYPE (arg1)

Re: Notes toward re-implementing EH in gimple

Hi, sorry for jumping in late, I had relatively urgent things to work at and didn't had much time to think this over. I am still having some problems understanding the plans on critical edge splitting. > EXC_PTR_EXPR and FILTER_EXPR will be expanded to take the EH > region number as a parameter.

Address as HImode when Pmode is QImode?

Hi, I am using gcc 4.4.1 and working on a port where #define BITS_PER_UNIT 16 #define UNITS_PER_WORD 1 #define Pmode QImode #define LONG_TYPE_SIZE 32 (i.e. int is 16 bits QImode, long is 32 bits HImode and pointer mode is QImode) POINTERS_EXTEND_UNSIGNED is not defined since POINTER_SIZE is equ

Re: How to deal with 48-bit pointers and 32-bit integers

I chose to define Pmode as PDImode, and write PDI patterns for pointer moves & arithmetic. POINTER_SIZE is 64 bits, UNITS_PER_WORD is 4. FUNCTION_ARG_ADVANCE arranges for both SImode and PDImode values to occupy a single register. I have the port mostly working (passes 90% of execution tests), b

Help on loop peeling

Hi, I'm implementing a loop peeling function used in tree-ssa-loop-prefetch.c according to the following comment, /* Step 5: unroll the loop. TODO -- peeling of first and last few iterations so that we do not issue superfluous prefetches. */ I take the functions slpeel_* in tree-vercteriz

Re: Anyone else run ACATS on ARM?

On 8/12/09, Matthias Klose wrote: > On 12.08.2009 23:07, Martin Guy wrote: > > I looked into gnat-arm for the new Debian port and the conclusion was > > that it has never been bootstrapped onto ARM. The closest I have seen > > is Adacore's GNATPro x86->xscale cross-compiler hosted on Windows and >