https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97196
Jakub Jelinek changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97196
--- Comment #2 from Miguel ---
Trigger seems to be line 22, in the loop guard. If I change `while (x != 0)` to
`while (x)` the program then behaves properly regardless of optimization level.
On Thu, 24 Sep 2020, Jonathan Wakely wrote:
> On 24/09/20 11:11 +0200, Richard Biener wrote:
> >On Wed, 26 Aug 2020, Richard Biener wrote:
> >
> >> On Thu, 6 Aug 2020, Richard Biener wrote:
> >>
> >> > On Thu, 6 Aug 2020, Richard Biener wrote:
> >> >
> >> > > This adds a move CTOR to auto_vec and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97196
Miguel changed:
What|Removed |Added
Summary|Difference in output|Difference in output
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97196
Bug ID: 97196
Summary: Difference in output between no optimization and -O2,
triggered by a variable wrapped in parentheses in the
RHS of the assignment operator
Product:
Thanks Richard for your recommendations.
I am still discussing with Kyrill about a good name for the branch.
Once we agree on a name we will commit the patches to that branch.
Sebastian
On 9/24/20, 4:10 AM, "Richard Biener" wrote:
On Fri, Sep 11, 2020 at 12:38 AM Pop, Sebastian via
On 24/09/20 09:04 -0400, Patrick Palka via Libstdc++ wrote:
The class template semiregular-box defined in [range.semi.wrap] is
used by a number of views to accomodate non-semiregular subobjects
while ensuring that the overall view remains semiregular. It provides
a stand-in default constructor,
On Thu, Sep 24, 2020 at 3:27 PM Richard Biener
wrote:
>
> On Thu, Sep 24, 2020 at 10:21 AM xionghu luo wrote:
> >
> > Hi Segher,
> >
> > The attached two patches are updated and split from
> > "[PATCH v2 2/2] rs6000: Expand vec_insert in expander instead of gimple
> > [PR79251]"
> > as your
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97194
--- Comment #3 from Richard Biener ---
(In reply to Richard Biener from comment #2)
> Eventually there's a more efficient way to generate {0, 1, 2, 3...}.
vpmovzx* could be at least used to only have a single
byte vector {0, ... 255 } in memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86419
--- Comment #13 from Jonathan Wakely ---
Thanks!
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97194
--- Comment #2 from Richard Biener ---
So for set with T == int and N == 32 we could generate
vmovd %edi, %xmm1
vpbroadcastd%xmm1, %ymm1
vpcmpeqd.LC0(%rip), %ymm1, %ymm2
vpblendvb %ymm2,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97195
Bug ID: 97195
Summary: construct_at on a union member is not a constant
expression
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
I see it handy to debug cgraph_edge and I've dumped it manually many times.
Maybe it's time to come up with the function? Example output:
(gdb) p e->debug()
ag/9 -> h/3 (1 (adjusted),0.25 per call)
ag/9 (ag) @0x7773eca8
Type: function definition analyzed
Visibility: public
next
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97194
Richard Biener changed:
What|Removed |Added
Target||x86_64-*-* i?86-*-*
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97194
Bug ID: 97194
Summary: optimize vector element set/extract at variable
position
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86419
--- Comment #12 from Dimitrij Mijoski ---
Hello Jonathan. I posted a patch for this bug which I hope you'll find it
useful once you start working on this.
https://gcc.gnu.org/pipermail/libstdc++/2020-September/051073.html
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97166
Alan Modra changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97166
--- Comment #4 from CVS Commits ---
The releases/gcc-10 branch has been updated by Alan Modra :
https://gcc.gnu.org/g:71c83e108de7b54f604eeebefbc9e97672310ca7
commit r10-8795-g71c83e108de7b54f604eeebefbc9e97672310ca7
Author: Alan Modra
Date:
Fixes the conversion from UTF-8 to UTF-16 to properly return partial
instead ok.
Fixes the conversion from UTF-16 to UTF-8 to properly return partial
instead ok.
Fixes the conversion from UTF-8 to UCS-2 to properly return partial
instead error.
Fixes the conversion from UTF-8 to UCS-2 to treat
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97166
--- Comment #3 from CVS Commits ---
The releases/gcc-10 branch has been updated by Alan Modra :
https://gcc.gnu.org/g:8f4b43c00feed11a6cedd4c40baa3cdcf687b3a1
commit r10-8794-g8f4b43c00feed11a6cedd4c40baa3cdcf687b3a1
Author: Alan Modra
Date:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91610
--- Comment #2 from Jakub Jelinek ---
Yeah, for -O0 we'd need a special mode of -fvar-tracking that would only track
the register vars or vars before they have their memory slot initialized.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91610
Eric Botcazou changed:
What|Removed |Added
CC||ebotcazou at gcc dot gnu.org
"Hu, Jiangping" writes:
> Hi,
>
> I find there are many "ATTRIBUTE_UNUSED" macros in the function parameter
> lists,
> but some of the parameters are used in the function bodies in fact. E.g.
>
> @@gcc/final.c
> void
> output_operand (rtx x, int code ATTRIBUTE_UNUSED)
> {
> if (x
On Thu, Sep 24, 2020 at 10:21 AM xionghu luo wrote:
>
> Hi Segher,
>
> The attached two patches are updated and split from
> "[PATCH v2 2/2] rs6000: Expand vec_insert in expander instead of gimple
> [PR79251]"
> as your comments.
>
>
> [PATCH v3 2/3] rs6000: Fix lvsl mode and change
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97186
Nathan Sidwell changed:
What|Removed |Added
Resolution|--- |FIXED
Status|ASSIGNED
This fixes an ICE in noexcept instantiation. It was presuming
functions always have template_info, but that changed with my
DECL_LOCAL_DECL_P changes. Fortunately DECL_LOCAL_DECL_P fns are
never member fns, so we don't need to go fishing out a this pointer.
Also I realized I'd misnamed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97186
--- Comment #3 from CVS Commits ---
The master branch has been updated by Nathan Sidwell :
https://gcc.gnu.org/g:2e66e53b1efb98f5cf6b0a123990c1ca999affd7
commit r11-3436-g2e66e53b1efb98f5cf6b0a123990c1ca999affd7
Author: Nathan Sidwell
Date:
Ping?
On Mon, 7 Sep 2020 at 18:13, Christophe Lyon wrote:
>
> Since r204778 (g571880a0a4c512195aa7d41929ba6795190887b2), we favor
> branches over IT blocks on Cortex-M. As a result, instead of
> generating two nested IT blocks in thumb2-cond-cmp-[1234].c, we
> generate either a single IT block,
On 24/09/20 11:11 +0200, Richard Biener wrote:
On Wed, 26 Aug 2020, Richard Biener wrote:
On Thu, 6 Aug 2020, Richard Biener wrote:
> On Thu, 6 Aug 2020, Richard Biener wrote:
>
> > This adds a move CTOR to auto_vec and makes use of a
> > auto_vec return value for get_loop_exit_edges denoting
The class template semiregular-box defined in [range.semi.wrap] is
used by a number of views to accomodate non-semiregular subobjects
while ensuring that the overall view remains semiregular. It provides
a stand-in default constructor, copy assignment operator and move
assignment operator
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97193
Martin Liška changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97193
Richard Biener changed:
What|Removed |Added
Keywords||documentation
--- Comment #1 from
On Thu, 24 Sep 2020, Tom de Vries wrote:
> On 9/24/20 1:42 PM, Richard Biener wrote:
> > On Wed, 23 Sep 2020, Tom de Vries wrote:
> >
> >> On 9/23/20 9:28 AM, Richard Biener wrote:
> >>> On Tue, 22 Sep 2020, Tom de Vries wrote:
> >>>
> [ was: Re: [Patch] [middle-end & nvptx] gcc/tracer.c:
On Wed, Sep 2, 2020 at 1:53 PM Martin Liška wrote:
>
> On 9/1/20 4:50 PM, David Malcolm wrote:
> > Hope this is constructive
> > Dave
>
> Thank you David. All of them very very useful!
>
> There's updated version of the patch.
I noticed several functions without a function-level comment.
-
xionghu luo writes:
> @@ -2658,6 +2659,43 @@ expand_vect_cond_mask_optab_fn (internal_fn, gcall
> *stmt, convert_optab optab)
>
> #define expand_vec_cond_mask_optab_fn expand_vect_cond_mask_optab_fn
>
> +/* Expand VEC_SET internal functions. */
> +
> +static void
> +expand_vec_set_optab_fn
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97127
--- Comment #13 from Michael_S ---
(In reply to Hongtao.liu from comment #11)
> (In reply to Michael_S from comment #10)
> > (In reply to Hongtao.liu from comment #9)
> > > (In reply to Michael_S from comment #8)
> > > > What are values of gcc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97186
--- Comment #2 from Nathan Sidwell ---
The error abount conversion failure, if it is a bug, is unrelated to the ICE.
I say 'if', because I think there have been changes in regards to whether
functions decay to pointers which can be implicitly
Hi,
With nvptx, we run into:
...
FAIL: gcc.dg/tls/thr-cse-1.c scan-assembler-not \
emutls_get_address.*emutls_get_address.*
...
because the nvptx assembly looks like:
...
call (%value_in), __emutls_get_address, (%out_arg1);
...
// BEGIN GLOBAL FUNCTION DECL: __emutls_get_address
.extern
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97193
Bug ID: 97193
Summary: .gcno files are not written to same directory as the
object file
Product: gcc
Version: 9.3.0
Status: UNCONFIRMED
Severity: normal
On Wed, 23 Sep 2020 at 17:50, Christophe Lyon
wrote:
>
> On Wed, 23 Sep 2020 at 17:33, Martin Sebor wrote:
> >
> > On 9/23/20 2:54 AM, Christophe Lyon wrote:
> > > On Wed, 23 Sep 2020 at 01:47, Martin Sebor wrote:
> > >>
> > >> On 9/22/20 9:15 AM, Christophe Lyon wrote:
> > >>> On Tue, 22 Sep
On 9/24/20 1:42 PM, Richard Biener wrote:
> On Wed, 23 Sep 2020, Tom de Vries wrote:
>
>> On 9/23/20 9:28 AM, Richard Biener wrote:
>>> On Tue, 22 Sep 2020, Tom de Vries wrote:
>>>
[ was: Re: [Patch] [middle-end & nvptx] gcc/tracer.c: Don't split BB
with SIMT LANE [PR95654] ]
Hi,
"duanbo (C)" writes:
> Sorry for the late reply.
My time to apologise for the late reply.
> Thanks for your suggestions. I have modified accordingly.
> Attached please find the v1 patch.
Thanks, the logic to choose which precision we pick looks good.
But I think the
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97186
Nathan Sidwell changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |nathan at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97192
--- Comment #2 from Zdenek Sojka ---
Sorry for the dup. I used gcc built this morning, and I didn't find PR97085,
since it was closed in the meantime.
On Wed, 23 Sep 2020, Tom de Vries wrote:
> On 9/23/20 9:28 AM, Richard Biener wrote:
> > On Tue, 22 Sep 2020, Tom de Vries wrote:
> >
> >> [ was: Re: [Patch] [middle-end & nvptx] gcc/tracer.c: Don't split BB
> >> with SIMT LANE [PR95654] ]
> >>
> >> On 9/16/20 8:20 PM, Alexander Monakov wrote:
>
Hi,
When running test-case gcc.dg/independent-cloneids-1.c for nvptx, we get:
...
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]0: 1
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]1: 1
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]2: 1
FAIL: scan-assembler-times
On Thu, Sep 24, 2020 at 1:26 PM Jan Hubicka wrote:
>
> > >
> > > I will do (but need to think bit of a redundancy between comment in
> > > ipa-modref and ipa-modref-tree)
> >
> > One place is enough - just add a pointer to the other place.
> Here is updated patch I am testing. I adds
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97085
--- Comment #11 from CVS Commits ---
The master branch has been updated by Richard Biener :
https://gcc.gnu.org/g:a8d5c28233f95e3474ee8cbc4d341cbb43ab7bb6
commit r11-3431-ga8d5c28233f95e3474ee8cbc4d341cbb43ab7bb6
Author: Richard Biener
Date:
This adds another testcase for the PR97085 fix.
Pused.
2020-09-24 Richard Biener
PR tree-optimization/97085
* gcc.dg/pr97192.c: New testcase.
---
gcc/testsuite/gcc.dg/pr97192.c | 16
1 file changed, 16 insertions(+)
create mode 100644
> >
> > I will do (but need to think bit of a redundancy between comment in
> > ipa-modref and ipa-modref-tree)
>
> One place is enough - just add a pointer to the other place.
Here is updated patch I am testing. I adds documentation into
ipa-modref-tree.h that is perhaps more natural place and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97192
Richard Biener changed:
What|Removed |Added
Resolution|--- |DUPLICATE
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97085
Richard Biener changed:
What|Removed |Added
CC||zsojka at seznam dot cz
--- Comment
On Thu, Sep 24, 2020 at 12:54 PM Jan Hubicka wrote:
>
> > > + else if (TREE_CODE (op) == SSA_NAME
> > > + && POINTER_TYPE_P (TREE_TYPE (op)))
> > > +{
> > > + if (DECL_P (base) && !ptr_deref_may_alias_decl_p (op, base))
> > > + return false;
> > > + if (TREE_CODE
On Thu, Sep 24, 2020 at 12:36 PM Prathamesh Kulkarni
wrote:
>
> On Wed, 23 Sep 2020 at 16:40, Richard Biener
> wrote:
> >
> > On Wed, Sep 23, 2020 at 12:11 PM Prathamesh Kulkarni
> > wrote:
> > >
> > > On Wed, 23 Sep 2020 at 13:22, Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Sep 22,
--disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r11-3421-20200924150219-gfff56af6421-checking-yes-rtl-df-extra-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 11.0.0 20200924 (experimental) (GCC)
> > + else if (TREE_CODE (op) == SSA_NAME
> > + && POINTER_TYPE_P (TREE_TYPE (op)))
> > +{
> > + if (DECL_P (base) && !ptr_deref_may_alias_decl_p (op, base))
> > + return false;
> > + if (TREE_CODE (base) == SSA_NAME
> > + && !ptr_derefs_may_alias_p (op,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96495
--- Comment #5 from CVS Commits ---
The master branch has been updated by Paul Thomas :
https://gcc.gnu.org/g:e86a02f87d8a11480c1421ef2dd71b8b5f43d938
commit r11-3430-ge86a02f87d8a11480c1421ef2dd71b8b5f43d938
Author: Paul Thomas
Date: Thu
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97127
--- Comment #12 from Hongtao.liu ---
Correct AVX256 load cost outside of register allocation and vectorizer
> they are
> 1. AVX256 Load 16
> 2. FMA3 ymm,ymm,ymm --- 16
> 3. AVX256 Regmove --- 2
> 4. FMA3 mem,ymm,ymm --- 32
That's why
Hi,
with nvptx we run into:
...
FAIL: gcc.dg/pr87314-1.c scan-assembler hellooo
...
The required string is part of the assembly, just in a different format than
expected:
...
.const .align 1 .u8 $LC0[12] =
{ 104, 101, 108, 108, 111, 111, 111, 111, 98, 121, 101, 0 };
...
Fix
On Thu, Sep 24, 2020 at 11:06 AM Jan Hubicka wrote:
>
> Hi,
> this patch re-adds tracking of accesses which was unfinished in David's patch.
> At the moment I only implemented tracking of the fact that access is based on
> derefernece of the parameter (so we track THIS pointers).
> Patch does not
On Wed, 23 Sep 2020 at 16:40, Richard Biener wrote:
>
> On Wed, Sep 23, 2020 at 12:11 PM Prathamesh Kulkarni
> wrote:
> >
> > On Wed, 23 Sep 2020 at 13:22, Richard Biener
> > wrote:
> > >
> > > On Tue, Sep 22, 2020 at 6:25 PM Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Tue, 22 Sep
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96394
Martin Liška changed:
What|Removed |Added
Target Milestone|--- |10.3
Priority|P3
Hi all,
I'd like to backport this fix from Tamar to the GCC 8 branch to avoid having
incorrectly-named intrinsics.
Tested on aarch64-none-elf.
Committing to the branch.
This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
to be more consistent with the naming
Hi all,
I'd like to backport this patch to the GCC 8 branch that implements intrinsics
that were (erroneously) missed out
of the initial implementation in GCC 8.
Bootstrapped and tested on aarch64-none-linux-gnu on the branch.
This patch adds the missing neon intrinsics for all 128 bit vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233
--- Comment #38 from CVS Commits ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
:
https://gcc.gnu.org/g:11e0e5fa724f9f6f979abe537d6485850abfe4d9
commit r8-10530-g11e0e5fa724f9f6f979abe537d6485850abfe4d9
Author: Tamar
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233
--- Comment #39 from CVS Commits ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
:
https://gcc.gnu.org/g:7409639ab568d0d4babcc17370816a2ddd112b72
commit r8-10531-g7409639ab568d0d4babcc17370816a2ddd112b72
Author: Tamar
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97181
--- Comment #3 from Jan Hubicka ---
> and then inline btsum.0. Notice how the possibility of level < 0 is left
> untouched ... [I think there are no unsigned types in fortran]
>
> That said, I don't think IPA-CP/VRP do this kind of "evolution
Hi,
On nvptx we run into:
...
FAIL: c-c++-common/ident-1b.c -Wc++-compat scan-assembler GCC:
FAIL: c-c++-common/ident-2b.c -Wc++-compat scan-assembler GCC:
...
Using a scan-assembler directive adds -fno-indent to the compile options.
The test c-c++-common/ident-1b.c adds dg-options
This fixes spurious complaints about PIC mode not supported
on "gcc --help=...", on VxWorks without -mrtp. The spurious message
is emitted by vxworks_override_options, called with flag_pic == -1
when we're running for --help.
The change simply adjusts the check testing for "we're generating pic
"iains at gcc dot gnu.org via Gcc-bugs" writes:
[...]
> unfortunately, I've not been able to test since you applied this - currently
> bootstrap is broken on aarch64-darwin for reasons outside our control (new
> security provisions stopping the gcc/build/gen* programs from running). If it
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96968
--- Comment #8 from Andrea Corallo ---
"iains at gcc dot gnu.org via Gcc-bugs" writes:
[...]
> unfortunately, I've not been able to test since you applied this - currently
> bootstrap is broken on aarch64-darwin for reasons outside our control
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96968
--- Comment #7 from Iain Sandoe ---
(In reply to Andrea Corallo from comment #6)
> I believe f5e73de00e9c853ce65333efada7409b0d00f758 should have fixed
> this.
>
> Okay to close?
unfortunately, I've not been able to test since you applied this
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97127
--- Comment #11 from Hongtao.liu ---
(In reply to Michael_S from comment #10)
> (In reply to Hongtao.liu from comment #9)
> > (In reply to Michael_S from comment #8)
> > > What are values of gcc "loop" cost of the relevant instructions now?
> >
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96968
--- Comment #6 from Andrea Corallo ---
I believe f5e73de00e9c853ce65333efada7409b0d00f758 should have fixed
this.
Okay to close?
Thanks
Andrea
I believe f5e73de00e9c853ce65333efada7409b0d00f758 should have fixed
this.
Okay to close?
Thanks
Andrea
On Thu, Sep 24, 2020 at 11:50 AM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Sep 24, 2020 at 11:41:00AM +0200, Tobias Burnus wrote:
> > Following Jakub's suggestion, I also added
> > __attribute__((used))
> > to the tree belonging to both tables in omp-offload.c's omp_finish
> > but that
On Thu, Sep 24, 2020 at 11:41 AM Tobias Burnus wrote:
>
> On 9/24/20 10:03 AM, Richard Biener wrote:
>
> >> The symbols are added to offload_vars + offload_funcs.
> >> In lto-cgraph.c's output_offload_tables there is the last chance
> >> to remove now unused nodes ? as once the tables are
Andrea Corallo writes:
> Kyrylo Tkachov writes:
[...]
>>
>> Can you please also backport it to the appropriate branches as well after
>> some time on trunk.
>> Thanks,
>> Kyrill
>
> Ciao Kyrill,
>
> Sure happy to do that. For now into trunk as 2c62952f816.
Backported into gcc-10 as
On Thu, Sep 24, 2020 at 11:41:00AM +0200, Tobias Burnus wrote:
> Following Jakub's suggestion, I also added
> __attribute__((used))
> to the tree belonging to both tables in omp-offload.c's omp_finish
> but that did not help, either.
That is really DECL_PRESERVED_P, the attribute is turned into
Hello,
After
https://gcc.gnu.org/pipermail/gcc-patches/2020-January/537843.html
and
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-12/msg01398.html
Re-proposing this patch after re-testing with a recent
mainline on on aarch64-linux (bootstrap and regression test
with --enable-languages=all),
On 9/24/20 10:03 AM, Richard Biener wrote:
The symbols are added to offload_vars + offload_funcs.
In lto-cgraph.c's output_offload_tables there is the last chance
to remove now unused nodes ? as once the tables are streamed
for device usage, they cannot be changed. Hence, there one
has
On 24/09/20 10:15 +0300, Antony Polukhin via Libstdc++ wrote:
Looks like the last patch was not applied. Do I have to change something in
it?
No, it just hasn't been reviewed yet.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96488
Eric Botcazou changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: 24 September 2020 10:01
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 8] aarch64: Add support for Neoverse V1 CPU
>
> This patch backports the AArch64 support
On Wed, 26 Aug 2020, Richard Biener wrote:
> On Thu, 6 Aug 2020, Richard Biener wrote:
>
> > On Thu, 6 Aug 2020, Richard Biener wrote:
> >
> > > This adds a move CTOR to auto_vec and makes use of a
> > > auto_vec return value for get_loop_exit_edges denoting
> > > that lifetime management of
On Fri, Sep 11, 2020 at 12:38 AM Pop, Sebastian via Gcc-patches
wrote:
>
> Hi,
>
> the attached patches are back-porting the flag -moutline-atomics to the
> gcc-7-arm vendor branch.
> The flag enables a very important performance optimization for N1-neoverse
> processors.
> The patches pass
Hi,
this patch re-adds tracking of accesses which was unfinished in David's patch.
At the moment I only implemented tracking of the fact that access is based on
derefernece of the parameter (so we track THIS pointers).
Patch does not implement IPA propagation since it needs bit more work which
I
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97107
Alan Modra changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Target|powerpc*
This patch backports the AArch64 support for Arm's Neoverse V1 CPU to
GCC 8.
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu.
OK for GCC 8 branch?
Thanks,
Alex
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse V1.
*
Kyrylo Tkachov writes:
> Hi Richard,
>
>> -Original Message-
>> From: Richard Sandiford
>> Sent: 23 September 2020 19:34
>> To: gcc-patches@gcc.gnu.org
>> Cc: ni...@redhat.com; Richard Earnshaw ;
>> Ramana Radhakrishnan ; Kyrylo
>> Tkachov
>> Subject: [PATCH] arm: Add a couple of extra
This patch backports the AArch64 support for Arm's Neoverse V1 CPU to
GCC 9.
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu.
OK for GCC 9 branch?
Thanks,
Alex
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse V1.
*
This patch backports the AArch64 support for Arm's Neoverse V1 CPU to
GCC 10.
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu.
OK for GCC 10 branch?
Thanks,
Alex
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse V1.
*
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97190
Richard Biener changed:
What|Removed |Added
Version|10.0|11.0
Target Milestone|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97191
Richard Biener changed:
What|Removed |Added
Ever confirmed|0 |1
Keywords|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96528
rsandifo at gcc dot gnu.org changed:
What|Removed |Added
CC||rsandifo at gcc dot
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96528
Richard Biener changed:
What|Removed |Added
Severity|enhancement |normal
CC|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97191
Bug ID: 97191
Summary: ICE In expand_expr_real_1, at expr.c:10234
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c++
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: 23 September 2020 19:34
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH] arm: Add a couple of extra stack-protector tests
>
> These
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: 23 September 2020 19:20
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov ; Kees Cook
> Subject: [PATCH] arm: Fix canary address calculation for non-PIC
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97127
--- Comment #10 from Michael_S ---
(In reply to Hongtao.liu from comment #9)
> (In reply to Michael_S from comment #8)
> > What are values of gcc "loop" cost of the relevant instructions now?
> > 1. AVX256 Load
> > 2. FMA3 ymm,ymm,ymm
> > 3.
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