[PATCH v3] vect: Verify that GET_MODE_UNITS is greater than one for vect_grouped_store_supported

. Bootstrap and testing done on x86_64-pc-linux-gnu. Would this be ok for trunk? Patch V1: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614463.html Patch V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614700.html Kevin Lee gcc/ChangeLog: * tree-vect-data-refs.cc

Re: [PATCH v2][RFC] vect: Verify that GET_MODE_NUNITS is greater than one for vect_grouped_store_supported

Thank you for the feedback Richard and Richard. > Note the calls are guarded with > > && ! known_eq (TYPE_VECTOR_SUBPARTS (vectype), 1U) Yes, I believe nelt.is_constant() wouldn't be necessary. I didn't realize the call was guarded by this condition. > But I think the better check for

Ping: [PATCH v2][RFC] vect: Verify that GET_MODE_NUNITS is greater than one for vect_grouped_store_supported

May I ping this patch? https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614700.html Any suggestions and comments would be appreciated. Thank you! Sincerely, Kevin Lee

[PATCH v2][RFC] vect: Verify that GET_MODE_NUNITS is greater than one for vect_grouped_store_supported

This patch is a proper fix to the previous patch https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614463.html vect_grouped_store_supported checks if the count is a power of 2, but doesn't check the size of the GET_MODE_NUNITS. This should handle the riscv case where the mode is VNx1DI since

[RFC][Patch] vect: verify that nelt is greater than one

and didn't cause more failures, but wasn't sure if total_elem would be used in the rest of the function. Should there be additional changes in the vect_grouped_store_supported? Thank you! gcc/ChangeLog: Kevin Lee * tree-vect-data-refs.cc (vect_grouped_store_supported): Check if the nelt

[PATCH v3] RISC-V missing __builtin_lceil and __builtin_lfloor

for commit? gcc/ChangeLog: Michael Collison Kevin Lee * config/riscv/iterators.md (RINT): Additional iterators. (rint_pattern): Additional attributes. (rint_rm): Ditto. * config/riscv/riscv.md (UNSPEC_LCEIL): New unspec. (UNSPEC_LFLO

[PATCH] RISC-V uninit-pred-9_b.c failure

The gimple generated by riscv is identical to that of powerpc64 currently. It seems like the change at r12-4790-4b3a325f07acebf47e82de227ce1d5ba62f5bcae also affected riscv64 like powerpc64 and cris. gcc/testsuite/ChangeLog: * gcc.dg/uninit-pred-9_b.c: Xfail for riscv64 ---

Re: [PATCH v2] RISC-V missing __builtin_lceil and __builtin_lfloor

On Wed, Nov 9, 2022 at 1:49 AM Xi Ruoyao wrote: > > On Mon, 2022-11-07 at 20:36 -0800, Kevin Lee wrote: > I "shamelessly copied" your idea in > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605456.html. > During the review we found an issue. > > -

Re: Different outputs in Gimple pass dump generated by two different architectures

On Fri, Nov 11, 2022 at 8:39 AM Andrew Pinski wrote: > > On Fri, Nov 11, 2022 at 12:57 AM Marc Glisse via Gcc wrote: > > > > On Thu, 10 Nov 2022, Kevin Lee wrote: > > > What would be causing the difference? Is this intended? Link > > > <https://godbolt.

Different outputs in Gimple pass dump generated by two different architectures

Hello GCC, While looking at the failure for gcc.dg/uninit-pred-9_b.c, I observed that x86-64 and risc-v has a different output for the gimple pass since r12-4790-g4b3a325f07acebf4 . What would be causing the difference? Is this

[PATCH v2] RISC-V missing __builtin_lceil and __builtin_lfloor

attributes. (rint_rm): Ditto. * config/riscv/riscv.md: New attributes. gcc/testsuite/ChangeLog: Kevin Lee * gcc.target/riscv/lfloor-lceil.c: New test. --- gcc/config/riscv/iterators.md | 8 +- gcc/config/riscv/riscv.md | 3

Re: [PATCH] RISC-V missing __builtin_lceil and __builtin_lfloor

s > floating around on a branch and hopefully that'll remind me to commit > it after I sort that out. Currently, the testsuite doesn't show additional failures. It seems like the corrupted patch caused the issue. I will post the clean patch as v2. Thank you for the review! On Sun, Oct 2, 2022 at

[PATCH v3] RISC-V modified add3 for large stack frame optimization [PR105733]

Thank you for the review Jeff! I am currently looking into this issue in a different patch. I'll come back with some improvement. gcc/ChangeLog: Jim Wilson Michael Collison Kevin Lee * config/riscv/predicates.md (const_lui_operand): New Predicate. (add_operand):

[PATCH v2] RISC-V modified add3 for large stack frame optimization [PR105733]

/ rv32imafdc / rv32imac and no additional failures were detected in the testsuite. gcc/ChangeLog: Jim Wilson Michael Collison Kevin Lee * config/riscv/predicates.md (const_lui_operand): New Predicate. (add_operand): Ditto. (reg_or_const_int_operand): Ditto. * config/riscv/riscv-protos.h

Re: [PATCH] RISC-V missing __builtin_lceil and __builtin_lfloor

gt; >> >Michael Collison > >> > * config/riscv/riscv.md (RINT): Add iterator for lceil and > >> lround. > >> > (rint_pattern): Add ceil and floor. > >> > (rint_rm): Add rup and rdn. > >> > > >

Re: [PATCH] RISC-V modified add3 for large stack frame optimization [PR105733]

de some data including code size and performance? add is > frequently used patten, so we should more careful when changing that. > > Kevin Lee 於 2022年9月19日 週一，18:07寫道： > >> Hello GCC, >> Started from Jim Wilson's patch in >> >> https://github.com/riscv-admin/risc

[PATCH] RISC-V modified add3 for large stack frame optimization [PR105733]

++ | gfortran | rv64gc/ lp64d/ medlow |4 / 4 | 13 / 4 |0 / 0 | No additional failures were created from the testsuite. gcc/ChangeLog: Jim Wilson Michael Collison Kevin Lee * config/riscv/predicates.md (const_lui_operand): New predicate. (add_operand): Ditto

[PATCH] RISC-V missing __builtin_lceil and __builtin_lfloor

. (rint_rm): Add rup and rdn. gcc/testsuite/ChangeLog: Kevin Lee * gcc.target/riscv/lfloor-lceil.c: New test. --- gcc/config/riscv/riscv.md | 13 ++- gcc/testsuite/gcc.target/riscv/lfloor-lceil.c | 79 +++ 2 files changed, 88 insertions(+), 4