On 23 June 2015 at 09:49, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
This patch moves the instruction fusion pairs from a set of #defines
to an enum which we can generate from a .def file.
We'll use that .def file again, and the friendly names it introduces
shortly.
OK?
On 23 June 2015 at 09:49, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
The FMA steering pass should be enabled through the tuning structures
rather than be an intrinsic property of the core. This patch moves
the control of the pass to the tuning structures - turning it off for
On 23 June 2015 at 14:02, Jiong Wang jiong.w...@arm.com wrote:
Marcus Shawcroft writes:
On 20 May 2015 at 11:21, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.md: (ldr_got_small_mode): Support new GOT
relocation
modifiers.
(ldr_got_small_sidi): Ditto
On 20 May 2015 at 11:21, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/aarch64.md: (ldr_got_small_mode): Support new GOT
relocation
modifiers.
(ldr_got_small_sidi): Ditto.
* config/aarch64/iterators.md (got_modifier): New mode iterator.
*
On 18 June 2015 at 20:17, Christophe Lyon christophe.l...@linaro.org wrote:
Hi,
While backporting the fix for PR62308 from trunk to 4.9-branch, it
appeared that a testcase would be useful.
Here it is. I'll send another email to request the backport of the fix
+ testcase to the 4.9-branch.
On 4 June 2015 at 10:16, Matthew Wahab matthew.wa...@arm.com wrote:
gcc/
2015-06-4 Matthew Wahab matthew.wa...@arm.com
* config/aarch64/aarch64-arches.def: Add armv8.1-a.
* config/aarch64/aarch64-options-extensions.def: Update fP,
simd and crypto. Add lse, pan,
On 12 June 2015 at 21:43, Jim Wilson jim.wil...@linaro.org wrote:
We have 5 patterns that can emit the movi instruction. These patterns
map it to 4 different type attributes. The movmode_aarch64 pattern
uses mov_imm. The movdi_aarch64 pattern uses fmov. The movtf_aarch64
pattern uses
On 4 June 2015 at 01:35, Jim Wilson jim.wil...@linaro.org wrote:
I noticed that poor code is emitted for a long double 0.0. This testcase
long double sub (void) { return 0.0; }
void sub2 (long double *ld) { *ld = 0.0; }
currently generates
sub:
ldr q0, .LC0
ret
...
sub2:
ldr q0, .LC1
On 29 May 2015 at 09:32, Shiva Chen shiva0...@gmail.com wrote:
Hi, Andrew
I modify the patch as you suggestion and testing on 32/64 bit host.
Thanks your tips.
I really appreciate for your help.
Shiva
OK and committed with this ChangeLog:
2015-06-14 Shiva Chen shiva0...@gmail.com
*
On 10 June 2015 at 11:06, weixiangyu weixian...@huawei.com wrote:
Another backport patch which fixes a csmith ICE problem. Rebased on the
latest 4.9 branch.
Tested ok on aarch64-linux with qemu.
Hi, The attached patch contains a ChangeLog diff but no code diff.
The patch r210497 on mainline
: James Greenhalgh [mailto:james.greenha...@arm.com]
Sent: Thursday, May 28, 2015 9:58 PM
To: weixiangyu
Cc: gcc-patches@gcc.gnu.org; Marcus Shawcroft; Richard Earnshaw; Yangfei
(Felix)
Subject: Re: backport the fixes of PR target/64011 and /61749 to 4.9 gcc
On Wed, May 27, 2015 at 03:49:24AM +0100
On 4 June 2015 at 14:36, Renlin Li renlin...@arm.com wrote:
Hi Marcus,
Sorry for the delay. I have come up with an updated patch. Two test cases
are added to check against the limit.
__ARM_ALIGN_MAX_STACK_PWR is hard coded into 16.
__ARM_ALIGN_MAX_PWR is hard coded into 28 which is the
On 2 June 2015 at 10:30, Renlin Li renlin...@arm.com wrote:
Is it Okay for me to backport it to gcc-5?
OK provided the patch applies cleanly and there are no regressions. /Marcus
Regards,
Renlin Li
On 30/04/15 16:21, Marcus Shawcroft wrote:
On 30 April 2015 at 12:55, Renlin Li renlin
On 18 May 2015 at 15:57, Szabolcs Nagy szabolcs.n...@arm.com wrote:
Rewrote the generator script in awk, to avoid dealing with
sed portability issues.
gcc/Changelog:
2015-05-18 Szabolcs Nagy szabolcs.n...@arm.com
PR target/66136
* config/aarch64/geniterators.sh: Rewrite
Attached updated patch:
- Expanded the comment for aarch64_emit_post_barrier.
- Used 'barrier' rather than 'fence' in comments.
- Simplified the code for the initial load.
Tested with check-gcc for aarch64-none-linux-gnu.
Ok?
Matthew
2015-06-01 Matthew Wahab matthew.wa...@arm.com
On 5 May 2015 at 12:07, Christian Bruel christian.br...@st.com wrote:
This fixes PR target/66015 and a latent issue revealed by
gcc.dg/ipa/iinline-attr.c since
https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01609.html
Regtested on aarch64-linux-gnu by Linaro.
OK for trunk ?
OK. Is this
On 4 May 2015 at 10:13, Chen Shanyao chenshan...@huawei.com wrote:
According to your opinion, I split the backports of pr64304 into 2 emails,
and this one is for 4.9 branch.
This patch backport the fix of PR target/64304 , miscompilation with
-mgeneral-regs-only, to the 4.9 branch from trunk
On 4 May 2015 at 09:58, Yvan Roux yvan.r...@linaro.org wrote:
Yes this is a better formulation.
+corresponding flag to the linker. It can be explicitly disabled
during
+compilation by passing the @option{-mno-fix-cortex-a53-835769} option.
Copy paste error here with the previous errata
On 17 April 2015 at 16:40, Alan Lawrence alan.lawre...@arm.com wrote:
This just adds the necessary patterns used for comparisons of DImode
vectors. Used as part of arm_neon.h, in next/final patch.
Tested on aarch64-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
On 17 April 2015 at 16:41, Alan Lawrence alan.lawre...@arm.com wrote:
This also makes the existing intrinsics tests apply to the new patterns.
Tested on aarch64-none-elf.
gcc/ChangeLog:
* config/aarch64/arm_neon.h (vceq_s64, vceq_u64, vceqz_s64,
vceqz_u64,
vcge_s64,
On 1 May 2015 at 14:56, Yvan Roux yvan.r...@linaro.org wrote:
2015-05-01 Yvan Roux yvan.r...@linaro.org
* configure.ac: Add --enable-fix-cortex-a53-843419 option.
* configure: Regenerate.
* config/aarch64/aarch64-elf-raw.h (CA53_ERR_843419_SPEC): Define.
(LINK_SPEC):
On 1 May 2015 at 16:30, Renlin Li renlin...@arm.com wrote:
Thank you, Marcus. I have updated the patch accordingly, please check..
Regards,
Renlin Li
OK, thanks /Marcus
On 1 May 2015 at 09:25, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-05-01 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Do not overwrite cost
with COSTS_N_INSNS (1).
OK /Marcus
On 1 May 2015 at 09:20, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-05-01 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case):
Add cost of op0 in the compare-with-fpzero case.
ok /Marcus
On 21 April 2015 at 17:10, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to generate a move instruction to temporarily hold
the large immediate for a add instruction.
GCC regression test has been run using aarch64-none-elf toolchain. NO new
issues.
Okay for trunk?
On 4 March 2015 at 15:37, Wilco Dijkstra wdijk...@arm.com wrote:
Include the cost of op0 and op1 in all cases in PLUS and MINUS in
aarch64_rtx_costs.
Bootstrap regression OK.
ChangeLog:
2015-03-04 Wilco Dijkstra wdijk...@arm.com
* gcc/config/aarch64/aarch64.c
On 27 April 2015 at 14:43, Wilco Dijkstra wdijk...@arm.com wrote:
static unsigned int
-aarch64_min_divisions_for_recip_mul (enum machine_mode mode
ATTRIBUTE_UNUSED)
+aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
{
- return 2;
+ if (GET_MODE_UNIT_SIZE (mode) == 4)
+
On 21 April 2015 at 15:00, Matthew Wahab matthew.wa...@arm.com wrote:
2015-05-21 Matthew Wahab matthew.wa...@arm.com
* gcc/config/aarch64-protos.h (struct cpu_branch_cost): New.
(tune_params): Add field branch_costs.
(aarch64_branch_cost): Declare.
*
On 1 May 2015 at 10:11, Yvan Roux yvan.r...@linaro.org wrote:
Hi all,
As described in the thread bellow, there is a link-time workaround for
an erratum (843419) of some early revision of Cortex-A53. Similarly
to what was done for a previous erratum, this patch adds a new
configure-time
On 30 April 2015 at 20:38, Christophe Lyon christophe.l...@linaro.org wrote:
This is a cleanup of the series of tests I added some time ago.
During the latest reviews, I got comments about the fact that some
intrinsics do not support all the vector types but the corresponding
tests would
On 1 May 2015 at 09:21, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-05-01 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle FLOAT and
UNSIGNED_FLOAT.
OK /Marcus
On 23 March 2015 at 17:06, Szabolcs Nagy szabolcs.n...@arm.com wrote:
GCC can be compiled for aarch64 target with busybox sed except for
the geniterators.sh script which uses nonstandard basic regex.
I explicitly set LC_ALL=C too because the regex depends on collation
order.
I tested that
On 1 May 2015 at 12:26, Wilco Dijkstra wdijk...@arm.com wrote:
Marcus Shawcroft wrote:
On 27 April 2015 at 14:43, Wilco Dijkstra wdijk...@arm.com wrote:
static unsigned int
-aarch64_min_divisions_for_recip_mul (enum machine_mode mode
ATTRIBUTE_UNUSED
On 20 April 2015 at 17:48, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
When calculating the rtx costs of an arithmetic operation combined with
zero or sign extension of its operand we should use the extend_arith
cost rather than the arith_shift cost.
Bootstrapped and tested on
On 20 April 2015 at 17:35, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The aarch64_rtx_mult_cost helper is supposed to handle multiplication costs
as well as
PLUS/MINUS operations combined with multiplication or shift operations. The
shift
operations may contain an extension.
On 20 April 2015 at 17:36, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Currently we do not handle the MNEG patterns properly in rtx costs.
These instructions are similar to the MSUB ones.
This patch handles them by catching the NEG at the appropriate position,
extracting its
On 27 April 2015 at 14:24, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-27 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs, MINUS):
Properly account for both operand costs in simple case.
OK /Marcus
On 30 April 2015 at 12:55, Renlin Li renlin...@arm.com wrote:
2015-04-30 Renlin Li renlin...@arm.com
* config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec.
* config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHR.
gcc/testsuite/ChangeLog:
2015-04-30 Renlin Li
On 30 April 2015 at 16:22, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 22 April 2015 at 17:18, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-22 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/arm/arm.c (arm_new_rtx_costs): Do not lower cost
immediate moves.
OK
On 27 April 2015 at 11:01, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-27 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.md (*extrmode5_insn_alt): New pattern.
(*extrsi5_insn_uxtw_alt): Likewise.
* config/aarch64/aarch64.c (aarch64_extr_rtx_p): New
On 22 April 2015 at 17:18, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-22 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/arm/arm.c (arm_new_rtx_costs): Do not lower cost
immediate moves.
OK
/Marcus
On 23 April 2015 at 17:57, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-23 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.md
(*eor_one_cmpl_SHIFT:optabmode3_alt):
New pattern.
(*eor_one_cmpl_SHIFT:optabsidi3_alt_ze): Likewise.
*
On 22 April 2015 at 17:01, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2015-04-22 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle pattern for
fabd in ABS case.
OK /Marcus
On 29 April 2015 at 01:24, Andrew Pinski pins...@gmail.com wrote:
On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros into
aarch64 backend.
They are __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR.
On 28 April 2015 at 16:41, Renlin Li renlin...@arm.com wrote:
Hi all,
unsigned shift left dosen't support immediate shift. Previouly, gcc will
generate asm instruction like this: ushl d1, d0, 32, which is not a legal
insn and will be rejected by assembler. This patch change the use of ushl in
On 16 April 2015 at 18:27, Alan Lawrence alan.lawre...@arm.com wrote:
As per bugzilla entry, indices in the generated assembly for bigendian are
flipped when they should not be (and, flipped always relative to a
Q-register!).
This flips the lane indices back again at assembly time, fixing PR.
Picking up this old back port request...
On 5 March 2015 at 06:36, Chen Shanyao chenshan...@huawei.com wrote:
+2015-03-05 Shanyao Chenchenshan...@huawei.com
There should be two spaces after the date and two before the marker
in a ChangeLog name line. This comment applies to each of the
On 16 December 2014 at 10:19, Renlin Li renlin...@arm.com wrote:
2014-12-16 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.h(TARGET_CPU_CPP_BUILTINS): Define
__ARM_ALIGN_MAX_PWR
and __ARM_ALIGN_MAX_STACK_PWR.
OK /Marcus
On 22 April 2015 at 16:08, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 22/04/15 12:46, Kyrill Tkachov wrote:
[Sorry for resending twice. My mail client glitched]
+/* Native CPU detection for aarch64.
+ Copyright (C) 2014 Free Software Foundation, Inc.
+
That should be 2015, otherwise
On 23 April 2015 at 17:36, Jakub Jelinek ja...@redhat.com wrote:
Hi!
This patch undoes the PR65780 performance regressions on a few targets
I have tested to work fine.
This PR was about an access to uninitialized COMMON symbol defined in
executable (or PIE) where there is a normal symbol
On 20 April 2015 at 16:12, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Thanks,
I could've sworn I had sent this version out a couple hours ago.
My mail client has been playing up.
Here it is with 6 tests. For the tests corresponding to f1/f3 in my
example above I scan that we don't use the
On 26 February 2015 at 06:22, Xingxing Pan xxing...@marvell.com wrote:
Hi,
This patch fix the type of movmode_aarch64 in aarch64.md.
Is it OK for trunk?
OK, thank you /Marcus
On 25 February 2015 at 09:53, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 13/02/15 10:14, Richard Earnshaw wrote:
On 13/02/15 09:52, Kyrill Tkachov wrote:
Hi all,
This patch to changes.html mentions the xgene1 support in GCC 5 for arm
and aarch64 and also the FreeBSD support for ARM.
case SYMBOL_SMALL_GOTTPREL:
{
- rtx tmp_reg = gen_reg_rtx (Pmode);
+ /* In ILP32, the mode of dest can be either SImode or DImode,
+ while the got entry is always of SImode size. The mode of
+ dest depends on how dest is used: if dest is assigned to
On 18 February 2015 at 11:35, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Ok for trunk and 4.9?
Thanks,
Kyrill
2015-02-17 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_mode3):
Mark operand 0 as earlyclobber in 2nd alternative.
On 11 February 2015 at 10:57, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
PR target/64997
* config/aarch64/aarch64.md (*xor_one_cmplmode3): Use FP_REGNUM_P
as split condition; force split via '#' in output pattern.
OK /Marcus
On 18 February 2015 at 04:45, Hurugalawadi, Naveen
naveen.hurugalaw...@caviumnetworks.com wrote:
Hi Marcus,
Thanks for the review.
OK, but fix the trailing white space in the patch
Done. Committed with the modification.
Can you prepare a backport into 4.9
ILP32 support is not
On 9 February 2015 at 05:41, Andrew Pinski pins...@gmail.com wrote:
The problem here is that we get a symbol_ref which is SImode but for
the sibcall patterns we only match symbol_refs which use DImode. I
added a new testcase that tests the non-value sibcall pattern too.
OK? Bootstrapped and
On 2 February 2015 at 04:51, Hurugalawadi, Naveen
naveen.hurugalaw...@caviumnetworks.com wrote:
Hi,
Please find attached the patch that handles the operations on
SYMBOL_SMALL_TPREL appropriately.
It fixes gcc.dg/tls/opt-11.c regression on ilp32.
Please review the patch and let us know if
On 8 February 2015 at 02:24, Andrew Pinski pins...@gmail.com wrote:
Here is the updated patch with Jakub's comments included and added a
testcase for the 0, 0 case.
Thanks,
Andrew Pinski
ChangeLog:
PR target/64893
* config/aarch64/aarch64-builtins.c
On 10 February 2015 at 16:06, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
As is already done for mips and hppa, we should XFAIL this test on
AArch64 as we don't currently use the store_by_pieces infrastructure.
We may in future want to tweak this, but for GCC 5.0 the safe thing
to
On 4 February 2015 at 17:34, Gerald Pfeifer ger...@pfeifer.com wrote:
On Wednesday 2015-02-04 16:19, Matthew Wahab wrote:
This patch documents in gcc-5/changes.html the addition of support for the
Cortex-A72 to the ARM and the AArch64 backends.
Looks good to me, but you may want to wait a
On 28 January 2015 at 10:01, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
Hi Andrew,
cortex-a57-fma-steering.c is really meant to be autosufficient with
On 12 January 2015 at 15:52, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
As raised in https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01237.html and
discussed in that thread, using __builtin_sqrt for vsqrt_f64 may end up in a
call to the library sqrt at -O0. To avoid that this patch
On 4 February 2015 at 12:18, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch makes use of std::swap in every peephole2 of aarch64-ldp-stp.md
instead of manually swapping rtxen.
No functional change, just a cleanup.
Bootstrapped and tested on aarch64.
I'm proposing this for
On 4 February 2015 at 10:35, Matthew Wahab matthew.wa...@arm.com wrote:
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as the
Cortex-A57. This patch adds support for the command line option
-mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option, only
On 4 February 2015 at 12:06, James Greenhalgh james.greenha...@arm.com wrote:
Hi,
HAVE_DESIGNATED_INITIALIZERS is not set for C++, so the NAMED_PARAM macros
using it provide false security when we compile aarch64.c. Removing this
is an obvious cleanup and gets rid of some confusing dead
2015-01-25 Christophe Lyon christophe.l...@linaro.org
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(_ARM_FPSRC): Add DN and AHP fields.
(clean_results): Force DN=1 on AArch64.
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
*
On 30 January 2015 at 12:09, Alan Lawrence alan.lawre...@arm.com wrote:
This was posted towards the end of stage 3, a few days before stage 4
started. Is it now too late to ping ?
--Alan
gcc/ChangeLog:
* config/aarch64/arm_neon.h (vst1_lane_f32, vst1_lane_f64,
On 28 January 2015 at 09:24, James Greenhalgh james.greenha...@arm.com wrote:
2015-01-28 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64-simd.md (aarch64_absmode): New.
* config/aarch64/aarch64-simd-builtins.def (abs): Split by
integer and
On 28 January 2015 at 17:41, Mike Stump mikest...@comcast.net wrote:
On Jan 27, 2015, at 8:24 AM, Alex Velenko alex.vele...@arm.com wrote:
This patch fixes aarch64/atomic-op-consume.c test to expect safe LDAXR
instruction to be generated when __ATOMIC_CONSUME semantics is requested.
Did you
On 27 January 2015 at 14:31, Jiong Wang jiong.w...@arm.com wrote:
2015-01-19 Ramana Radhakrishnan ramana.radhakrish...@arm.com
Jiong Wang jiong.w...@arm.com
gcc/
* config/aarch64/aarch64.md (tboptabmode1): Clobber CC reg instead
of scratch reg.
(cboptabmode1):
On 20 January 2015 at 15:28, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 17:24, Tejas Belagod tejas.bela...@arm.com wrote:
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
On 20 January 2015 at 15:34, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 19:29, Tejas Belagod tejas.bela...@arm.com wrote:
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+0x33, 0x33, 0x33, 0x33,
+
On 20 January 2015 at 14:57, Renlin Li renlin...@arm.com wrote:
gcc/ChangeLog:
2015-01-20 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Correct
the comment.
* config/aarch64/aarch64.md (tlsle_small_mode): Add left shift 12-bit
On 20 January 2015 at 15:24, Christophe Lyon christophe.l...@linaro.org wrote:
Here is an updated version, where I have removed a few more useless
variables than you noticed: the [u]int64x1 as well as the 128 bits
ones.
OK /Marcus
On 20 January 2015 at 15:35, Christophe Lyon christophe.l...@linaro.org wrote:
Hmm changed my mind: vpaddl takes only one vector as input, although
it does add 2 vector elements.
Here is an updated version, removing poly, float and int8 variants.
OK /Marcus
On 20 January 2015 at 15:33, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 19:27, Tejas Belagod tejas.bela...@arm.com wrote:
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x, 0x, 0x, 0x,
+0x, 0x, 0x,
On 20 January 2015 at 15:32, Christophe Lyon christophe.l...@linaro.org wrote:
No poly or float for vmovl.
Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2
variants are necessary.
This version is OK /Marcus
On 20 January 2015 at 15:30, Christophe Lyon christophe.l...@linaro.org wrote:
+ /* Apply a unary operator named INSN_NAME. */
Unary op?
Hmm cut paste issue. Thanks
Here is an updated versoin, also renaming VPADD into VPXXX, since it's
in a template.
Updated version is OK /Marcus
On 19/01/15 21:05, James Greenhalgh wrote:
On Mon, Jan 19, 2015 at 08:57:31PM +, Gerald Pfeifer wrote:
On Monday 2015-01-19 17:52, James Greenhalgh wrote:
OK after the Cortex-A57 scheduling description goes in to the ARM port?
Yes, thanks, except that once will be sufficient. ;-) (The
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
OK
On 16 January 2015 at 18:06, Tejas Belagod tejas.bela...@arm.com wrote:
+
+void vsri_extra(void)
+{
+/* Test cases with maximum shift amount (this amount is different
+ * from vsli. */
+
Nit. Comment Formatting. Similarly, few other places.
Otherwise, LGTM.
Tejas.
w.r.t the
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
On 16 December 2014 at 11:26, Yangfei (Felix) felix.y...@huawei.com wrote:
The v3 patch attached fixed this minor issue. Thanks.
+2014-12-13 Felix Yang felix.y...@huawei.com
+ Haijian Zhang z.zhanghaij...@huawei.com
+
+ *
On 16 January 2015 at 18:12, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 16:20, Tejas Belagod tejas.bela...@arm.com wrote:
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
Thanks, I should mention
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
On 16 January 2015 at 18:10, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 16:58, Tejas Belagod tejas.bela...@arm.com wrote:
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
*
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
OK
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
On 16 January 2015 at 11:17, Jiong Wang jiong.w...@arm.com wrote:
exactly, thanks, we should use FAIL although DONE and FAIL work the same in
this scenario.
I checked their definition, FAIL always return the initial value of _val
which is NULL,
while DONE stop and return generated insns
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
OK /Marcus
On 16 January 2015 at 16:54, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-01-16 Kyrylo Tkachov kyrylo.tkac...@arm.com
PR target/64448
* config/aarch64/aarch64-simd.md (aarch64_simd_bslmode_internal):
Match xor-and-xor RTL pattern.
OK /Marcus
On 16 January 2015 at 17:52, Christophe Lyon christophe.l...@linaro.org wrote:
OK provided, as per the previous couple, that we don;t regression or
introduce new fails on aarch64[_be] or aarch32.
This patch shows failures on aarch64 and aarch64_be for vmax and vmin
when the input is -NaN.
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
OK with the
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c:
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
OK /Marcus
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