On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c: New file.
OK /Marcus
On 13 January 2015 at 15:17, Christophe Lyon christophe.l...@linaro.org wrote:
This patch series is a follow-up of the conversion of my existing
testsuite into DejaGnu. It does not yet cover all the tests I wrote,
but I chose to post this set to have a chance to have it accepted
before stage
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: New file.
OK /Marcus
On 19 January 2015 at 15:43, Christophe Lyon christophe.l...@linaro.org wrote:
On 19 January 2015 at 14:29, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 16 January 2015 at 17:52, Christophe Lyon christophe.l...@linaro.org
wrote:
OK provided, as per the previous couple, that we don
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c: New file.
OK /Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c: New file.
OK
/Marcus
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
OK /Marcus
On 15 January 2015 at 15:38, Renlin Li renlin...@arm.com wrote:
gcc/testsuite/ChangeLog:
2015-01-15 Renlin Li renlin...@arm.com
* gcc.dg/builtin-apply2.c: Remove aarch64 target from skip list.
OK /Marcus
On 15 January 2015 at 09:50, James Greenhalgh james.greenha...@arm.com wrote:
2015-01-15 James Greenhalgh james.greenha...@arm.com
* config/arm/cortex-a57.md: New.
* config/aarch64/aarch64.md: Include it.
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
On 14 January 2015 at 15:31, Jiong Wang jiong.w...@arm.com wrote:
2015-01-15 Jiong. Wang (jiong.w...@arm.com)
gcc/
PR64304
* config/aarch64/aarch64.md (define_insn *ashlmode3_insn): Deleted.
(ashlmode3): Don't expand if operands[2] is not constant.
gcc/testsuite/
*
On 15 January 2015 at 18:18, Richard Henderson r...@redhat.com wrote:
On 12/15/2014 12:41 AM, Zhenqiang Chen wrote:
+(define_expand cmpmode
+ [(set (match_operand 0 cc_register )
+(match_operator:CC 1 aarch64_comparison_operator
+ [(match_operand:GPI 2 register_operand )
+
+2014-12-09 Felix Yang felix.y...@huawei.com
+
+ * config/aarch64/aarch64-simd.md (aarch64_maxmin_unspmode): New
+ pattern.
+ * config/aarch64/aarch64-simd-builtins.def (smaxp, sminp, umaxp,
+ uminp, smax_nanp, smin_nanp): New builtins.
+ *
On 12 January 2015 at 15:12, Matthew Wahab matthew.wa...@arm.com wrote:
2015-01-08 Matthew Wahab matthew.wa...@arm.com
PR target/64149
* config/aarch64/aarch64.opt: Remove lra option and aarch64_lra_flag
variable.
* config/aarch64/aarch64.c (TARGET_LRA_P):
On 12 December 2014 at 15:33, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-12-11 Kyrylo Tkachov kyrylo.tkac...@arm.com
Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/64263
* config/aarch64/aarch64.md (*movsi_aarch64): Don't split if the
On 13 January 2015 at 15:17, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(Set_Neon_Cumulative_Sat): Add parameter.
(__set_neon_cumulative_sat): Support new parameter.
*
On 13 January 2015 at 15:18, Christophe Lyon christophe.l...@linaro.org wrote:
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
Add trace.
(CHECK_FP): Likewise.
(CHECK_CUMULATIVE_SAT): Likewise.
OK, provided no regressions and no new fails for
On 16 January 2015 at 16:21, Christophe Lyon christophe.l...@linaro.org wrote:
My existing tests only cover armv7 so far.
I do plan to expand them once they are all in GCC.
Otherwise, they look good to me(but I can't approve it).
Tejas.
OK provided, as per the previous couple, that we
On 16 January 2015 at 16:23, Christophe Lyon christophe.l...@linaro.org wrote:
On 16 January 2015 at 15:09, Tejas Belagod tejas.bela...@arm.com wrote:
On 13/01/15 15:18, Christophe Lyon wrote:
* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
Hmm.. again, I don't see
On 14 January 2015 at 07:35, Jeff Law l...@redhat.com wrote:
On 01/13/15 11:55, Eric Botcazou wrote:
(1) we have a non-paradoxical subreg;
(2) both (reg:ymode xregno) and (reg:xmode xregno) occupy full
hard registers (no padding or unused upper bits);
(3) (reg:ymode xregno) and
On 11 January 2015 at 02:37, Andrew Pinski pins...@gmail.com wrote:
On Tue, Nov 11, 2014 at 6:47 AM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 30 October 2014 08:54, Gopalasubramanian, Ganesh
ganesh.gopalasubraman...@amd.com wrote:
2014-10-30 Ganesh Gopalasubramanian
On 9 January 2015 at 16:31, Tejas Belagod tejas.bela...@arm.com wrote:
gcc/testsuite:
* gcc.target/aarch64/vect-movi.c: Check for vectorization for
64-bit and 128-bit.
OK /Marcus
On 7 January 2015 at 14:01, Renlin Li renlin...@arm.com wrote:
Is it Okay for branch 4.9?
gcc/ChangeLog:
2014-11-19 Renlin Li renlin...@arm.com
PR target/63424
* config/aarch64/aarch64-simd.md (sumaxminv2di3): New.
gcc/testsuite/ChangeLog:
2014-11-19 Renlin Li renlin...@arm.com
On 13 January 2015 at 10:47, Richard Sandiford
richard.sandif...@arm.com wrote:
Several sub-based patterns allowed the stack pointer to be the destination
but not the first source. This looked like an oversight; in all the patterns
changed here (but not for example in *sub_mul_imm_mode), the
On 13 January 2015 at 04:48, Andrew Pinski pins...@gmail.com wrote:
ChangeLog:
* config/aarch64/aarch64.c (fusion_load_store): Check dest mode
instead of src mode.
* gcc.target/aarch64/store-pair-1.c: New testcase.
OK, thanks /Marcus
On 12 January 2015 at 20:15, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
---
gcc/config/aarch64/aarch64.md | 1 +
gcc/config/arm/xgene1.md | 531
++
2 files changed, 532 insertions(+)
create mode 100644
On 10 December 2014 at 02:18, Andrew Pinski pins...@gmail.com wrote:
Hi,
As mentioned in
https://gcc.gnu.org/ml/gcc-patches/2014-12/msg00609.html, the
load/store pair peepholes currently accept volatile mem which can
cause wrong code as the architecture does not define which part of the
On 12 January 2015 at 20:15, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
+2014-11-19 Philipp Tomsich philipp.toms...@theobroma-systems.com
+
+ * config/aarch64/aarch64-cores.def (xgene1): Update/add the
+ xgene1 (APM XGene-1) core definition.
+ *
On 17 December 2014 at 16:19, Alan Lawrence alan.lawre...@arm.com wrote:
This seems to have slipped under the radar for awhile. Ping.
--Alan
The sshr_n_64 intrinsics allow performing a signed shift right by 64
places. The standard ashrdi3 pattern masks the sign amount with 63, so
cannot be
gcc/ChangeLog:
* config/aarch64/aarch64.md (enum unspec): Remove UNSPEC_SSHR64.
* config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change
shift
amount to 63 if was 64.
(aarch64_sshr_simddi): Remove.
OK /Marcus
On 17 December 2014 at 15:15, Tejas Belagod tejas.bela...@arm.com wrote:
It isn;t clear to me how far through the various BE patches we need to
get before 59810 is actually resolved?
David's 2 patches
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01431.html
On 8 September 2014 at 17:25, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift
by 64 by moving const0_rtx.
(aarch64_ushr_simddi): Delete.
* config/aarch64/aarch64.md (enum unspec):
On 12 December 2014 at 14:48, Wilco Dijkstra wdijk...@arm.com wrote:
This patch generalizes the code alignment and lets each CPU set function,
jump and loop alignment
independently. The defaults for A53/A57 are based the original patch by James
Greenhalgh.
OK for trunk?
ChangeLog:
On 12 December 2014 at 15:19, Wilco Dijkstra wdijk...@arm.com wrote:
Add an override for TARGET_MIN_DIVISIONS_FOR_RECIP_MUL and set the minimum
number of divisions to 2.
This gives ~0.5% speedup on SPECFP2000/2006.
OK for trunk?
ChangeLog:
2014-12-13 Wilco Dijkstra wdijk...@arm.com
On 23 November 2014 at 00:09, Andrew Pinski pins...@gmail.com wrote:
Hi,
This is just a rebase of
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01615.html as requested
by https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01736.html. Nothing
has changed in it.
OK? Built and tested on
On 10 December 2014 at 15:30, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-12-10 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (aarch64_parse_extension): Update error
message to say +no only when removing extension.
OK /Marcus
On 10 December 2014 at 13:58, Renlin Li renlin...@arm.com wrote:
This is a backport patch of
https://gcc.gnu.org/ml/gcc-patches/2014-12/msg00287.html
aarch64-none-elf has been built and tested on the model, no issue.
Okay for branch 4.9?
Regards,
Renlin Li
gcc/ChangeLog:
2014-12-10
On 10 December 2014 at 16:34, Renlin Li renlin...@arm.com wrote:
2014-12-10 Renlin Li renlin...@arm.com
* config/aarch64/aarch64-cores.def: Change all AARCH64_FL_FPSIMD to
AARCH64_FL_FOR_ARCH8.
* config/aarch64/aarch64.c (all_cores): Use FLAGS from aarch64-cores.def
file
On 11 December 2014 at 10:06, Bin Cheng bin.ch...@arm.com wrote:
gcc/testsuite/ChangeLog
2014-12-11 Bin Cheng bin.ch...@arm.com
* gcc.target/aarch64/ldp_stp_2.c: Make test less vulnerable.
* gcc.target/aarch64/ldp_stp_3.c: Ditto.
OK /Marcus
On 10 December 2014 at 09:51, Alan Hayward alan.hayw...@arm.com wrote:
This is a new version of my BE patch from a few weeks ago.
This is part 1 and covers rtlanal.c. The second part will be aarch64
specific.
When combined with the second patch, It fixes up movoi/ci/xi for Big
Endian, so that we
On 24 November 2014 at 13:46, Wilco Dijkstra wdijk...@arm.com wrote:
Richard Earnshaw wrote:
If all cores seem to benefit from FP reassociation set to 4, then it
seems odd that 4 is not also the default for generic.
Andrew, you may need to pick a target-specific value for ThunderX; I
think
On 5 December 2014 at 14:36, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Andrew posted this patch sometime ago (before stage1 closed) and I had
rebased it on top of the
other macro fusion patches in that series.
This is a respin of that patch with the comment about not calling
On 3 December 2014 at 10:30, Alan Lawrence alan.lawre...@arm.com wrote:
On Wed, Nov 26, 2014 at 04:35:50PM +, James Greenhalgh wrote:
Why do we want to turn off folding for the V4SF/V2SF/V2DF modes of these
intrinsics? There should be no difference between the mid-end definition
and the
On 24 November 2014 at 17:49, Andrew Pinski pins...@gmail.com wrote:
I had some local patches in my tree which adds a bswap tree code.
This breaks the aarch64 back-end vectorizing of byteswaps as we use
the standard mechanism to see if a tree code vectorizes (optabs).
Since it make sense to
On 18 November 2014 at 08:34, Bin Cheng bin.ch...@arm.com wrote:
2014-11-18 Bin Cheng bin.ch...@arm.com
* config/aarch64/aarch64.md (load_pairmode): Split to
load_pairsi, load_pairdi, load_pairsf and load_pairdf.
(load_pairsi, load_pairdi, load_pairsf, load_pairdf):
On 19 November 2014 at 06:14, Yangfei (Felix) felix.y...@huawei.com wrote:
Index: gcc/ChangeLog
===
--- gcc/ChangeLog (revision 217717)
+++ gcc/ChangeLog (working copy)
@@ -1,3 +1,14 @@
+2014-11-13 Felix Yang
On 21 November 2014 at 18:44, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
+;; Machine description for AppliedMicro xgene1 core.
+;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
+;; Contributed by Theobroma Systems Design und Consulting GmbH.
+;;See
On 3 December 2014 at 15:30, Renlin Li renlin...@arm.com wrote:
2014-12-03 Renlin Li renlin...@arm.com
* config/aarch64/aarch64-opts.h (AARCH64_CORE): Rename IDENT to SCHED.
* config/aarch64/aarch64.h (AARCH64_CORE): Likewise.
* config/aarch64/aarch64.c (AARCH64_CORE): Rename X
On 21 November 2014 at 18:44, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
+2014-11-19 Philipp Tomsich philipp.toms...@theobroma-systems.com
+
+ * config/aarch64/aarch64-cores.def (xgene1): Update/add the
+ xgene1 (APM XGene-1) core definition.
+ *
On 25 November 2014 at 14:03, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/arm_neon.h (__AARCH64_NUM_LANES, __aarch64_lane
*2):
New.
(aarch64_vset_lane_any): Redefine using previous, same for BE + LE.
(vset_lane_f32,
On 5 December 2014 at 11:54, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c
(aarch64_types_binopv_qualifiers,
TYPES_BINOPV): Delete.
(enum aarch64_builtins): Add AARCH64_BUILTIN_SIMD_LANE_CHECK and
On 5 December 2014 at 11:55, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* gcc/config/aarch64-builtins.c (aarch64_simd_expand_args): Update
error
message for SIMD_ARG_CONSTANT.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/arg-type-diagnostics-1.c:
On 5 December 2014 at 11:56, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane):
Delete.
* config/aarch64/aarch64-simd.md
(aarch64_be_checked_get_lanemode\):
Delete.
*
On 5 December 2014 at 11:56, Alan Lawrence alan.lawre...@arm.com wrote:
I tested this by poisoning the old pattern and running check-gcc on both
aarch64-none-elf and aarch64_be-none-elf; there were no regressions even
with the poisoned pattern.
gcc/ChangeLog:
*
On 4 December 2014 at 09:42, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-12-04 Kyrylo Tkachov kyrylo.tkac...@arm.com\
* gcc.target/aarch64/vect_ctz_1.c: Add -fno-vect-cost-model to
dg-options.
OK /Marcus
On 5 December 2014 at 13:14, Christophe Lyon christophe.l...@linaro.org wrote:
2014-12-03 Christophe Lyon christophe.l...@linaro.org
testsuite/
* gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Actually execute
the test. Fix expected output.
*
On 28 November 2014 at 09:23, Yangfei (Felix) felix.y...@huawei.com wrote:
Hi,
This patch converts vpmaxX vpminX intrinsics to use builtin functions
instead of the previous inline assembly syntax.
Regtested with aarch64-linux-gnu on QEMU. Also passed the glorious
testsuite of
On 5 December 2014 at 18:44, Tejas Belagod tejas.bela...@arm.com wrote:
+__extension__ static __inline float32x2_t __attribute__
+((__always_inline__))
+vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c) {
+ return __builtin_aarch64_fmav2sf (-__b, __c, __a); }
+
+__extension__
On 27 November 2014 at 11:27, Renlin Li renlin...@arm.com wrote:
gcc/ChangeLog:
2014-11-27 Renlin Li renlin...@arm.com
* config/aarch64/aarch64.c (aarch64_parse_cpu): Don't define
selected_tune.
(aarch64_override_options): Use selected_cpu's tuning.
OK and this is also broken
On 1 December 2014 at 07:48, Gopalasubramanian, Ganesh
ganesh.gopalasubraman...@amd.com wrote:
Please ignore the previous patch sent. The attachment was wrong.
There's no point in the buffer or the sprintf.
The text is short enough to repeat whole pattern in the array:
Updated the patch for
On 20 November 2014 16:27, Alex Velenko alex.vele...@arm.com wrote:
2014-11-20 Alex Velenko alex.vele...@arm.com
*MAINTAINERS (write-after-approval): Add myself.
Your patch looks fine, commit it. /Marcus
On 21 November 2014 12:11, Alan Hayward alan.hayw...@arm.com wrote:
2014-11-21 Alan Hayward alan.hayw...@arm.com
PR 57233
PR 59810
* config/aarch64/aarch64.c
(aarch64_classify_address): Allow extra addressing modes for BE.
(aarch64_print_operand):
On 17 November 2014 17:35, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-11-17 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/arm_neon.h (vsqrt_f64): New intrinsic.
2014-11-17 Kyrylo Tkachov kyrylo.tkac...@arm.com
* gcc.target/aarch64/simd/vsqrt_f64_1.c
OK /Marcus
On 17 November 2014 11:42, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Makes sense. Here are the changes for the 4.9 and 4.8 changes.html pages.
Ok?
This looks ok to me, I'd suggest changing...
+ li Starting with GCC 4.8.4 a workaround for the ARM Cortex-A53
to
+ li As of GCC 4.8.4
On 14 November 2014 15:46, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (vec_shrmode): New.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_whole_vector_shift): Add aarch64{,_be}.
OK /Marcus
On 17 November 2014 16:56, Alan Lawrence alan.lawre...@arm.com wrote:
This is a pure tidyup, no new functionality. Changes are
(1) Use op[0] to store the result operand, rather than a separate variable,
thus combining the two large switch statements into one;
(2) The 'arg' and 'mode' arrays
On 14 November 2014 16:38, Jiong Wang jiong.w...@arm.com wrote:
gcc/
* config/aarch64/iterators.md (VS): New mode iterator.
(vsi2qi): New mode attribute.
(VSI2QI): Likewise.
* config/aarch64/aarch64-simd-builtins.def: New entry for ctz.
* config/aarch64/aarch64-simd.md (ctzmode2):
On 18 November 2014 12:20, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 18/11/14 10:33, Kyrill Tkachov wrote:
diff --git a/gcc/config/arm/aarch-common-protos.h
b/gcc/config/arm/aarch-common-protos.h
index 264bf01..ad7ec43c 100644
--- a/gcc/config/arm/aarch-common-protos.h
+++
On 18 November 2014 10:33, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-11-18 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c: Include tm-constrs.h
(AARCH64_FUSE_ADRP_ADD): Define.
(cortexa57_tunings): Add AARCH64_FUSE_ADRP_ADD to fuseable_ops.
On 18 November 2014 10:33, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-11-18 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (AARCH64_FUSE_MOVK_MOVK): Define.
(cortexa53_tunings): Specify AARCH64_FUSE_MOVK_MOVK in fuseable_ops.
(cortexa57_tunings):
On 18 November 2014 10:33, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
2014-11-18 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/aarch64/aarch64.c (AARCH64_FUSE_ADRP_LDR): Define.
(cortexa53_tunings): Specify AARCH64_FUSE_ADRP_LDR in fuseable_ops.
(aarch_macro_fusion_pair_p):
On 20 November 2014 14:33, Tejas Belagod tejas.bela...@arm.com wrote:
The same patch applies cleanly to 4.9. OK to commit?
Thanks,
Tejas.
Provided it regresses ok, yes.
/Marcus
On 14 November 2014 16:48, Alan Hayward alan.hayw...@arm.com wrote:
This is a new version of my BE patch from a few weeks ago.
This is part 2 and covers all the aarch64 changes.
When combined with the first patch, It fixes up movoi/ci/xi for Big
Endian, so that we end up with the lab of a
On 13 November 2014 10:09, David Sherwood david.sherw...@arm.com wrote:
gcc/:
2014-11-13 David Sherwood david.sherw...@arm.com
* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist,
aarch64_reverse_mask): New decls.
*
On 19 November 2014 14:32, Wilco Dijkstra wdijk...@arm.com wrote:
Hi Jiong,
Can you commit this please?
2014-11-19 Wilco Dijkstra wdijk...@arm.com
* gcc/config/aarch64/aarch64.c (generic_regmove_cost):
Increase FP move cost (PR61915).
Use the proper format for referring
On 12 November 2014 17:47, Charles Baylis charles.bay...@linaro.org wrote:
On 12 November 2014 15:35, Alan Lawrence alan.lawre...@arm.com wrote:
Nice! One nit - can the extra tree argument be a const_tree ? - I'll
defer to the maintainers on the use of C++ default arguments in the AArch64
On 19 November 2014 16:48, Charles Baylis charles.bay...@linaro.org wrote:
On 19 November 2014 16:42, Alan Lawrence alan.lawre...@arm.com wrote:
Of the calls to aarch64_simd_lane_bounds that remain in aarch64-simd.md:
aarch64_get_lanedi
aarch64_im_lane_boundsi
aarch64_ld{2,3,4}_lanemode
On 19 November 2014 19:05, Charles Baylis charles.bay...@linaro.org wrote:
PR target/63870
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Pass
expression to aarch64_simd_lane_bounds.
* config/aarch64/aarch64-protos.h (aarch64_simd_lane_bounds):
On 17 November 2014 06:58, Yangfei (Felix) felix.y...@huawei.com wrote:
PING?
BTW: It seems that Alan's way of improving vld1(q?)_dup intrinsic is more
elegant.
So is the improvement of vcls(q?) vcnt(q?) OK for trunk? Thanks.
Please rebase over Alan's patch and repost, thank you /Marcus
On 17 November 2014 07:59, Yangfei (Felix) felix.y...@huawei.com wrote:
+2014-11-13 Felix Yang felix.y...@huawei.com
+
+ * config/aarch64/aarch64.md (doloop_end): New pattern.
+
This looks like a straight copy of the ARM code, but without the
TARGET_CAN_USE_DOLOOP_P definition. If the
On 18 November 2014 11:28, Yangfei (Felix) felix.y...@huawei.com wrote:
Yeah, that's a good idea. See my updated patch :-)
Index: gcc/ChangeLog
===
--- gcc/ChangeLog (revision 217394)
+++ gcc/ChangeLog (working
On 17 November 2014 17:33, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add more conditional macros defined ACLE 2.0.
aarch64-none-elf target is tested on the model, no new issues.
Is this Okay for trunk?
gcc/ChangeLog:
2014-11-17 Renlin Li renlin...@arm.com
On 13 November 2014 10:38, Alan Lawrence alan.lawre...@arm.com wrote:
Hi,
gcc/config/aarch64/iterators.md contains numerous duplicates - not always
obvious as they are not always sorted the same. Sometimes, one copy is used
is aarch64-simd-builtins.def and another in aarch64-simd.md;
On 11 November 2014 11:59, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch models the latency of moves between FP and GP registers on the
A15 and A57 a bit more accurately by splitting the reservations for FP-GP
and GP-FP moves and adding an appropriate bypass.
Bootstrapped
On 14 November 2014 14:35, Wilco Dijkstra wdijk...@arm.com wrote:
2014-11-14 Wilco Dijkstra wdijk...@arm.com
* gcc/config/aarch64/aarch64.c (generic_regmove_cost):
Increase FP move cost.
OK /Marcus
On 14 November 2014 15:06, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Considering that the erratum workaround option was backported to 4.9, I
assume we'll need an item for that
in the changes.html for that branch?
The text is the same as in the trunk version that I committed
On 17 November 2014 14:48, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Some configurations of Cortex-A53 and Cortex-A57 don't ship with crypto,
so enabling it by default for -mcpu=cortex-a53 and cortex-a57 is
inappropriate.
Tested aarch64-none-elf. Reminder that at the moment all
On 14 November 2014 10:45, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove.
* config/aarch64/aarch64-simd-builtins.def (create): Remove.
* config/aarch64/aarch64-simd.md (aarch64_createmode): Remove.
On 14 November 2014 10:46, Alan Lawrence alan.lawre...@arm.com wrote:
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_setmode): Add
variant reading from memory and assembling to ld1.
* config/aarch64/arm_neon.h (vld1_lane_f32, vld1_lane_f64,
On 14 November 2014 10:46, Alan Lawrence alan.lawre...@arm.com wrote:
This patch replaces the inline asm for vld1_dup intrinsics with a vdup_n_
and a load from the pointer. The existing *aarch64_simd_ld1rmode insn,
combiner, etc., are quite capable of generating the expected single ld1r
On 14 November 2014 12:01, Christophe Lyon christophe.l...@linaro.org wrote:
On 14 November 2014 12:17, Marcus Shawcroft marcus.shawcr...@gmail.com
wrote:
On 12 November 2014 13:11, Christophe Lyon christophe.l...@linaro.org
wrote:
Hi,
The attached patch adds a few more tests
On 29 October 2014 10:28, Zhenqiang Chen zhenqiang.c...@arm.com wrote:
-Original Message-
From: Richard Henderson [mailto:r...@redhat.com]
Sent: Monday, October 27, 2014 10:56 PM
To: Zhenqiang Chen
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [Ping] [PATCH, 1/10] two hooks for
On 14 November 2014 08:19, Andrew Pinski pins...@gmail.com wrote:
On Fri, Nov 14, 2014 at 12:12 AM, Tejas Belagod tejas.bela...@arm.com wrote:
Hi,
Following the discussion here
https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02237.html, this has been
tracked down to a range-checking bug with
On 12 November 2014 16:46, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
v2 , based on Richard's suggestion as well as fixing a bug that I hit in
some more testing at O1. aarch64_internal_mov_immediate should not generate
a temporary for subtarget when not actually generating code.
On 11 November 2014 23:39, Andrew Pinski pins...@gmail.com wrote:
Hi,
The problem here is that aarch64-builtins.c contains gty markers but
does not include gt-aarch64-builtins.h and is not included in the
target_gtfiles list in config.gcc. So sometimes the builtins get
garbage collected
On 13 November 2014 06:14, Yangfei (Felix) felix.y...@huawei.com wrote:
Hi,
We find that the VALLDI mode iterator used in *aarch64_simd_ld1rmode
pattern is not appropriate.
The reason is that it's impossible to get a new operand of DImode by
vec_duplicating an operand of the same mode.
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