On 11/09/2023 16:22, Jonathan Wakely via Gcc-patches wrote:
> On Mon, 11 Sept 2023 at 14:57, Christophe Lyon
> wrote:
>>
>>
>>
>> On Mon, 11 Sept 2023 at 15:12, Jonathan Wakely wrote:
>>>
>>> On Mon, 11 Sept 2023 at 13:36, Christophe Lyon
>>> wrote:
On Mon, 11 Sept 2023 at
On 23/08/2023 16:49, Richard Sandiford via Gcc-patches wrote:
> Richard Earnshaw via Gcc-patches writes:
>> Now that we require C++ 11, we can safely forward declare rtx_code
>> so that we can use it in target hooks.
>>
>> gcc/ChangeLog
>> * coretypes.h (rtx_code): Add forward declaration.
On 18/08/2023 17:37, FX Coudert via Gcc-patches wrote:
A rather trivial fix for fprintf() specifier of a HOST_WIDE_INT value.
Tested on aarch64-apple-darwin. OK to commit?
FX
OK.
R.
On 08/08/2023 20:39, Carlos O'Donell via Gcc-patches wrote:
On 8/8/23 13:46, David Edelsohn wrote:
I believe that upstream projects for components that are imported
into GCC should be responsible for their security policy, including
libgo, gofrontend, libsanitizer (other than local patches),
On 08/08/2023 15:40, Siddhesh Poyarekar wrote:
On 2023-08-08 10:37, Jakub Jelinek wrote:
On Tue, Aug 08, 2023 at 10:30:10AM -0400, Siddhesh Poyarekar wrote:
Do you have a suggestion for the language to address libgcc, libstdc++,
etc. and libiberty, libbacktrace, etc.?
I'll work on this a bit
On 11/07/2023 15:54, Richard Earnshaw (lists) via Gcc-patches wrote:
On 11/07/2023 10:37, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key):
Add missing const qualifier. Cast from const unsigned char *
to const char
On 11/07/2023 10:37, Florian Weimer via Gcc-patches wrote:
libgcc/
* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key):
Add missing const qualifier. Cast from const unsigned char *
to const char *. Use __builtin_strchr to avoid an implicit
On 28/06/2023 10:26, Christophe Lyon via Gcc-patches wrote:
This tests currently expect a directive containing .fpu fpv5-sp-d16
and thus may fail if the test is executed for instance with
-march=armv8.1-m.main+mve.fp+fp.dp
This patch accepts either fpv5-sp-d16 or fpv5-d16 to avoid the failure.
On 28/06/2023 10:26, Christophe Lyon via Gcc-patches wrote:
If GCC is configured with the default (soft) -mfloat-abi, and we don't
override the target_board test flags appropriately,
gcc.target/arm/mve/general-c/nomve_fp_1.c fails for lack of
-mfloat-abi=softfp or -mfloat-abi=hard, because it
On 01/06/2023 05:26, YunQiang Su wrote:
speculation_barrier for MIPS needs sync+jr.hb (r2+),
so we implement __speculation_barrier in libgcc, like arm32 does.
gcc/ChangeLog:
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
*
On 08/06/2023 11:00, Tamar Christina via Gcc-patches wrote:
Hi All,
This converts some patterns in the AArch64 backend to use the new
compact syntax.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64.md (arches):
On 08/06/2023 11:29, Richard Earnshaw (lists) via Gcc-patches wrote:
On 08/06/2023 11:12, Andreas Schwab wrote:
On Jun 08 2023, Tamar Christina via Gcc-patches wrote:
@@ -713,6 +714,183 @@ you can use @samp{*} inside of a @samp{@@}
multi-alternative template:
@end group
@end smallexample
On 08/06/2023 11:12, Andreas Schwab wrote:
On Jun 08 2023, Tamar Christina via Gcc-patches wrote:
@@ -713,6 +714,183 @@ you can use @samp{*} inside of a @samp{@@}
multi-alternative template:
@end group
@end smallexample
+@node Compact Syntax
+@section Compact Syntax
+@cindex compact
On 06/06/2023 13:49, Richard Sandiford via Gcc-patches wrote:
Tamar Christina writes:
int operand_number; /* Operand index in the big array. */
int output_format; /* INSN_OUTPUT_FORMAT_*. */
+ bool compact_syntax_p;
struct operand_data operand[MAX_MAX_OPERANDS];
On 24/04/2023 09:33, Richard Sandiford via Gcc-patches wrote:
Richard Sandiford writes:
Tamar Christina writes:
Hi All,
This patch adds support for a compact syntax for specifying constraints in
instruction patterns. Credit for the idea goes to Richard Earnshaw.
I am sending up this RFC to
On 13/01/2023 22:12, Jakub Jelinek wrote:
On Fri, Jan 13, 2023 at 09:58:26PM +, Richard Earnshaw (lists) wrote:
> I'm afraid increasing number of DWARF registers is ABI incompatible change.
> E.g. libgcc __frame_state_for function fills in:
> typedef struct frame_state
> {
> void *cfa;
>
On 13/01/2023 18:02, Jakub Jelinek via Gcc-patches wrote:
On Fri, Jan 13, 2023 at 05:44:15PM +, Srinath Parvathaneni via Gcc-patches
wrote:
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register",
Fix a signed vs unsigned comparison in last change.
gcc:
* common/config/arm/arm-common.c (arm_config_default): Change type
of 'i' to unsigned.
---
gcc/common/config/arm/arm-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 03/03/2021 14:11, Christophe Lyon via Gcc-patches wrote:
> On Wed, 3 Mar 2021 at 14:55, Richard Earnshaw (lists)
> wrote:
>>
>> Hopefully this change will reduce the number of times Christophe is
>> needing to tweak the testsuite.
>>
>
> Thanks!
>
> I guess this means we can now do some
Hopefully this change will reduce the number of times Christophe is
needing to tweak the testsuite.
--
Arm processors can support up to two instruction sets. Some early
cores only support the traditional A32 (Arm) instructions, while some
more recent devices only support T32 (Thumb)
Commit r10-6017 relaxed the constraint on thumb2 calls to
__gnu_cmse_nonsecure_call to allow any register for the call address.
Although the initial code expansion continues to use r4 with the FPCXT
extension is not enabled, the change was unsafe because subsequent
optimizations could use the
On 10/02/2021 17:44, Andrea Corallo via Gcc-patches wrote:
> Andrea Corallo via Gcc-patches writes:
>
>> "Richard Earnshaw (lists)" writes:
>>
>>> On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote:
Jakub Jelinek writes:
> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub
On 09/02/2021 16:27, Andrea Corallo via Gcc-patches wrote:
> Jakub Jelinek writes:
>
>> On Tue, Feb 09, 2021 at 03:09:43PM +0100, Jakub Jelinek via Gcc-patches
>> wrote:
"TARGET_32BIT && TARGET_HAVE_LOB"
- "le\t%|lr, %l0")
+ "*
+ if (get_attr_length (insn) == 4)
+
On 26/11/2020 13:53, Andrea Corallo via Gcc-patches wrote:
> Hi all,
>
> I'd like to submit the following simple patch to clean some Low Loop
> Overhead test failing on hard float configurations.
>
> lob2.c and lob5.c are failing with: "'-mfloat-abi=hard': selected
> processor lacks an FPU".
>
arm_split_atomic_op handles subtracting a constant by converting it
into addition of the negated constant. But if the type of the operand
is int and the constant is -1 we currently end up generating invalid
RTL which can lead to an abort later on.
The problem is that in a HOST_WIDE_INT, INT_MIN
On 19/11/2020 14:40, Wilco Dijkstra via Gcc-patches wrote:
> Hi,
>
As for your second patch, --with-cpu-64 could be a simple alias indeed,
but what is the exact definition/expected behaviour of a --with-cpu-32
on a target that only supports 64-bit code? The AArch64
On 18/11/2020 17:16, Pop, Sebastian via Gcc-patches wrote:
> Hi,
>
> On 11/18/20, 10:17 AM, "Wilco Dijkstra" wrote:
>>I presume you're trying to unify the --with- options across most targets?
>
> Yes, my intention was to provide the same configure options on arm64
> as on x86, such that
On 17/11/2020 15:18, Bernd Edlinger wrote:
> On 11/17/20 1:44 PM, Richard Earnshaw (lists) wrote:
>> On 03/11/2020 15:08, Bernd Edlinger wrote:
>>> Hi,
>>>
>>> this fixes a problem with a missing symbol __sync_synchronize
>>> which happens when newlib is used together with libstdc++ for
>>> the
On 03/11/2020 15:08, Bernd Edlinger wrote:
> Hi,
>
> this fixes a problem with a missing symbol __sync_synchronize
> which happens when newlib is used together with libstdc++ for
> the non-threaded simulator target arm-none-eabi.
>
> There are several questions on stackoverflow about this issue.
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