: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
I use ppc gcc to compile following code with option -O2
unsigned long c2l(unsigned char* p)
{
unsigned long res = *p + *(p+1);
return res;
}
long c2sl(signed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764
--- Comment #6 from Carrot carrot at google dot com ---
Another example for ppc.
Following code is disassembled from sha1dgst.o in openssl which is compiled by
gcc
sha1_block_data_order:
...
80: 82 5a 52 3f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63530
--- Comment #7 from Carrot carrot at google dot com ---
(In reply to Ramana Radhakrishnan from comment #6)
Fixed then ?
Yes, thanks for closing it.
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
Currently ppc gcc generates two instructions to compute the address of non
local data. If the data layout is known to compiler, we
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63530
--- Comment #3 from Carrot carrot at google dot com ---
It turns out that when function vect_create_addr_base_for_vector_ref create a
new pointer, it doesn't set the correct alignment of pointer value, so the
default alignment of the point_to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63530
Carrot carrot at google dot com changed:
What|Removed |Added
CC||carrot at google dot
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
In bzip2 there are code segment like:
if (s-state == BZ_X_MAGIC_1) {
/*initialise the save area*/
s-save_i = 0;
s-save_j = 0;
s-save_t
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156
--- Comment #9 from Carrot carrot at google dot com ---
The original flag setting code is neither correct. Consider following
pre_modify expression:
(pre_modify (r1)// def1, use1
(plus (r1) // use2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156
--- Comment #8 from Carrot carrot at google dot com ---
(In reply to Steven Bosscher from comment #7)
(In reply to Carrot from comment #6)
Since it is intentionally to remove flag DF_REF_READ_WRITE on use,
Ah, but I don't think
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156
--- Comment #6 from Carrot carrot at google dot com ---
(In reply to Steven Bosscher from comment #5)
(In reply to Carrot from comment #4)
For a AUTOINC rtl expression, we create two refs, one def and one use, but
only the def gets the flag
-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Check out the latest trunk, apply the following patch to move web before IRA
Index: passes.def
===
--- passes.def(revision 214881
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156
--- Comment #3 from Carrot carrot at google dot com ---
../trunk3/configure '--build=x86_64-build_unknown-linux-gnu'
'--host=x86_64-build_unknown-linux-gnu' '--target=arm-unknown-linux-gnueabi'
'--prefix=/usr/local/google/home/carrot/x-tools/arm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156
--- Comment #4 from Carrot carrot at google dot com ---
In function df_uses_record, we have:
...
case PRE_DEC:
case POST_DEC:
case PRE_INC:
case POST_INC:
case PRE_MODIFY:
case POST_MODIFY:
gcc_assert
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62262
--- Comment #5 from Carrot carrot at google dot com ---
(In reply to amker from comment #2)
(In reply to Andrew Pinski from comment #1)
(insn 27 26 40 5 (set (reg:SI 73 [ D.2590 ])
(and:SI (ashift:SI (reg/v:SI 74 [ value
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: aarch64
Compile following source code with options -fprofile-use -O2
static inline int CLZ(int mask) {
return mask ? __builtin_clz(mask) : 32;
}
int foo(int value)
{
if (value
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
Compile following source code with options -m64 -mcpu=power8 -O2
typedef struct {
int l;
int b[258];
} S;
void clear (S* s )
{
int i;
int
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62040
Carrot carrot at google dot com changed:
What|Removed |Added
CC||carrot at google dot
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62040
--- Comment #6 from Carrot carrot at google dot com ---
Even more simplified test case for gcc4.9, but it doesn't trigger the error for
trunk.
typedef __builtin_aarch64_simd_udi uint64x1
__attribute__ ((__vector_size__ (8)));
typedef
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
Compile following source code with options -m64 -mcpu=power8 -O2
typedef struct {
int l;
int b[258];
} S;
void clear (S* s )
{
int i;
int len = s-l + 1
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: arm-unknown-linux-gnueabi
Compile following source code with options -march=armv7-a -mfpu=vfpv3
-mfloat-abi=softfp -O2 -std=gnu++11
#include limits
#include cmath
const int
: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
Compile following code with options -m64 -mcpu=power8 -O2
extern void free (void *__ptr);
void my_free ( void* p, void* addr )
{
if (addr != ((void *)0)) free
: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Host: x86_64-unknown-linux-gnu
Target: powerpc64le
Compile following code with trunk compiler and options -O2 -m64 -mcpu=power8
void foo(int *p1, char *p2, int s)
{
int
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202
Carrot carrot at google dot com changed:
What|Removed |Added
Status|NEW |RESOLVED
: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le
Compile the following source code with options -m64 -mvsx -mcpu=power8 -O2
typedef unsigned char Bool;
typedef unsigned char UChar;
typedef unsigned int UInt32
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202
--- Comment #3 from Carrot carrot at google dot com ---
4.8 branch also has the same problem.
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: aarch64
Created attachment 32808
-- https://gcc.gnu.org/bugzilla/attachment.cgi?id=32808action=edit
testcase
Attached is reduced preprocessed source code. Compile it with gcc 4.9
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202
--- Comment #1 from Carrot carrot at google dot com ---
In arm_neon.h, we have
__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
vqdmulhq_n_s16 (int16x8_t a, int16_t b)
{
int16x8_t result;
__asm__ (sqdmulh %0.8h
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
Target: powerpc64le-grtev4-linux-gnu
Source code:
extern int* foo1 ( long* );
extern int *foo2 ( long *, long *);
extern void foo3 (long, long);
void bar()
{
long d, f, x, s
-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: carrot at google dot com
This is actually a regression caused by r175916.
Compile the following code with options -O2 -fno-strict-aliasing
-fprofile-generate
struct thread_param
{
long* buf;
long iterations;
long
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56993
--- Comment #3 from Carrot carrot at google dot com ---
I don't have a reduced test case. But I have a reduced config file.
###
ext = Linux64
backup_config = 0
makeflags
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56993
--- Comment #1 from Carrot carrot at google dot com ---
I did some more experimentation on this benchmark.
O0/O1 generates correct result, but O2/Os generates wrong result. So the
problem should be in some optimization pass that is enabled in O2
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56993
Bug #: 56993
Summary: power gcc built 416.gamess generates wrong result
Classification: Unclassified
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55769
Bug #: 55769
Summary: unnecessary spill/reload to compose register pair
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
Severity:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55666
Bug #: 55666
Summary: Use scratch register to avoid save/restore of callee
saved register
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55666
--- Comment #1 from Carrot carrot at google dot com 2012-12-12 19:48:30 UTC
---
Created attachment 28938
-- http://gcc.gnu.org/bugzilla/attachment.cgi?id=28938
testcase
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54574
Bug #: 54574
Summary: G++ accepts parameters with wrong types in parent
constructor
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54398
--- Comment #8 from Carrot carrot at google dot com 2012-09-12 20:57:33 UTC
---
(In reply to comment #7)
This rings a bell.
Maybe the patch mentioned below needs backporting given Carrot is
reporting this against the 4.6 branch. What's
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54398
--- Comment #5 from Carrot carrot at google dot com 2012-09-11 00:10:45 UTC
---
It's the bug in local dse sub step in dse.c.
66 (insn/f 70 69 71 2 (set (reg/f:SI 7 r7)
67 (plus:SI (reg/f:SI 13 sp)
68 (const_int 0 [0
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54398
Carrot carrot at google dot com changed:
What|Removed |Added
CC||carrot at google dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447
Carrot carrot at google dot com changed:
What|Removed |Added
Status|NEW |RESOLVED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447
--- Comment #2 from Carrot carrot at google dot com 2012-05-23 06:54:55 UTC
---
A question about related pattern
626 (define_insn_and_split *arm_adddi3
627 [(set (match_operand:DI 0 s_register_operand =r,r)
628 (plus:DI
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447
Bug #: 53447
Summary: missed optimization of 64bit ALU operation with small
constant
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53241
Bug #: 53241
Summary: Bad pre increment insn for ARM vfp store instructions
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52412
Bug #: 52412
Summary: another unnecessary register move on arm
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52396
Bug #: 52396
Summary: Gcc failed to hoist loop invariant expression out of
loop
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52338
Bug #: 52338
Summary: shorter abs thumb2 code sequences
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52256
Bug #: 52256
Summary: CSE the memory load from both branches of if statement
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52129
Bug #: 52129
Summary: wrong code to pass parameters to tail call function
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: major
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51797
Bug #: 51797
Summary: Arm backend missed the mls related optimization
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51659
--- Comment #2 from Carrot carrot at google dot com 2012-01-05 07:06:22 UTC
---
It can be reproduced with following simple code
struct function
{
int pops_args;
long long x_frame_offset;
};
long long get_func_frame_size (struct function
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51659
Bug #: 51659
Summary: ICE in function output_move_double
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51659
--- Comment #1 from Carrot carrot at google dot com 2011-12-23 02:29:49 UTC
---
(gdb) cont
Continuing.
Breakpoint 2, output_move_double (operands=0x19be680, emit=1 '\001', count=0x0)
at ../../../trunk/gcc/config/arm/arm.c:13933
13933
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51509
Bug #: 51509
Summary: Inefficient neon intrinsic code sequence
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51372
Bug #: 51372
Summary: internal compiler error: in write_builtin_type, at
cp/mangle.c:2204
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51372
Carrot carrot at google dot com changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50150
--- Comment #4 from Carrot carrot at google dot com 2011-09-26 02:16:15 UTC
---
After adding '--with-fpu=neon' '--with-float=softfp' to my configuration, most
of the failure disappeared, but there are still several
gcc
FAIL: gcc.dg/vect/vect-120
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49452
--- Comment #23 from Carrot carrot at google dot com 2011-09-16 06:57:15 UTC
---
(In reply to comment #21)
All callee saved registers should never changed after function call. Here fp
has been changed is not because it is after a function
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49452
Carrot carrot at google dot com changed:
What|Removed |Added
CC||carrot at google dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49452
--- Comment #20 from Carrot carrot at google dot com 2011-09-14 03:02:03 UTC
---
Instruction 2 and 24 refer to the same location, but have different offset
relative to FP because the call to y changes FP. DSE doesn't (and can
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50194
--- Comment #3 from Carrot carrot at google dot com 2011-08-30 01:16:34 UTC
---
Yes, it's a problem of the linker in my testing environment. I've tried to
manually link it with a different linker, it can run successfully. And the
correct stub
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50194
Bug #: 50194
Summary: wrong tail call optimization for mixed arm/thumb mode
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50150
Bug #: 50150
Summary: misc vect.exp failures for target arm
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50150
--- Comment #2 from Carrot carrot at google dot com 2011-08-23 01:14:46 UTC
---
(In reply to comment #1)
So how was this toolchain configured by default ?
Ramana
My configuration is:
configured by /usr/local/google/home/carrot/trunk4
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799
Carrot carrot at google dot com changed:
What|Removed |Added
Status|NEW |RESOLVED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799
Carrot carrot at google dot com changed:
What|Removed |Added
Component|target |rtl-optimization
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799
--- Comment #6 from Carrot carrot at google dot com 2011-07-25 09:25:22 UTC
---
(In reply to comment #5)
We should never generate a shift of -1. Instead the code that does that
should
return (clobber const_int 0).
I'm afraid this method may
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799
--- Comment #8 from Carrot carrot at google dot com 2011-07-26 02:51:39 UTC
---
(In reply to comment #7)
No, you miss the point.
Internally we must not generate (ashift (reg) (const_int)) where the const is
negative.
Note that your
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799
Summary: gcc arm generates illegal sbfx instruction
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49573
Carrot carrot at google dot com changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49573
Summary: wrong rtl pre transformation
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48328
--- Comment #1 from Carrot carrot at google dot com 2011-03-30 07:25:31 UTC
---
Another possible enhancement is we can also use HImode jump table entries.
Similar to cases min0, although tbh is not available in arm mode, we can use
separate
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48328
Summary: GCC failed to generate 16bit relative jump table
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47920
Summary: strange code generated for expression (a+7)/8
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47920
--- Comment #3 from Carrot carrot at google dot com 2011-03-01 06:44:47 UTC
---
(In reply to comment #1)
Presumably because arithmetic right-shift by 3 isn't the same as a division by
8 when (a+7) is negative. Changing the types to unsigned
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855
--- Comment #1 from Carrot carrot at google dot com 2011-02-25 07:18:07 UTC
---
I printed out the address of each instruction from function arm_reorg()
id=173 addr=0
id=2 addr=4
id=3 addr=8
id=15 addr=12
id=18 addr=16
id=199 addr=24
id=21 addr
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855
Summary: missed cbnz optimization
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47831
Summary: avoid if-convertion if the conditional instructions
and following conditional branch has the same
condition
Product: gcc
Version: 4.6.0
Status:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764
--- Comment #3 from Carrot carrot at google dot com 2011-02-21 03:15:45 UTC
---
Any ideas of how this improvement could be implemented, Carrot?
The root cause of this problem is that arm/thumb store instruction can't
directly store a immediate
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=4
Summary: use __aeabi_idivmod to compute quotient and remainder
at the same time
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764
Summary: The constant load instruction should be hoisted out of
loop
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47454
--- Comment #3 from Carrot carrot at google dot com 2011-01-31 08:48:40 UTC
---
(In reply to comment #2)
-frename-registers should help for this issue on the ARM.
All of r8 can be renamed to r2, in this case only two of them have been
renamed.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47454
Summary: registers are not allocated according to its preferred
order
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47373
Summary: avoid goto table to reduce code size when optimized
for size
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47133
Summary: code size opportunity for boolean expression
evaluation
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46975
Summary: Replace 32 bit instructions with 16 bit instructions
in thumb2
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46932
Summary: Inefficient code sequence to access local variable
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46631
Summary: Change operands order so we can use 16bit and instead
of 32bit in thumb2
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46548
Summary: Build arm gcc failure after patch 165463
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46127
Summary: Use 16bit add instead of 32bit in thumb2
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46092
Summary: Improve constant handling of thumb2 instructions
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45980
--- Comment #1 from Carrot carrot at google dot com 2010-10-18 06:24:04 UTC
---
The replacement of constant loading with add operations is occurred at pass
postreload in function reload_cse_move2add. It is straight forward to extend
that to other
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45980
Summary: Use not in stead of add to generate new constant
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45937
Summary: unnecessary push/pop to reserve stack memory
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo:
--- Comment #4 from carrot at google dot com 2010-08-22 04:34 ---
Both have been fixed. But I don't have the permission to close PR43461.(In
reply to comment #3)
Didn't Carrot's r163184 fix this PR and its dupe PR43461?
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44999
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45335
--- Comment #1 from carrot at google dot com 2010-08-20 03:13 ---
By simply define the following pattern
(define_insn *thumb2_ldrd
[(parallel [(set (match_operand:SI 0 s_register_operand )
(mem:SI (match_operand:SI 2 )))
(set (match_operand:SI 1
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45252
: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: middle-end
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http
: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45039
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla
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