On Mon, Apr 19, 2010 at 5:54 PM, Jeff Law l...@redhat.com wrote:
combine requires a data dependency, so for this situation, combine isn't
going to help. The easy solution is to create a peephole. You can also
create a machine dependent reorg pass to detect more of these opportunities.
Frank Isamov frank.isa...@gmail.com writes:
1. Is it possible to add a machine dependent reorg pass at backend
level without changing the standard infrastructure? If so, can you
please point me such example? If no, may the new plugin architecture
help here?
See
On Wed, Apr 21, 2010 at 4:42 PM, Ian Lance Taylor i...@google.com wrote:
2. A peephole for such case just repeats instruction definition
pattern. As all information already available for such peephole,
wouldn’t it be useful to implement the pass to be a part of the
standard infrastructure?
On 04/21/10 00:39, Frank Isamov wrote:
On Mon, Apr 19, 2010 at 5:54 PM, Jeff Lawl...@redhat.com wrote:
combine requires a data dependency, so for this situation, combine isn't
going to help. The easy solution is to create a peephole.You can also
create a machine dependent reorg pass
Hi Ian,
On Wed, Apr 21, 2010 at 5:42 PM, Ian Lance Taylor i...@google.com wrote:
Frank Isamov frank.isa...@gmail.com writes:
2. A peephole for such case just repeats instruction definition
pattern. As all information already available for such peephole,
wouldn’t it be useful to implement
On 04/21/10 11:57, Frank Isamov wrote:
Instructions which manipulate with data in parallel and have no data
dependency automatically require peephole2 definition or/and machine
dependent reorg pass. (Please see an example at the bottom of this
email). Peephole2 pattern, in this case, just
Hi,
My architecture supports instructions with two parallel side effects.
For example, addition and subtraction can be done in parallel:
(define_insn assi6
[(parallel [
(set (match_operand:SI 0 register_operand =r)
(minus:SI (match_operand:SI 1 register_operand r)
On 04/19/10 06:58, Frank Isamov wrote:
Hi,
My architecture supports instructions with two parallel side effects.
For example, addition and subtraction can be done in parallel:
(define_insn assi6
[(parallel [
(set (match_operand:SI 0 register_operand =r)
(minus:SI
