Hi,
I was looking into PR65105 and tried to generate SSE computation for a
simple 64bit a + b + c sequence. Having no scalar integer
instructions in SSE I have to use vector variants.
Original RTL:
(insn 3 2 4 2 (set (reg/v:DI 91 [ b ])
(mem/c:DI (plus:SI (reg/f:SI 16 argp)
(const_int 8 [0x8])) [1 b+0 S8 A32])) test.c:3 89
{*movdi_internal}
(nil))
(insn 8 5 9 2 (parallel [
(set (reg:DI 94 [ D.1813 ])
(plus:DI (mem/c:DI (reg/f:SI 16 argp) [1 a+0 S8 A32])
(reg/v:DI 91 [ b ])))
(clobber (reg:CC 17 flags))
]) test.c:4 215 {*adddi3_doubleword}
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_DEAD (reg/v:DI 91 [ b ])
(nil))))
(insn 9 8 14 2 (parallel [
(set (reg:DI 93 [ D.1813 ])
(plus:DI (reg:DI 94 [ D.1813 ])
(mem/c:DI (plus:SI (reg/f:SI 16 argp)
(const_int 16 [0x10])) [1 c+0 S8 A32])))
(clobber (reg:CC 17 flags))
]) test.c:4 215 {*adddi3_doubleword}
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_DEAD (reg:DI 94 [ D.1813 ])
(nil))))
Transformed RTL:
(insn 3 2 4 2 (set (reg:V1DI 91)
(mem/c:V1DI (plus:SI (reg/f:SI 16 argp)
(const_int 8 [0x8])) [1 b+0 S8 A32])) test.c:3 1077
{*movv1di_internal}
(nil))
(insn 17 5 8 2 (set (reg:V1DI 95)
(mem/c:V1DI (reg/f:SI 16 argp) [1 a+0 S8 A32])) test.c:4 -1
(nil))
(insn 8 17 24 2 (set (reg:V2DI 94 [ D.1813 ])
(plus:V2DI (reg:V2DI 95)
(reg/v:V2DI 91 [ b ]))) test.c:4 2949 {*addv2di3}
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_DEAD (reg/v:V2DI 91 [ b ])
(nil))))
(insn 24 8 9 2 (set (reg:V1DI 100)
(mem/c:V1DI (plus:SI (reg/f:SI 16 argp)
(const_int 16 [0x10])) [1 c+0 S8 A32])) test.c:4 -1
(nil))
(insn 9 24 18 2 (set (reg:V2DI 93 [ D.1813 ])
(plus:V2DI (reg:V2DI 94 [ D.1813 ])
(reg:V2DI 100))) test.c:4 2949 {*addv2di3}
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_DEAD (reg:V2DI 94 [ D.1813 ])
(nil))))
The problem is that all loads are removed as dead code during subreg pass:
DCE: Deleting insn 24
deleting insn with uid = 24.
DCE: Deleting insn 17
deleting insn with uid = 17.
DCE: Deleting insn 3
deleting insn with uid = 3.
Is there a way to handle it without adding fake addv1di instruction
for MMX registers?
Thanks,
Ilya
