Hello all,
The target that i am working on is 16bit, big endian and with 16 registers.
It has this particular addressing mode
load Rd, Ra[offset]
store Rs, Ra[offset]
where the offset should be positive, base register Ra should be an
even register and for the source or the destination register
On Tue, Apr 1, 2008 at 2:10 AM, Jim Wilson [EMAIL PROTECTED] wrote:
Mohamed Shafi wrote:
For the source or the destination register Rd/Ra, the restriction is
that it should be one more than the base register . So the following
instructions are valid:
GCC doesn't provide any easy way for the
Mohamed Shafi wrote:
For the source or the destination register Rd/Ra, the restriction is
that it should be one more than the base register . So the following
instructions are valid:
GCC doesn't provide any easy way for the source address to depend on the
destination address, or vice versa.
On Tue, Apr 1, 2008 at 2:10 AM, Jim Wilson [EMAIL PROTECTED] wrote:
Mohamed Shafi wrote:
For the source or the destination register Rd/Ra, the restriction is
that it should be one more than the base register . So the following
instructions are valid:
GCC doesn't provide any easy way
On Tue, 2008-04-01 at 09:48 +0530, Mohamed Shafi wrote:
What i did was to have 8 register class with each class having two
registers, an even register and an odd register then in define expand
look for the register indirect with offset addressing mode and emit
gen_store_offset or
Hello all,
For a port that i am working on has this particular addressing mode
load Rd, Ra[offset]
store Rs, Ra[offset]
For the above two instructions base register Ra should be an even
register. This i have implemented using the macros REGNO_OK_FOR_BASE_P
and BASE_REG_CLASS by creating a class
