On 05/19/11 01:32, Richard Sandiford wrote:
> Paul Koning writes:
>> It looks like the machinery that picks MIPS branch-likely instructions
>> (on processors that don't object to them) is driven purely by their
>> delay slot annul properties and not at all by branch probability.
>
> Unfortunately
On 05/19/11 13:01, Paul Koning wrote:
>
> On May 19, 2011, at 6:41 AM, Paul Koning wrote:
>
>>
>> On May 19, 2011, at 3:32 AM, Richard Sandiford wrote:
>>
>>> Paul Koning writes:
...
>>>
2. In the delay slot fill machinery (reorg.c), I don't see how a
target can supply hooks to ad
On May 19, 2011, at 6:41 AM, Paul Koning wrote:
>
> On May 19, 2011, at 3:32 AM, Richard Sandiford wrote:
>
>> Paul Koning writes:
>>> ...
>>
>>> 2. In the delay slot fill machinery (reorg.c), I don't see how a
>>> target can supply hooks to adjust the picking of one branch over
>>> another.
On May 19, 2011, at 3:32 AM, Richard Sandiford wrote:
> Paul Koning writes:
>> ...
>
>> 2. In the delay slot fill machinery (reorg.c), I don't see how a
>> target can supply hooks to adjust the picking of one branch over
>> another. In other words, if the architecture has branch-likely that
>>
Paul Koning writes:
> It looks like the machinery that picks MIPS branch-likely instructions
> (on processors that don't object to them) is driven purely by their
> delay slot annul properties and not at all by branch probability.
Unfortunately, reorg.c is very old code that is effectively in dee
It looks like the machinery that picks MIPS branch-likely instructions (on
processors that don't object to them) is driven purely by their delay slot
annul properties and not at all by branch probability.
That brings up a couple of questions.
1. Assuming it doesn't matter to the delay slot fill
