The reasoning here is
that if splitting will result in worse code, then we shouldn't have
accepted it in the first place. If dropping this alternative results in
register allocator failures for some strange reason, then we accept it
and generate the 3 instruction sequence with a new
On Thu, 2010-03-18 at 19:20 +0800, Amker.Cheng wrote:
Does it possible that the method would ever result in register
allocator failure?
In my understanding, doesn't reload pass would do whatever it can to make
all insns' constraints satisfied?
In theory, there should be no failure. In
On Tue, 2010-03-16 at 15:12 +0800, Amker.Cheng wrote:
In my understanding, the macro GENERATE_MADD_MSUB is true when the processor
has
madd insn, rather than madd2. And the macro ISA_HAS_DMUL3 is false if it
has
no mul insn.
for this kind processor, gcc will
step 1 : generate insn using
If you don't know anything about register class preferencing or reload as
yet, then this is probably not going to make much sense to you, but it isn't
anything important you need to worry about at this point. It is a very
minor performance optimization.
It makes sense to me now, though I
Hi :
I am studying multiplication-accumulate patterns for mips
and noticed there are some changes when IRA was merged.
There are two pattern which confused me, as :
1: In pattern *mul_acc_si, there's constraint like *?*?.
what does this supposed to do?
I could not connect *? with document
On 03/15/2010 01:00 AM, Amker.Cheng wrote:
1: In pattern *mul_acc_si, there's constraint like *?*?.
what does this supposed to do?
'*' is in the Constraint Modifier Characters section of the docs. It
means ignore the next character for register class preferencing. '?' is
in the Multiple
