Joey,
My understanding was that the latency is used to figure out data
delays and the reservation to figure out reservation delays and that
these two are used independently. The post below seems to confirm
this,
http://gcc.gnu.org/ml/gcc/2006-08/msg00497.html
I have latency 1 because there are
On 8/31/07, Adam Nemet [EMAIL PROTECTED] wrote:
Matt Lee [EMAIL PROTECTED] writes:
I am seeing poor scheduling in Dhrystone where a memcpy call is
expanded inline.
memcpy (dst, src, 16) ==
load 1, rA + 4
store 1, rB + 4
load 2, rA + 8
store 2, rB + 8
...
Are you sure that
Matt Lee writes:
In any case, I am trying to optimize the case where there is clearly no
aliasing. Your suggestion regarding movmemsi is interesting. I have not used
this pattern before and assumed that it was required only when something
special must be done to do block moves. In my
Matt,
I just started working on pipeline description and I'm confused one thing in
your description.
For integer, your cpu have a 1-cycle latency, but with 3 units stages
issue,iu,wb. What does that mean? My understanding is that the number of
units seperated by , should be equal to latency.
Matt Lee wrote:
Hi,
I am working with GCC-4.1.1 on a simple 5-pipe stage simple scalar
RISC processors with the following description for loads and stores,
(define_insn_reservation integer 1
(eq_attr type branch,jump,call,arith,darith,icmp,nop)
issue,iu,wb)
(define_insn_reservation load 3
Matt Lee [EMAIL PROTECTED] writes:
I am seeing poor scheduling in Dhrystone where a memcpy call is
expanded inline.
memcpy (dst, src, 16) ==
load 1, rA + 4
store 1, rB + 4
load 2, rA + 8
store 2, rB + 8
...
Are you sure that there are no dependencies due to aliasing here. The
only
