Re: Redundant loads for bitfield accesses

When implementing the RISC-V port, I took the name of this macro at face value. It does seem that we should follow Andrew's advice and set it to 1. (For your examples, doing so does improve code generation.) We'll submit a patch if the change doesn't regress. On Wed, Aug 16, 2017 at 4:00 PM,

Re: Redundant loads for bitfield accesses

> On 17 Aug 2017, at 10:41 AM, Andrew Pinski wrote: > > On Wed, Aug 16, 2017 at 3:29 PM, Michael Clark wrote: >> Hi, >> >> Is there any reason for 3 loads being issued for these bitfield accesses, >> given two of the loads are bytes, and one is a

Re: Redundant loads for bitfield accesses

On Wed, Aug 16, 2017 at 3:29 PM, Michael Clark wrote: > Hi, > > Is there any reason for 3 loads being issued for these bitfield accesses, > given two of the loads are bytes, and one is a half; the compiler appears to > know the structure is aligned at a half word

Re: Redundant loads for bitfield accesses

Here’s a more extreme example: - https://cx.rv8.io/g/2HWQje The bitfield type is unsigned int, so one or two 32-bit loads should suffice (depending on register pressure). GCC is issuing a lw at some point in the asm. struct foo { unsigned int a : 3; unsigned int b : 3; unsigned int c :

Redundant loads for bitfield accesses

Hi, Is there any reason for 3 loads being issued for these bitfield accesses, given two of the loads are bytes, and one is a half; the compiler appears to know the structure is aligned at a half word boundary. Secondly, the riscv code is using a mixture of 32-bit and 64-bit adds and shifts.