Re: [RFC] fix bootstrap on aarch64-*-freebsd and probably others

On 19.01.17 00:33, Jeff Law wrote: On 01/18/2017 11:43 AM, Andreas Tobler wrote: Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void

Re: [PATCH] Introduce --with-gcc-major-version-only configure option

Just one suggestion: What about configure option like --with-version-convert where one could specify actual conversion? I have used conversion sed -e 's:\.::2g' for DJGPP to leave only the first dot in version for complying with MS-DOS file name restrictions. The implementation of that was

[Bug target/77346] [7 Regression] ICE in push_reload, at reload.c:1350

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77346 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|2016-11-11

[Bug target/79144] New: cmpstrsi optimization breaks glibc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79144 Bug ID: 79144 Summary: cmpstrsi optimization breaks glibc Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[RFC][PATCH][PR 67336][PING] Verify pointers during stack unwind

Hi all, Libgcc unwinder currently does not do any verification of pointers which it chases on stack. In practice this not so rarely causes segfaults when unwinding on corrupted stacks (e.g. when when trying to print diagnostic on fatal error) [1]. Ironically this usually happens in error

[Bug c++/79139] warning: argument 1 null where non-null expected [-Wnonnull]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79139 Martin Sebor changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug c++/79143] New: [7 Regression][new inheriting constructors] inheriting constructor fails with brace initialization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79143 Bug ID: 79143 Summary: [7 Regression][new inheriting constructors] inheriting constructor fails with brace initialization Product: gcc Version: 7.0 Status: UNCONFIRMED

[Bug rtl-optimization/77499] [7 Regression] Regression after code-hoisting, due to combine pass failing to evaluate known value range

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77499 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug rtl-optimization/78559] [7 Regression] wrong code due to tree if-conversion?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78559 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P1 CC|

[Bug rtl-optimization/78634] [7 Regression] 30% performance drop after r242832.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78634 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug target/78972] [5/6/7 Regression] poor x86 simd instruction scheduling

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78972 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug c++/79095] [7 regression] spurious stringop-overflow warning

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79095 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug rtl-optimization/79125] [7 Regression] ICE in rtl_verify_bb_insns, at cfgrtl.c:2661 (error: flow control insn inside a basic block)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79125 Jeffrey A. Law changed: What|Removed |Added CC||bernds at redhat dot com --- Comment

[Bug rtl-optimization/79125] [7 Regression] ICE in rtl_verify_bb_insns, at cfgrtl.c:2661 (error: flow control insn inside a basic block)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79125 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 Status|UNCONFIRMED

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #22 from Peter Bergner --- Author: bergner Date: Thu Jan 19 02:23:35 2017 New Revision: 244609 URL: https://gcc.gnu.org/viewcvs?rev=244609=gcc=rev Log: PR target/78516 * config/rs6000/spe.md (mov_si_e500_subreg0):

Re: [PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

On 1/18/17 8:04 PM, Segher Boessenkool wrote: On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote: Is this ok for trunk? This looks good, please apply. Thanks, Thanks, committed as revision 244609. Peter

[Bug target/79131] [7 Regression] ICE: in extract_constrain_insn, at recog.c:2213, big-endian ARM

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79131 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 Status|UNCONFIRMED

[Bug target/79140] gcc.target/powerpc/ssp-1.c fails starting with its introduction in r244562

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79140 Segher Boessenkool changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

Re: [PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

On Wed, Jan 18, 2017 at 02:38:30PM -0600, Peter Bergner wrote: > This is a partial patch for PR78516. This patch fixes some broken constraints > in spe.md that were exposed by the rs6000 port's switch to using LRA. > In order to change some of the constraints to outputs from inout, I had > to

Re: [PATCH, GCC/x86 mingw32] Add configure option to force wildcard behavior on Windows

On 01/18/2017 09:48 AM, Thomas Preudhomme wrote: > By default, wildcard support on Windows for programs compiled with mingw > depends on how the mingw runtime was configured. This means if one wants > to build GCC for Windows with a consistent behavior with Wildcard > (enabled or disabled) the

[PATCH], PowerPC ISA 3.0 defaults + IEEE 128-bit floating point test

This patch changes the default options enabled for the PowerPC -mcpu=power9 option to include the undocumented -mpower9-minmax option. This option enables MIN/MAX instructions that do not require -ffast-math or -fhonor-nans. I also changed the minimum option requirements for IEEE 128-bit

[Bug c/79142] bit shift + compare returns wrong value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79142 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug c/79142] bit shift + compare returns wrong value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79142 --- Comment #1 from layer at known dot net --- And the code: #include /* whatever the shift in badexample does, * the function should never return 1 */ long badexample(unsigned long iv) { long ov = ((long)(1)) << ((iv & 0x3f) + 1); if

[Bug c/79142] New: bit shift + compare returns wrong value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79142 Bug ID: 79142 Summary: bit shift + compare returns wrong value Product: gcc Version: 6.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c

[Bug target/79039] builtins-3-p9.c fails with -m32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79039 Carl Love changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [PATCH, rs6000] Update some Power9 latencies

On Wed, Jan 18, 2017 at 12:34:00PM -0600, Pat Haugen wrote: > The following patch updates a few latencies in the Power9 machine > description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for > trunk? Okay, thanks! Segher > 2017-01-18 Pat Haugen > >

Re: [RFC] fix bootstrap on aarch64-*-freebsd and probably others

On 01/18/2017 11:43 AM, Andreas Tobler wrote: Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void aarch64_elf_asm_destructor(rtx, int)':

Re: RISC-V port accepted for inclusion in GCC

Thank you, David, and the rest of the Steering Committee, for welcoming us into the GCC community. I look forward to working together. On Wed, Jan 18, 2017 at 7:50 AM, David Edelsohn wrote: > I am pleased to announce that the GCC Steering Committee has > accepted the

Re: [PATCH, MIPS] Target flag and build option to disable indexed memory OPs.

On 01/17/2017 05:41 AM, Moore, Catherine wrote: > > >> -Original Message- >> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com] >> Sent: Tuesday, January 17, 2017 4:35 AM >> ... >> Thanks for the comments. >> >> Having thought further I agree we can safely ignore DSP indexed load

[Bug libgomp/55691] Setting OMP_NESTED increases the runtime dramatically for GCC compiled executable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55691 Geir Johansen changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/78478] Compile Error for i386-rtems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78478 --- Comment #16 from Joel Sherrill --- Thanks for all the feedback. With this patch, it now builds. Is the style of change to configure.host OK? I need to check how far back this impacts. A user reported it with a released gcc. Since we don't

[PATCH, rs6000, committed] Fix "type" attribute for vbpermq instruction

Hi, Pat Haugen pointed out that the vbpermq instruction should preferably have its "type" attribute set to vecperm, rather than vecsimple. This patch makes that change. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions, committed as obvious. Thanks, Bill 2017-01-18

[Bug target/79040] vec_cntlz redefined

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79040 Bill Schmidt changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/79127] [7 Regression] Error: invalid register for .seh_savexmm in matmul_i4.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79127 --- Comment #12 from Jakub Jelinek --- On x86_64-linux and i686-linux it passed bootstrap/regtest and still defines HAVE_AVX512F, which is desirable there.

[PATCH, rs6000, committed] Fix PR79040 (built-in typo)

Hi, A previous patch mistakenly added a #define of vec_cntlz which should have been a #define of vec_cnttz. This patch fixes that. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions, committed as obvious. Thanks, Bill 2017-01-18 Bill Schmidt

[Bug target/79040] vec_cntlz redefined

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79040 --- Comment #4 from Bill Schmidt --- Author: wschmidt Date: Wed Jan 18 22:29:22 2017 New Revision: 244602 URL: https://gcc.gnu.org/viewcvs?rev=244602=gcc=rev Log: 2017-01-18 Bill Schmidt PR target/79040

Re: GCC libatomic ABI specification draft

On 01/17/2017 09:00 AM, Torvald Riegel wrote: I think the ABI should set a baseline for each architecture, and the baseline decides whether something is inlinable or not. Thus, the x86_64 ABI would make __int128 operations not imlinable (because of the issues with cmpxchg16b, see above). If

Re: [PATCH] Fix IPA CP where it forgot to add a reference in cgraph

> > 2016-12-19 Martin Liska > > * cgraphclones.c (cgraph_node::create_virtual_clone): > Create either IPA_REF_LOAD of IPA_REF_READ depending on > whether new_tree is a VAR_DECL or an ADDR_EXPR. > * ipa-cp.c (create_specialized_node): Add reference just

[Bug libstdc++/79141] New: std::pair<int,int> p = {}; fails to compile due to ambiguous overload

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79141 Bug ID: 79141 Summary: std::pair p = {}; fails to compile due to ambiguous overload Product: gcc Version: 6.3.1 Status: UNCONFIRMED Severity: normal

[Bug target/58452] GCC 4.8 and trunk do not compile simple powerpc-linuxpaired -O3 case

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58452 Michael Meissner changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48 PM, Uros Bizjak wrote: > Hello! > >> This fix follows the same approach that glibc uses to disable TSX on >> processors on which it is broken. TSX can also be disabled through a >> microcode update on these processors, but glibc consensus is that

[Bug target/69738] PowerPC built-in __builtin_addg6s should be enabled on 64-bit

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69738 Michael Meissner changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [PATCH] Allow building GCC with PTX offloading even without CUDA being installed (gcc and nvptx-tools patches)

On Wed, Jan 18, 2017 at 10:52:32PM +0300, Alexander Monakov wrote: > Sorry for not noticing this earlier, but ... > > > +#ifdef __LP64__ > > +typedef unsigned long long CUdeviceptr; > > +#else > > +typedef unsigned CUdeviceptr; > > +#endif > > I think this #ifdef doesn't do the right thing on

[Bug target/79140] New: gcc.target/powerpc/ssp-1.c fails starting with its introduction in r244562

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79140 Bug ID: 79140 Summary: gcc.target/powerpc/ssp-1.c fails starting with its introduction in r244562 Product: gcc Version: 7.0 Status: UNCONFIRMED Severity:

[Bug c++/79139] New: warning: argument 1 null where non-null expected [-Wnonnull]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79139 Bug ID: 79139 Summary: warning: argument 1 null where non-null expected [-Wnonnull] Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: normal

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48:28PM +0100, Uros Bizjak wrote: > Hello! > > > This fix follows the same approach that glibc uses to disable TSX on > > processors on which it is broken. TSX can also be disabled through a > > microcode update on these processors, but glibc consensus is that it > >

[Bug rtl-optimization/55598] LRA on powerpc does not like assembler in libgcc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55598 Michael Meissner changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug fortran/55086] ICE with FORALL in allocate_temp_for_forall_nest_1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55086 lkrupp at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED CC|

[PATCH] C++: fix fix-it hints for misspellings within explicit namespaces (v2)

On Sat, 2017-01-14 at 09:50 -0500, Jason Merrill wrote: > On Fri, Jan 13, 2017 at 5:05 PM, David Malcolm > wrote: > > On Wed, 2017-01-04 at 14:58 -0500, Jason Merrill wrote: > > > On Tue, Jan 3, 2017 at 8:28 PM, David Malcolm < > > > dmalc...@redhat.com> > > > wrote: > > > >

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

On Wed, Jan 18, 2017 at 10:48 PM, Uros Bizjak wrote: > Hello! > >> This fix follows the same approach that glibc uses to disable TSX on >> processors on which it is broken. TSX can also be disabled through a >> microcode update on these processors, but glibc consensus is that

[Bug fortran/50069] FORALL fails on a character array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50069 lkrupp at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

Re: [PATCH] [ARC] Clean up arc header file.

On 18/01/2017 18:43, Andrew Burgess wrote: * Mike Stump [2017-01-17 10:49:30 -0800]: On Jan 17, 2017, at 3:30 AM, Andrew Burgess wrote: This patch revamps the arc's header file by means of using separate headers for different tool

[Bug go/79037] gccgo: Binaries crash with parforsetup: pos is not aligned on m68k

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79037 --- Comment #5 from Michael Karcher --- The root issue now is that the ABI gcc implements on m68k is incompatible with the Go runtime shipped with gcc. The Go runtime uses the lowest two bits in the type information pointer as flags (called

Re: [committed] libitm: Disable TSX on processors on which it may be broken.

Hello! > This fix follows the same approach that glibc uses to disable TSX on > processors on which it is broken. TSX can also be disabled through a > microcode update on these processors, but glibc consensus is that it > cannot be detected reliably whether the microcode update has been >

Fortran, committed: Forall-with-temporary problems(pr 50069 and pr 55086).

Fixed in revision 244601.

[Bug target/79131] [7 Regression] ICE: in extract_constrain_insn, at recog.c:2213, big-endian ARM

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79131 --- Comment #1 from Vladimir Makarov --- This is a bug in LRA now. LRA should have reloaded the destination or the operand as they conflicts in insn 31 (the destination is an early clobbered operand). IRA does not take early clobbers into

Re: [PATCH] Add AVX512 k-mask intrinsics

On Wed, Jan 18, 2017 at 1:45 PM, Andrew Senkevich wrote: > 2017-01-17 16:51 GMT+03:00 Jakub Jelinek : >> On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote: >>> > I've played a bit w/ SDE. And looks like operands are not early clobber:

[Bug fortran/50069] FORALL fails on a character array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50069 --- Comment #12 from lkrupp at gcc dot gnu.org --- Author: lkrupp Date: Wed Jan 18 21:41:48 2017 New Revision: 244601 URL: https://gcc.gnu.org/viewcvs?rev=244601=gcc=rev Log: 2017-01-18 Louis Krupp PR

[Bug fortran/55086] ICE with FORALL in allocate_temp_for_forall_nest_1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55086 --- Comment #2 from lkrupp at gcc dot gnu.org --- Author: lkrupp Date: Wed Jan 18 21:41:48 2017 New Revision: 244601 URL: https://gcc.gnu.org/viewcvs?rev=244601=gcc=rev Log: 2017-01-18 Louis Krupp PR

[committed] Implement LANG_HOOKS_TYPE_FOR_SIZE for jit

The jit testcase test-nested-loops.c was crashing. Root cause is that deep inside loop optimization we're now exposing this call within fold-const.c which wasn't being hit before: 4082 /* Compute the mask to access the bitfield. */ 4083 unsigned_type = lang_hooks.types.type_for_size

Re: [expand] Fix for PR rtl-optimization/79121 incorrect expansion of extend plus left shift

On 01/18/2017 11:08 AM, Richard Earnshaw (lists) wrote: PR 79121 is a silent wrong code regression where, when generating a shift from an extended value moving from one to two machine registers, the type of the right shift is for the most significant word should be determined by the signedness

[Bug c++/79138] New: ICE when trying to do template auto

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79138 Bug ID: 79138 Summary: ICE when trying to do template auto Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c++

[Bug c++/68666] [concepts] "is not a function template" using class-scoped variable template in constraint expression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68666 Jason Merrill changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug c++/68666] [concepts] "is not a function template" using class-scoped variable template in constraint expression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68666 --- Comment #2 from Jason Merrill --- Author: jason Date: Wed Jan 18 21:05:12 2017 New Revision: 244599 URL: https://gcc.gnu.org/viewcvs?rev=244599=gcc=rev Log: PR c++/68666 - member variable template-id * typeck.c

C++ PATCH for c++/68666 (member variable template)

The problem was that finish_class_member_access_expr got missed when we added variable templates. 68666 is a report of how this affects concepts; the patch adds both concepts and non-concepts testcases. Tested x86_64-pc-linux-gnu, applying to trunk. commit

[Bug target/61729] FAIL: g++.dg/abi/scoped1.C -std=gnu++11 execution test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61729 Segher Boessenkool changed: What|Removed |Added Status|NEW |ASSIGNED

[committed] jit.dg: fix issue with compilation of test-threads.c

DejaGnu's provides decls of various inline functions, of which the jit testsuite uses "pass", "fail" and "note". The jit testcase test-threads.c jumps through some hoops to make these functions threadsafe, using macros to rename the implementation in dejagnu.h, giving them a "dejagnu_" prefix,

[Bug c++/68666] [concepts] "is not a function template" using class-scoped variable template in constraint expression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68666 Jason Merrill changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[PATCH, rs6000] Fix PR78516, broken spe.md constraints exposed by LRA.

This is a partial patch for PR78516. This patch fixes some broken constraints in spe.md that were exposed by the rs6000 port's switch to using LRA. In order to change some of the constraints to outputs from inout, I had to change some of the instructions we emit to equivalent forms. Joseph has

[committed] libitm: Disable TSX on processors on which it may be broken.

This fix follows the same approach that glibc uses to disable TSX on processors on which it is broken. TSX can also be disabled through a microcode update on these processors, but glibc consensus is that it cannot be detected reliably whether the microcode update has been applied. Thus, we just

[Bug testsuite/79109] FAIL: gcc.dg/attr-alloc_size-4.c (test for excess errors)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79109 Martin Sebor changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug testsuite/79051] FAIL: gcc.dg/attr-alloc_size-4.c (test for warnings, line 140)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79051 Martin Sebor changed: What|Removed |Added CC||danglin at gcc dot gnu.org --- Comment

[Bug target/78478] Compile Error for i386-rtems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78478 --- Comment #15 from Uroš Bizjak --- (In reply to Joel Sherrill from comment #14) > (In reply to H.J. Lu from comment #13) > > The problem is config/i386/rtemself.h has > > > > #define LONG_DOUBLE_TYPE_SIZE (TARGET_80387 ? 80 : 64) > > > >

Re: [PATCH] Allow building GCC with PTX offloading even without CUDA being installed (gcc and nvptx-tools patches)

Hello Jakub, Sorry for not noticing this earlier, but ... > +#ifdef __LP64__ > +typedef unsigned long long CUdeviceptr; > +#else > +typedef unsigned CUdeviceptr; > +#endif I think this #ifdef doesn't do the right thing on MinGW. Would it be fine to simplify it? In my code I have typedef

[Bug libstdc++/70530] [DR2468] You should probably add addressof (a) != addressof (b) check to std::swap

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70530 --- Comment #4 from Askar Safin --- DR 2468 says that after "a = std::move (a)" state of a is unspecified. So three-move self-swap will be unspecified, too. You just said, that self-swap is not undefined, i. e. it is defined. Okey, so to make it

[Bug target/79137] Improve powerpc vector permutes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79137 --- Comment #1 from Bill Schmidt --- vec_perm_const is one of the standard pattern names, that gets expanded from a middle-end vector permute.

[PATCH, i386]: (Partially) fix PR78952, Combine does not convert 8-bit sign-extract to a zero-extract

As suggested by Segher, we have to use code iterator to iterate RTX pattern through zero- and sign-extract for 8 bit inserts. In a similar way, we can use any_shiftrt in a RTX pattern involving 8-bit inserts. While it would be nice to have a middle-end perform relevant simplifications, these two

[Bug c++/78488] [7 Regression] P0136R1 ICE when building call to inherited default constructor.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78488 Nathan Sidwell changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[PATCH] fix 78488, ICE with inherited ctor

This patch fixes an ICE with inherited default ctor and a local decl. In such a case we don't have any conv args (just the object expression, handled differently). Thus 'num_convs-1' is -1 and we seg fault at: cand->convs[cand->num_convs-1]->ellipsis_p do just check it's non-zero first.

[Bug c++/78488] [7 Regression] P0136R1 ICE when building call to inherited default constructor.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78488 --- Comment #6 from Nathan Sidwell --- Author: nathan Date: Wed Jan 18 19:27:52 2017 New Revision: 244592 URL: https://gcc.gnu.org/viewcvs?rev=244592=gcc=rev Log: PR c++/78488 * call.c (build_over_call): When checking ellipsis

[Bug rtl-optimization/78952] Combine does not convert 8-bit sign-extract to a zero-extract for QImode operations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78952 --- Comment #4 from uros at gcc dot gnu.org --- Author: uros Date: Wed Jan 18 19:24:30 2017 New Revision: 244591 URL: https://gcc.gnu.org/viewcvs?rev=244591=gcc=rev Log: PR rtl-optimization/78952 * config/i386/i386.md

Re: transaction_safe exceptions prevent libstdc++ building for some targets

Joe Seymour writes: >> the msp430 -mlarge multilib failing to build with... >>> configure: error: Unknown underlying type for size_t >>> make[1]: *** [configure-target-libstdc++-v3] Error 1 > > This is still reproducible. FYI the underlying type is uint20_t I think I've

[Bug target/79137] New: Improve powerpc vector permutes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79137 Bug ID: 79137 Summary: Improve powerpc vector permutes Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: enhancement Priority: P3 Component: target

[Bug go/79037] gccgo: Binaries crash with parforsetup: pos is not aligned on m68k

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79037 --- Comment #4 from John Paul Adrian Glaubitz --- Disabling the Go garbage collector fixes this particular crash: (sid-m68k-sbuild)root@jessie64:~# GOGC=off ./hello-world Hello World! (sid-m68k-sbuild)root@jessie64:~# So it seems GOGC is not

Re: transaction_safe exceptions prevent libstdc++ building for some targets

On 17/08/2016 12:19, Joe Seymour wrote: > fail to build with... > >> ../../../../../libstdc++-v3/src/c++11/cow-stdexcept.cc:274:3: error: static >> assertion failed: Pointers must be 32 bits or 64 bits wide >> static_assert(sizeof(uint64_t) == sizeof(void*) > > The assert fails because msp430

Re: [PATCH], Add support for PowerPC ISA 3.0 vector byte reverse instructions

On Wed, Jan 18, 2017 at 11:21:40AM -0600, Segher Boessenkool wrote: > On Tue, Jan 17, 2017 at 08:50:08PM -0500, Michael Meissner wrote: > > I have checked this on a little endian power8 system (64-bit only), a big > > endian power8 system (64-bit only), and a big endian power7 system (both > >

Re: [PATCH, Fortran, sync_alloc, v1] [Coarray] Do not add sync all call when allocating allocatable/pointer component

Hi Jerry, and also for this many thanks. Committed as r244590. Regards, Andre PS: Hopefully this mail is not declared SPAM by the mail-host like the last one. On Wed, 18 Jan 2017 10:13:10 -0800 Jerry DeLisle wrote: > On 01/18/2017 08:54 AM, Andre Vehreschild

[Bug bootstrap/79132] False positive for -Walloc-size-larger-than= with -fsanitize=address aka. bootstrap-asan breakage

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79132 Martin Sebor changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug libstdc++/79136] New: read outside of buffer in char* std::__copy_move<false, false, std::random_access_iterator_tag>::__copy_m(unsigned char const*, unsigned char co

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79136 Bug ID: 79136 Summary: read outside of buffer in char* std::__copy_move::__copy_m(unsigned char const*, unsigned

[RFC] fix bootstrap on aarch64-*-freebsd and probably others

Hi all, I have the following issue here on aarch64-*-freebsd: (sorry if the format is hardly readable) .. /export/devel/net/src/gcc/head/gcc/gcc/config/aarch64/aarch64.c: In function 'void aarch64_elf_asm_destructor(rtx, int)':

[Bug libstdc++/79135] New: null pointer dereference in std::_Bit_reference::operator=(bool) (stl_bvector.h:87)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79135 Bug ID: 79135 Summary: null pointer dereference in std::_Bit_reference::operator=(bool) (stl_bvector.h:87) Product: gcc Version: 6.2.1 Status:

[Bug libfortran/79134] New: Implicit declaration of free due to missing include

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79134 Bug ID: 79134 Summary: Implicit declaration of free due to missing include Product: gcc Version: 6.3.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug libstdc++/69301] std::atomic::load() won't compile if T doesn't have a default constructor

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69301 --- Comment #4 from Jonathan Wakely --- Fixed on trunk. Backports to follow.

[Bug libstdc++/69301] std::atomic::load() won't compile if T doesn't have a default constructor

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69301 --- Comment #3 from Jonathan Wakely --- Author: redi Date: Wed Jan 18 18:36:45 2017 New Revision: 244588 URL: https://gcc.gnu.org/viewcvs?rev=244588=gcc=rev Log: PR69301 don't assume atomic can default construct T PR libstdc++/69301

[PATCH] PR69301 don't assume atomic can default construct T

This fixes an invalid assumption that std::atomic can default construct a T. It also fixes some variables called "tmp" with non-uglified names. PR libstdc++/69301 * include/std/atomic (atomic::load, atomic::exchange): Use aligned buffer instead of default-initialized

[Bug target/79040] vec_cntlz redefined

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79040 Bill Schmidt changed: What|Removed |Added Assignee|meissner at gcc dot gnu.org|wschmidt at gcc dot gnu.org ---

Re: [PATCH, Fortran, pr70696, v2] [Coarray] ICE on EVENT POST of host-associated EVENT_TYPE coarray

Hi Jerry, thanks for the fast review. Committed as r244587. Regards, Andre On Wed, 18 Jan 2017 09:38:40 -0800 Jerry DeLisle wrote: > On 01/18/2017 04:26 AM, Andre Vehreschild wrote: > > Hi all, > > > > the patch I proposed for this pr unfortunately did not catch

[Bug fortran/70696] [Coarray] ICE on EVENT POST of host-associated EVENT_TYPE coarray

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70696 --- Comment #11 from vehre at gcc dot gnu.org --- Author: vehre Date: Wed Jan 18 18:35:41 2017 New Revision: 244587 URL: https://gcc.gnu.org/viewcvs?rev=244587=gcc=rev Log: gcc/fortran/ChangeLog: 2017-01-17 Andre Vehreschild

[PATCH, rs6000] Update some Power9 latencies

The following patch updates a few latencies in the Power9 machine description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk? -Pat 2017-01-18 Pat Haugen * config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add

[PR c++/78469] default ctor makes dtor required

Jason, I've figured out what's happening here. Just not sure of the most prudent way to fix it. struct no_destr { no_destr() = default; protected: ~no_destr() = default; }; void *Foo () { return new no_destr (); } no_destr is a type for which the default ctor is not DECL_ARTIFICIAL,

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