Re: Potential bug with wide_int_storage::set_len

[Andre Vieira (lists)]

On 12/10/16 18:59, Eric Botcazou wrote:
>> During the development of a patch I encountered some strange behavior
>> and decided to investigate. The result of which is I think I found a bug
>> with 'wide_int_storage::set_len' in gcc/wide-int.h.
>>
>> The function reads:
>> inline void
>> wide_int_storage::set_len (unsigned int l, bool is_sign_extended)
>> {
>>   len = l;
>>   if (!is_sign_extended && len * HOST_BITS_PER_WIDE_INT > precision)
>> val[len - 1] = sext_hwi (val[len - 1],
>>  precision % HOST_BITS_PER_WIDE_INT);
>> }
> 
> The code certainly lacks a comment explaining the apparent discrepancy.

It could do some comments yes. Also, it might also be worth changing the
comments on 'wide_int_storage::from':

/* Treat X as having signedness SGN and convert it to a PRECISION-bit
   number.  */
inline wide_int
wide_int_storage::from (const wide_int_ref , unsigned int precision,
signop sgn)
{
  wide_int result = wide_int::create (precision);
  result.set_len (wi::force_to_size (result.write_val (), x.val, x.len,
 x.precision, precision, sgn));
  return result;
}

If set_len really does 'ignore' signedness, then we are not treating X
as having signedness SGN. Right?

Cheers,
Andre

Re: Potential bug with wide_int_storage::set_len

[Andre Vieira (lists)]

> That is correct.  In RTL constants are always sign-extended from their
> precision to HOST_BITS_PER_WIDE_INT, regardless if it is "signed" or
> "unsigned" constant.  Whether you treat the low precision bits of the
> constant as signed or unsigned is something encoded in the operation on it.
> 
>   Jakub
> 
Euhm, but then surely we must get rid of the is_sign_extended parameter
altogether?

Right now if you call that function for the same example, but with
is_sign_extended set to true, the value will __NOT__ be sign extended.

Potential bug with wide_int_storage::set_len

[Andre Vieira (lists)]

Hello,

During the development of a patch I encountered some strange behavior
and decided to investigate. The result of which is I think I found a bug
with 'wide_int_storage::set_len' in gcc/wide-int.h.

The function reads:
inline void
wide_int_storage::set_len (unsigned int l, bool is_sign_extended)
{
  len = l;
  if (!is_sign_extended && len * HOST_BITS_PER_WIDE_INT > precision)
val[len - 1] = sext_hwi (val[len - 1],
 precision % HOST_BITS_PER_WIDE_INT);
}

Now assume you have a wide_int_storage, lets call it 'result' with the
following values:
val = [ 0x, ...];
len = 1;
precision = 32;

Say you are running it on a 64-bit host:
#define HOST_BITS_PER_WIDE_INT 64

and you call 'result.set_len (1, false);'

Then this will sign extend the first element of val, to
0x, and I don't think this is what you want.

Due to this, 'expand_expr' will expand a constant tree with unsigned
integer type and value MAX_UINT to a rtx node (const_int -1).

Am I missing something here?

Cheers,
Andre

PS: I will be running tests with a patch to remove the negation in front
of 'is_sign_extended' and post the patch in gcc-patches. If anyone
thinks this is wrong and wants to spare me the effort please reply!

Potential bug with wide_int_storage::set_len

[Andre Vieira (lists)]

Hello,

During the development of a patch I encountered some strange behavior
and decided to investigate. The result of which is I think I found a bug
with 'wide_int_storage::set_len' in gcc/wide-int.h.

The function reads:
inline void
wide_int_storage::set_len (unsigned int l, bool is_sign_extended)
{
  len = l;
  if (!is_sign_extended && len * HOST_BITS_PER_WIDE_INT > precision)
val[len - 1] = sext_hwi (val[len - 1],
 precision % HOST_BITS_PER_WIDE_INT);
}

Now assume you have a wide_int_storage, lets call it 'result' with the
following values:
val = [ 0x, ...];
len = 1;
precision = 32;

Say you are running it on a 64-bit host:
#define HOST_BITS_PER_WIDE_INT 64

and you call 'result.set_len (1, false);'

Then this will sign extend the first element of val, to
0x, and I don't think this is what you want.

Due to this, 'expand_expr' will expand a constant tree with unsigned
integer type and value MAX_UINT to a rtx node (const_int -1).

Am I missing something here?

Cheers,
Andre

PS: I will be running tests with a patch to remove the negation in front
of 'is_sign_extended' and post the patch in gcc-patches. If anyone
thinks this is wrong and wants to spare me the effort please reply!

[committed][ARM]Fix arm-netbsdelf bootstrap

[Andre Vieira (lists)]

On 02/12/16 21:16, Jeff Law wrote:
> 
> Trying to build arm-netbsdelf:
> 
> g++ -fno-PIE -c   -g -O2 -DIN_GCC  -DCROSS_DIRECTORY_STRUCTURE
> -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
> -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute
> -Woverloaded-virtual -pedantic -Wno-long-long -Wno-variadic-macros
> -Wno-overlength-strings -Werror -fno-common  -DHAVE_CONFIG_H -I. -I.
> -I/home/cygnus/law/gcc-testing/gcc/gcc
> -I/home/cygnus/law/gcc-testing/gcc/gcc/.
> -I/home/cygnus/law/gcc-testing/gcc/gcc/../include
> -I/home/cygnus/law/gcc-testing/gcc/gcc/../libcpp/include
> -I/opt/cfarm/mpc/include
> -I/home/cygnus/law/gcc-testing/gcc/gcc/../libdecnumber
> -I/home/cygnus/law/gcc-testing/gcc/gcc/../libdecnumber/dpd
> -I../libdecnumber -I/home/cygnus/law/gcc-testing/gcc/gcc/../libbacktrace
>   -o arm.o -MT arm.o -MMD -MP -MF ./.deps/arm.TPo
> /home/cygnus/law/gcc-testing/gcc/gcc/config/arm/arm.c
> /home/cygnus/law/gcc-testing/gcc/gcc/config/arm/arm.c:600:0: error:
> "TARGET_ASM_INIT_SECTIONS" redefined [-Werror]
>  #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
> 
> In file included from
> /home/cygnus/law/gcc-testing/gcc/gcc/target-def.h:106:0,
>  from
> /home/cygnus/law/gcc-testing/gcc/gcc/config/arm/arm.c:69:
> ./target-hooks-def.h:86:0: note: this is the location of the previous
> definition
>  #define TARGET_ASM_INIT_SECTIONS hook_void_void
> 
> 
> It's referring to this section of code.  Note the placement of the
> #endif.  Looks weird, not sure if it's in the right place, should be a
> line earlier or a line later:
> 
> #if ARM_UNWIND_INFO
> #undef TARGET_ASM_UNWIND_EMIT
> #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
> 
> /* EABI unwinding tables use a different format for the typeinfo
> tables.  */
> #undef TARGET_ASM_TTYPE
> #define TARGET_ASM_TTYPE arm_output_ttype
> 
> #undef TARGET_ARM_EABI_UNWINDER
> #define TARGET_ARM_EABI_UNWINDER true
> 
> #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
> #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
> 
> #undef TARGET_ASM_INIT_SECTIONS
> #endif /* ARM_UNWIND_INFO */
> #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
Hi Jeff,

Sorry about that, I meant to copy the whole thing out of the #if.

Committed this as obvious in revision r243240.

gcc/ChangeLog:

* config/arm/arm.c (TARGET_ASM_INIT_SECTIONS): Fix wrong undef
location.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
ec1f5fc5e0d9ff8ba41778ff5bb698bc50eefc5b..437da6fe3d34978e7a3a72f7ec39dc76a54d6408
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -595,8 +595,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
 
-#undef TARGET_ASM_INIT_SECTIONS
 #endif /* ARM_UNWIND_INFO */
+
+#undef TARGET_ASM_INIT_SECTIONS
 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
 
 #undef TARGET_DWARF_REGISTER_SPAN

[GCC] Add aarch64 to zero_bits_compound testing

[Andre Vieira (lists)]

Hello,

This patch adds aarch64*-*-* to the list of supported targets for the
recently added zero bits compound tests.
Tested for aarch64-none-elf and aarch64_be-none-elf.

Is this OK?

Cheers,
Andre

gcc/testsuite/ChangeLog
2016-06-10  Andre Vieira  

* gcc.dg/zero_bits_compound-1.c: Support aarch64.
* gcc.dg/zero_bits_compound-1.c: Likewise.
diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
index d78dc43d0a4d9c22b9c19a8435ca0f976b9819b6..650da60c0c33f912fd94fa330551a809d1d0fe67 100644
--- a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
+++ b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
@@ -4,7 +4,7 @@
 /* Note: This test requires that char, int and long have different sizes and the
target has a way to do 32 -> 64 bit zero extension other than AND.  */
 
-/* { dg-do compile { target x86_64-*-* s390*-*-* } } */
+/* { dg-do compile { target x86_64-*-* s390*-*-* aarch64*-*-* } } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-options "-O3 -dP" } */
 
diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-2.c b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
index 80fd363d9552e221d48801d2f29717ca5f3a42d4..f282b94d77915fd1717f3a51dc35c12682453f85 100644
--- a/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
+++ b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c
@@ -1,7 +1,7 @@
 /* Test whether an AND mask or'ed with the know zero bits that equals a mode
mask is a candidate for zero extendion.  */
 
-/* { dg-do compile { target x86_64-*-* s390*-*-* } } */
+/* { dg-do compile { target x86_64-*-* s390*-*-* aarch64*-*-* } } */
 /* { dg-require-effective-target lp64 } */
 /* { dg-options "-O3 -dP" } */
 

[arm-embedded][committed] patch for PR61578

[Andre Vieira (lists)]

Hi

Backported the following two patches to embedded-5-branch:
https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00096.html
https://gcc.gnu.org/ml/gcc-patches/2015-09/msg02028.html

Committed as revisions r237369 and r237371.


gcc/ChangeLog.arm:

2016-06-13  Andre Vieira  

Backport from Mainline
2015-09-25  Vladimir Makarov  

PR target/61578
* lra-constarints.c (match_reload): Check presence of the input pseudo
  in the output pseudo.


2016-06-13 Andre Vieira 
Backport from Mainline
2015-09-01  Vladimir Makarov  

PR target/61578
* lra-lives.c (process_bb_lives): Process move pseudos with the
  same value for copies and preferences
* lra-constraints.c (match_reload): Create match reload pseudo
  with the same value from single dying input pseudo.


Cheers,
Andre

Re: [PING^4][PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

Ping.

On 19/05/16 11:19, Andre Vieira (lists) wrote:
> Ping for GCC-7, patch applies cleanly, passed make check for cortex-m0.
> 
> Might be worth mentioning that this patch has been used in three
> releases of the GNU ARM embedded toolchain, using GCC versions 4.9 and
> 5, and no issues have been reported so far.
> 
> On 25/01/16 17:15, Andre Vieira (lists) wrote:
>> Ping.
>>
>> On 27/10/15 17:03, Andre Vieira wrote:
>>> Ping.
>>>
>>> BR,
>>> Andre
>>>
>>> On 13/10/15 18:01, Andre Vieira wrote:
>>>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings
>>>> (https://git.linaro.org/toolchain/cortex-strings.git), which was
>>>> contributed by ARM under Free BSD license.
>>>>
>>>> The new aeabi_idiv routine is used to replace the one in
>>>> libgcc/config/arm/lib1funcs.S. This replacement happens within the
>>>> Thumb1 wrapper. The new routine is under LGPLv3 license.
>>>>
>>>> The main advantage of this version is that it can improve the
>>>> performance of the aeabi_idiv function for Thumb1. This solution will
>>>> also increase the code size. So it will only be used if
>>>> __OPTIMIZE_SIZE__ is not defined.
>>>>
>>>> Make check passed for armv6-m.
>>>>
>>>> libgcc/ChangeLog:
>>>> 2015-08-10  Hale Wang  <hale.w...@arm.com>
>>>>   Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>
>>>> * config/arm/lib1funcs.S: Add new wrapper.
>>>>
>>
> 

[PATCH][ARM] Updating testcase unsigned-extend-2.c

[Andre Vieira (lists)]

Hello,

After some changes to GCC this test no longer tests the desired code
generation behavior. The generated assembly is better than it used to
be, but it has become too smart. I add an extra parameter to make sure
GCC can't optimize away the loop.

Tested for arm-none-eabi-gcc with a Cortex-M3 target.

Is this OK?

Cheers,
Andre

gcc/ChangeLog
2016-06-21  Andre Vieira  

* gcc.target/arm/unsigned-extend-2.c: Update testcase.
>From 12da0a48045b37efb2e459116ec81cc7117a0981 Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira 
Date: Mon, 20 Jun 2016 14:27:06 +0100
Subject: [PATCH] fix testcase

---
 gcc/testsuite/gcc.target/arm/unsigned-extend-2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
index b610b73617dc6e6a5428c966380516007a02acba..013240749ecaabf0d2e8ad802d27c7edc69d8828 100644
--- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
+++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
@@ -2,13 +2,13 @@
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-options "-O" } */
 
-unsigned short foo (unsigned short x)
+unsigned short foo (unsigned short x, unsigned short c)
 {
   unsigned char i = 0;
   for (i = 0; i < 8; i++)
 {
   x >>= 1;
-  x &= 0x7fff;
+  x &= c;
 }
   return x;
 }
-- 
1.9.1

Re: [PING^5][PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

Ping.

On 08/06/16 15:35, Andre Vieira (lists) wrote:
> Ping.
> 
> On 19/05/16 11:19, Andre Vieira (lists) wrote:
>> Ping for GCC-7, patch applies cleanly, passed make check for cortex-m0.
>>
>> Might be worth mentioning that this patch has been used in three
>> releases of the GNU ARM embedded toolchain, using GCC versions 4.9 and
>> 5, and no issues have been reported so far.
>>
>> On 25/01/16 17:15, Andre Vieira (lists) wrote:
>>> Ping.
>>>
>>> On 27/10/15 17:03, Andre Vieira wrote:
>>>> Ping.
>>>>
>>>> BR,
>>>> Andre
>>>>
>>>> On 13/10/15 18:01, Andre Vieira wrote:
>>>>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings
>>>>> (https://git.linaro.org/toolchain/cortex-strings.git), which was
>>>>> contributed by ARM under Free BSD license.
>>>>>
>>>>> The new aeabi_idiv routine is used to replace the one in
>>>>> libgcc/config/arm/lib1funcs.S. This replacement happens within the
>>>>> Thumb1 wrapper. The new routine is under LGPLv3 license.
>>>>>
>>>>> The main advantage of this version is that it can improve the
>>>>> performance of the aeabi_idiv function for Thumb1. This solution will
>>>>> also increase the code size. So it will only be used if
>>>>> __OPTIMIZE_SIZE__ is not defined.
>>>>>
>>>>> Make check passed for armv6-m.
>>>>>
>>>>> libgcc/ChangeLog:
>>>>> 2015-08-10  Hale Wang  <hale.w...@arm.com>
>>>>>   Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>>
>>>>> * config/arm/lib1funcs.S: Add new wrapper.
>>>>>
>>>
>>
> 

[PATCH][GCC-5] Fix "#pragma GCC pop_options" warning.

[Andre Vieira (lists)]

Hi there,

Can we have the "#pragma GCC pop_options" fix backported to GCC-5?

Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html 
and was committed in r228794.


The same patch applies cleanly to gcc-5, which would otherwise not be 
able to use this pragma even though the support is there.


Cheers,
Andre

Re: [Ping^3][PATCH][GCC][ARM] testcase memset-inline-10.c uses -mfloat-abi=hard but does not check whether target supports it

[Andre Vieira (lists)]

On 05/01/16 17:40, Andre Vieira wrote:

On 27/11/15 14:28, Andre Vieira wrote:

On 12/11/15 15:16, Andre Vieira wrote:

On 12/11/15 15:08, Andre Vieira wrote:

Hi,

   This patch changes the memset-inline-10.c testcase to make sure that
it is only compiled for ARM targets that support -mfloat-abi=hard using
the fact that all non-thumb1 targets do.

   This is correct because all targets for which -mthumb causes the
compiler to use thumb2 will support the generation of FP instructions.

   Tested by running regressions for this testcase for various ARM
targets.

   Is this OK to commit?

   Thanks,
   Andre Vieira

gcc/testsuite/ChangeLog:
2015-11-06  Andre Vieira  

 * gcc.target/arm/memset-inline-10.c: Added
 dg-require-effective-target arm_thumb2_ok.


Now with attachment, sorry about that.

Cheers,
Andre


Ping.



Ping.


Ping.

Re: [PATCH] Fix math transformation on targets without c99 math functions

[Andre Vieira (lists)]

On 11/01/16 16:39, Jakub Jelinek wrote:

On Mon, Jan 11, 2016 at 05:11:21PM +0100, Christophe Lyon wrote:

I tested a similar version on my side. It just makes the test become
UNSUPPORTED for arm/aarch64 + newlib. They used to pass, though.


Is anything bad on that?  The test tests functions that newlib does not
implement, so it is not wrong not to optimize those.

Jakub



Unfortunately c99_functions is a very wide net. For instance, newlib 
supports the ceill, but doesn't support wscanf_s nor any bounds checking 
function I think.


I extracted all function names from the C99 standard and did a quick nm 
and grep to look into whether newlib defined these for arm-none-eabi.


The functions I found missing fall into the following sections:
- Complex Arithmetic (which fall under the function_c99_math_complex class)
- floating-point environment
- Functions for greatest-width integer types
- atomics (missing atomic_is_lock_free and atomic_fetch_key)
- Bounds-checking interfaces

So arm-none-eabi used to be able to "legally" perform the transformation 
that we are speaking of. Though since that optimization is now guarded 
with the function_c99_misc class it is no longer performed, since we can 
not claim newlib supports all functions that are caught by 
function_c99_misc.


I don't quite know how to proceed. I suspect a new function class for 
C99 math functions (excluding complex) would help here and probably more 
places too. Though, I don't know how much work it would be to split 
function_c99_misc in that manner.


Opinions welcome!!

Cheers,
Andre

Re: Fix PR69752, insn with REG_INC being removed as equiv_init insn

[Andre Vieira (lists)]

On 12/02/16 07:43, Jeff Law wrote:

On 02/11/2016 06:28 PM, Bernd Schmidt wrote:

This seems fairly straightforward:

(insn 213 455 216 6 (set (reg:SI 266)
 (mem/u/c:SI (post_inc:SI (reg/f:SI 267)) [4  S4 A32])) 748
{*thumb1_movsi_insn}
  (expr_list:REG_EQUAL (const_int -1044200508 [0xc1c2c3c4])
 (expr_list:REG_INC (reg/f:SI 267)
 (nil

We don't notice that the SET_SRC has a side effect, record the insn as
an equivalencing one, and later remove it because we replaced the reg
with the constant everywhere. Thus, the increment doesn't take place.

Fixed as follows. Bootstrapped and tested on x86_64-linux. Also compared
before/after dumps for the testcase with arm-elf. Ok?


Bernd

equiv-inc.diff


PR rtl-optimization/69752
* ira.c (update_equiv_regs): When looking for more than a single SET,
also take other side effects into account.

Also note that the reporter says gcc-4.9 didn't have this problem, so
there's a reasonable chance this is a latent regression exposed by
codegen changes prior to IRA.


OK for the trunk.

Jeff

I tested it for the particular testcase it was failing for cortex-m0 and 
it fixed it. Ill fire up a regression run next.


Cheers,
Andre

[PING] Re: [RFC][PATCH, ARM 8/8] Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic

[Andre Vieira (lists)]

On 26/12/15 01:59, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch adds support ARMv8-M's Security Extension's cmse_nonsecure_caller 
intrinsic. This intrinsic is used to check whether an entry function was called 
from a non-secure state.
See Section 5.4.3 of ARM®v8-M Security Extensions: Requirements on Development 
Tools (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html) 
for further details.

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm-builtins.c (arm_builtins): Define
   ARM_BUILTIN_CMSE_NONSECURE_CALLER.
   (bdesc_2arg): Add line for cmse_nonsecure_caller.
   (arm_init_builtins): Init for cmse_nonsecure_caller.
   (arm_expand_builtin): Handle cmse_nonsecure_caller.
 * gcc/config/arm/arm_cmse.h (cmse_nonsecure_caller): New.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse-1.c: Added test for
   cmse_nonsecure_caller.


diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
11cd17d0b8f3c29ccbe16cb463a17d55ba0fa1e3..7934cf1d4d96c40255d3e93dc9902b4568014984
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -515,6 +515,8 @@ enum arm_builtins
ARM_BUILTIN_GET_FPSCR,
ARM_BUILTIN_SET_FPSCR,

+  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+
  #undef CRYPTO1
  #undef CRYPTO2
  #undef CRYPTO3
@@ -1263,6 +1265,10 @@ static const struct builtin_description bdesc_2arg[] =
FP_BUILTIN (set_fpscr, SET_FPSCR)
  #undef FP_BUILTIN

+  {ARM_FSET_MAKE_CPU2 (FL2_CMSE), CODE_FOR_andsi3,
+   "__builtin_arm_cmse_nonsecure_caller", ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+   UNKNOWN, 0},
+
  #define CRC32_BUILTIN(L, U) \
{ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, \
 ARM_BUILTIN_##U, UNKNOWN, 0},
@@ -1797,6 +1803,17 @@ arm_init_builtins (void)
= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
  }
+
+  if (arm_arch_cmse)
+{
+  tree ftype_cmse_nonsecure_caller
+   = build_function_type_list (unsigned_type_node, NULL);
+  arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
+   = add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
+   ftype_cmse_nonsecure_caller,
+   ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
+   NULL, NULL_TREE);
+}
  }

  /* Return the ARM builtin for CODE.  */
@@ -2356,6 +2373,14 @@ arm_expand_builtin (tree exp,
emit_insn (pat);
return target;

+case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
+  icode = CODE_FOR_andsi3;
+  target = gen_reg_rtx (SImode);
+  op0 = arm_return_addr (0, NULL_RTX);
+  pat = GEN_FCN (icode) (target, op0, const1_rtx);
+  emit_insn (pat);
+  return target;
+
  case ARM_BUILTIN_TEXTRMSB:
  case ARM_BUILTIN_TEXTRMUB:
  case ARM_BUILTIN_TEXTRMSH:
diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h
index 
ab20a3ec46025f268a1e9bed895d27da9af7aab6..0bdff668d03d54e1acf2bdd3b5ff1bfb2b463bd8
 100644
--- a/gcc/config/arm/arm_cmse.h
+++ b/gcc/config/arm/arm_cmse.h
@@ -163,6 +163,13 @@ __attribute__ ((__always_inline__))
  cmse_TTAT (void *p)
  CMSE_TT_ASM (at)

+//TODO: diagnose use outside cmse_nonsecure_entry functions
+__extension__ static __inline int __attribute__ ((__always_inline__))
+cmse_nonsecure_caller (void)
+{
+  return __builtin_arm_cmse_nonsecure_caller ();
+}
+
  #define CMSE_AU_NONSECURE 2
  #define CMSE_MPU_NONSECURE16
  #define CMSE_NONSECURE18
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c 
b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
index 
1c3d4e9e934f4b1166d4d98383cf4ae8c3515117..ccecf396d3cda76536537b4d146bbb5f70589fd5
 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
@@ -66,3 +66,32 @@ int foo (char * p)
  /* { dg-final { scan-assembler-times "ttat " 2 } } */
  /* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
  /* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
+
+typedef int (*int_ret_funcptr_t) (void);
+typedef int __attribute__ ((cmse_nonsecure_call)) (*int_ret_nsfuncptr_t) 
(void);
+
+int __attribute__ ((cmse_nonsecure_entry))
+baz (void)
+{
+  return cmse_nonsecure_caller ();
+}
+
+int __attribute__ ((cmse_nonsecure_entry))
+qux (int_ret_funcptr_t int_ret_funcptr)
+{
+  int_ret_nsfuncptr_t int_ret_nsfunc_ptr;
+
+  if (cmse_is_nsfptr (int_ret_funcptr))
+{
+  int_ret_nsfunc_ptr = cmse_nsfptr_create (int_ret_funcptr);
+  return int_ret_nsfunc_ptr ();
+}
+  return 0;
+}
+/* { 

[PATCHv2] Re: [RFC][PATCH, ARM 7/8] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call]

[Andre Vieira (lists)]

On 19/01/16 15:28, Andre Vieira (lists) wrote:

On 16/01/16 14:49, Senthil Kumar Selvaraj wrote:

User-agent: mu4e 0.9.13; emacs 24.5.1

Hi,

Apologies for the bad posting style (I don't have the
original email handy), but shouldn't _gnu_cmse_nonsecure_call be defined
with the .global directive in the below hunk (to make it visible when
linking)?

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
b/libgcc/config/arm/cm=
se_nonsecure_call.S
new file mode 100644
index
..bdc140f5bbe87c6599db225b1b9=
b7bbc7d606710
--- /dev/null
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -0,0 +1,87 @@
+.syntax unified
+.thumb
+__gnu_cmse_nonsecure_call:

Right now, it ends up as a local symbol, and compiling and linking a
program with cmse_nonsecure_call (say cmse-11.c), results in a linker
error - the linker doesn't find the symbol even if it is present in
libgcc.a. I found the problem that way - dumping symbols for my variant
of libgcc.a and grepping showed the symbol to be available but local.

Regards
Senthil


Hi Senthil,

Thanks for catching that!

Cheers,
Andre


Hi there,

Added missing global symbol.

Is this OK?

Cheers,
Andre

*** gcc/ChangeLog ***
2016-01-29  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc/config/arm/arm.c (detect_cmse_nonsecure_call): New.
  (cmse_nonsecure_call_clear_caller_saved): New.
* gcc/config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
* gcc/config/arm/arm.md (call): Handle cmse_nonsecure_entry.
  (call_value): Likewise.
  (nonsecure_call_internal): New.
  (nonsecure_call_value_internal): New.
* gcc/config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
  (*nonsecure_call_value_reg_thumb1_v5): New.
* gcc/config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
  (*nonsecure_call_value_reg_thumb2): New.
* gcc/config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.
* libgcc/config/arm/cmse_nonsecure_call.S: New.
* libgcc/config/arm/t-arm: Compile cmse_nonsecure_call.S


*** gcc/testsuite/ChangeLog ***
2016-01-29  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-11.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-6.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
* gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 4fb4261794668752a8224e2d4a2363162ae9cb94..402313c5f4aeb9d2d26ea7d4a0412609142d490b 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -132,6 +132,7 @@ extern int arm_const_double_inline_cost (rtx);
 extern bool arm_const_double_by_parts (rtx);
 extern bool arm_const_double_by_immediates (rtx);
 extern void arm_emit_call_insn (rtx, rtx, bool);
+bool detect_cmse_nonsecure_call (tree);
 extern const char *output_call (rtx *);
 void arm_emit_movpair (rtx, rtx);
 extern const char *output_mov_long_double_arm_from_arm (rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index da33ba1136b97c5f534c135e6d39f8b5777b3f36..153c746ad1910ad8ea7527e74369930ca14d2594 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17417,6 +17417,129 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
   return;
 }
 
+/* Saves callee saved registers, clears callee saved registers and caller saved
+   registers not used to pass arguments before a cmse_nonsecure_call.  And
+   restores the callee saved registers after.  */
+
+static void
+cmse_nonsecure_call_clear_caller_saved (void)
+{
+  basic_block bb;
+
+  FOR_EACH_BB_FN (bb, cfun)
+{
+  rtx_insn *insn;
+
+  FOR_BB_INSNS (bb, insn)
+	{
+	  uint64_t to_clear_mask, float_mask;
+	  rtx_insn

[PING] Re: [RFC][PATCH, ARM 5/8] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

On 26/12/15 01:54, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch extends support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute to safeguard against leak of information 
through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved 
registers that are not used to pass return values, by writing either the LR, in 
case of general purpose registers, or the value 0, in case of FP registers. We 
use the LR to write to APSR and FPSCR too. We currently only support 32 FP 
registers as in we only clear D0-D7.
We currently do not support entry functions that pass arguments or return 
variables on the stack and we diagnose this. This patch relies on the existing 
code to make sure callee-saved registers used in cmse_nonsecure_entry functions 
are saved and restored thus retaining their nonsecure mode value, this should 
be happening already as it is required by AAPCS.


*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm.c (output_return_instruction): Clear
   registers.
   (thumb2_expand_return): Likewise.
   (thumb1_expand_epilogue): Likewise.
   (arm_expand_epilogue): Likewise.
   (cmse_nonsecure_entry_clear_before_return): New.
 * gcc/config/arm/arm.h (TARGET_DSP_ADD): New macro define.
 * gcc/config/arm/thumb1.md (*epilogue_insns): Change length attribute.
 * gcc/config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
 * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are 
cleared.
 * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.


diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
f12e3c93bbe24b10ed8eee6687161826773ef649..b06e0586a3da50f57645bda13629bc4dbd3d53b7
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -230,6 +230,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
  /* Integer SIMD instructions, and extend-accumulate instructions.  */
  #define TARGET_INT_SIMD \
(TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
+/* Parallel addition and subtraction instructions.  */
+#define TARGET_DSP_ADD \
+  (TARGET_ARM_ARCH >= 6 && (arm_arch_notm || arm_arch7em))

  /* Should MOVW/MOVT be used in preference to a constant pool.  */
  #define TARGET_USE_MOVT \
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
e530b772e3cc053c16421a2a2861d815d53ebb01..0700478ca38307f35d0cb01f83ea182802ba28fa
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19755,6 +19755,24 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
default:
  if (IS_CMSE_ENTRY (func_type))
{
+ char flags[12] = "APSR_nzcvq";
+ /* Check if we have to clear the 'GE bits' which is only used if
+parallel add and subtraction instructions are available.  */
+ if (TARGET_DSP_ADD)
+   {
+ /* If so also clear the ge flags.  */
+ flags[10] = 'g';
+ flags[11] = '\0';
+   }
+ snprintf (instr, sizeof (instr),  "msr%s\t%s, %%|lr", conditional,
+   flags);
+ output_asm_insn (instr, & operand);
+ if (TARGET_HARD_FLOAT && TARGET_VFP)
+   {
+ snprintf (instr, sizeof (instr), "vmsr%s\tfpscr, %%|lr",
+   conditional);
+ output_asm_insn (instr, & operand);
+   }
  snprintf (instr, sizeof (instr), "bxns%s\t%%|lr", conditional);
}
  /* Use bx if it's available.  */
@@ -23999,6 +24017,17 @@ thumb_pop (FILE *f, unsigned long mask)
  static void
  thumb1_cmse_nonsecure_entry_return (FILE *f, int reg_containing_return_addr)
  {
+  char flags[12] = "APSR_nzcvq";
+  /* Check if we have to clear the 'GE bits' which is only used if
+ parallel add and subtraction instructions are available.  */
+  if (TARGET_DSP_ADD)
+{
+  flags[10] = 'g';
+  flags[11] = '\0';
+}
+  asm_fprintf (f, "\tmsr\t%s, %r\n", flags, reg_containing_return_addr);
+  if (TARGET_HARD_FLOAT && TARGET_VFP)
+asm_fprintf (f, "\tvmsr\tfpscr, %r\n", reg_containing_return_addr);
asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
  }

@@ -25140,6 +25169,139 @@ 

[PING] Re: [RFC][PATCH, ARM 6/8] Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute

[Andre Vieira (lists)]

On 26/12/15 01:55, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch adds support for the ARMv8-M Security Extensions 
'cmse_nonsecure_call' attribute. This attribute may only be used for function 
types and when used in combination with the '-mcmse' compilation flag. See 
Section 5.5 of ARM®v8-M Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently do not support cmse_nonsecure_call functions that pass arguments 
or return variables on the stack and we diagnose this.

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm.c (gimplify.h): New include.
   (arm_handle_cmse_nonsecure_call): New.
   (arm_attribute_table): Added cmse_nonsecure_call.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse-3.c: Add tests.
 * gcc.target/arm/cmse/cmse-4.c: Add tests.


diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
0700478ca38307f35d0cb01f83ea182802ba28fa..4b4eea88cbec8e04d5b92210f0af2440ce6fb6e4
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -61,6 +61,7 @@
  #include "builtins.h"
  #include "tm-constrs.h"
  #include "rtl-iter.h"
+#include "gimplify.h"

  /* This file should be included last.  */
  #include "target-def.h"
@@ -136,6 +137,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
  static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
  #endif
  static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
+static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
  static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
  static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
  static int arm_comp_type_attributes (const_tree, const_tree);
@@ -347,6 +349,8 @@ static const struct attribute_spec arm_attribute_table[] =
/* ARMv8-M Security Extensions support.  */
{ "cmse_nonsecure_entry", 0, 0, true, false, false,
  arm_handle_cmse_nonsecure_entry, false },
+  { "cmse_nonsecure_call", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_call, false },
{ NULL,   0, 0, false, false, false, NULL, false }
  };


@@ -6667,6 +6671,76 @@ arm_handle_cmse_nonsecure_entry (tree *node, tree name,
return NULL_TREE;
  }

+
+/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
+   function will check whether the attribute is allowed here and will add the
+   attribute to the function type tree or otherwise issue a diagnose.  The
+   reason we check this at declaration time is to only allow the use of the
+   attribute with declartions of function pointers and not function
+   declartions.  */
+
+static tree
+arm_handle_cmse_nonsecure_call (tree *node, tree name,
+tree /* args */,
+int /* flags */,
+bool *no_add_attrs)
+{
+  tree decl = NULL_TREE;
+  tree type, fntype, main_variant;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}
+
+  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
+{
+  decl = *node;
+  type = TREE_TYPE (decl);
+}
+
+  if (!decl
+  || (!(TREE_CODE (type) == POINTER_TYPE
+   && TREE_CODE (TREE_TYPE (type)) == FUNCTION_TYPE)
+ && TREE_CODE (type) != FUNCTION_TYPE))
+{
+   warning (OPT_Wattributes, "%qE attribute only applies to base type of a 
"
+"function pointer", name);
+   *no_add_attrs = true;
+   return NULL_TREE;
+}
+
+  /* type is either a function pointer, when the attribute is used on a 
function
+   * pointer, or a function type when used in a typedef.  */
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+fntype = type;
+  else
+fntype = TREE_TYPE (type);
+
+  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
+
+  if (*no_add_attrs)
+return NULL_TREE;
+
+  /* Prevent tree's being shared among function types with and without
+ cmse_nonsecure_call attribute.  Do however make sure they keep the same
+ main_variant, this is required for correct DIE output.  */
+  main_variant = TYPE_MAIN_VARIANT (fntype);
+  fntype = build_distinct_type_copy (fntype);
+  TYPE_MAIN_VARIANT (fntype) = main_variant;
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+TREE_TYPE (decl) = fntype;
+  else
+TREE_TYPE (type) = fntype;
+
+  /* Construct a type attribute and add it to the function type.  */
+  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
+ TYPE_ATTRIBUTES (fntype));
+  TYPE_ATTRIBUTES (fntype) = attrs;
+  return NULL_TREE;
+}
+
  /* 

[PING] Re: [RFC][PATCH, ARM 3/8] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Andre Vieira (lists)]

On 26/12/15 01:47, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch adds support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute. In this patch we implement the attribute 
handling and diagnosis around the attribute. See Section 5.4 of ARM®v8-M 
Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
   (arm_attribute_table): Added cmse_nonsecure_entry
   (arm_compute_func_type): Handle cmse_nonsecure_entry.
   (cmse_func_args_or_return_in_stack): New.
   (arm_handle_cmse_nonsecure_entry): New.
 * gcc/config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
   (IS_CMSE_ENTRY): Likewise.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse-3.c: New.


diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
cf6d9466fb79e4f8a2dbfe725c52d5be8ea24fd2..f12e3c93bbe24b10ed8eee6687161826773ef649
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1375,6 +1375,7 @@ enum reg_class
  #define ARM_FT_VOLATILE   (1 << 4) /* Does not return.  */
  #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func.  */
  #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack.  */
+#define ARM_FT_CMSE_ENTRY  (1 << 7) /* ARMv8-M non-secure entry function.  
*/

  /* Some macros to test these flags.  */
  #define ARM_FUNC_TYPE(t)  (t & ARM_FT_TYPE_MASK)
@@ -1383,6 +1384,7 @@ enum reg_class
  #define IS_NAKED(t)   (t & ARM_FT_NAKED)
  #define IS_NESTED(t)  (t & ARM_FT_NESTED)
  #define IS_STACKALIGN(t)  (t & ARM_FT_STACKALIGN)
+#define IS_CMSE_ENTRY(t)   (t & ARM_FT_CMSE_ENTRY)


  /* Structure used to hold the function stack frame layout.  Offsets are
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
2223101fbf96bceb4beb3a7d6cb04162481dc3bf..5b9e51b10e91eee64e3383c1ed50269c3e6cf24c
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -135,6 +135,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
  #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
  static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
  #endif
+static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
  static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
  static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
  static int arm_comp_type_attributes (const_tree, const_tree);
@@ -343,6 +344,9 @@ static const struct attribute_spec arm_attribute_table[] =
{ "notshared",0, 0, false, true, false, arm_handle_notshared_attribute,
  false },
  #endif
+  /* ARMv8-M Security Extensions support.  */
+  { "cmse_nonsecure_entry", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_entry, false },
{ NULL,   0, 0, false, false, false, NULL, false }
  };


@@ -3562,6 +3566,9 @@ arm_compute_func_type (void)
else
  type |= arm_isr_value (TREE_VALUE (a));

+  if (lookup_attribute ("cmse_nonsecure_entry", attr))
+type |= ARM_FT_CMSE_ENTRY;
+
return type;
  }

@@ -6552,6 +6559,109 @@ arm_handle_notshared_attribute (tree *node,
  }
  #endif

+/* This function is used to check whether functions with attributes
+   cmse_nonsecure_call or cmse_nonsecure_entry use the stack to pass arguments
+   or return variables.  If the function does indeed use the stack this
+   function returns true and diagnoses this, otherwise it returns false.  */
+
+static bool
+cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
+
+  /* Error out if any argument is passed on the stack.  */
+  arm_init_cumulative_args (_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+{
+  rtx arg_rtx;
+  machine_mode arg_mode = TYPE_MODE (arg_type);
+
+  prev_arg_type = arg_type;
+  if (VOID_TYPE_P (arg_type))
+   continue;
+
+  if (!first_param)
+   arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
+  arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
+  if (!arg_rtx
+ || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
+   {
+ error ("%qE attribute not available to functions with arguments "
+"passed on the stack", name);
+ return true;
+   }
+ 

Re: [RFC][PATCH , ARM 2/8] Add RTL patterns for thumb1 push/pop

[Andre Vieira (lists)]

On 26/12/15 01:45, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch adds RTL patterns for the push and pop instructions for thumb1. 
These are needed by subsequent patches in the series.

*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm-ldmstm.nl (constr thumb): Enabled
   stackpointer to be written/read.
 * gcc/config/arm/ldmstm.md: Regenerated.
 * gcc/config/arm/thumb1.md (*thumb1_pop_single): New.
   (*thumb1_load_multiple_operation): New.
 * gcc/config/arm/arm.c (thumb_pop): Fix of comment.


diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml
index 
62982df594d5d4a1407df359e927c66986a9788c..f3ee741e93927d8d44a9eccec8970b46a8984216
 100644
--- a/gcc/config/arm/arm-ldmstm.ml
+++ b/gcc/config/arm/arm-ldmstm.ml
@@ -63,7 +63,7 @@ let rec final_offset addrmode nregs =
| DB -> -4 * nregs

  let constr thumb =
-  if thumb then "l" else "rk"
+  if thumb then "lk" else "rk"

  let inout_constr op_type =
match op_type with
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
06a6184ee0c4ed1a7cec1de4c1786e297cc57872..2223101fbf96bceb4beb3a7d6cb04162481dc3bf
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -23773,8 +23773,8 @@ thumb1_emit_multi_reg_push (unsigned long mask, 
unsigned long real_regs)
return insn;
  }

-/* Emit code to push or pop registers to or from the stack.  F is the
-   assembly file.  MASK is the registers to pop.  */
+/* Emit code to pop registers from the stack.  F is the assembly file.
+   MASK is the registers to pop.  */
  static void
  thumb_pop (FILE *f, unsigned long mask)
  {
diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
index 
ebb09ab86e799f3606e0988980edf3cd0189272b..8c0472e07799bd9d08759e35b6b98f3536d3d013
 100644
--- a/gcc/config/arm/ldmstm.md
+++ b/gcc/config/arm/ldmstm.md
@@ -43,7 +43,7 @@
  (define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation"
  [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 5 "s_register_operand" "lk")))
   (set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 5)
(const_int 4
@@ -80,7 +80,7 @@

  (define_insn "*thumb_ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 5 "s_register_operand" "+")
+[(set (match_operand:SI 5 "s_register_operand" "+")
(plus:SI (match_dup 5) (const_int 16)))
   (set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_dup 5)))
@@ -133,7 +133,7 @@

  (define_insn "*thumb_stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
-[(set (match_operand:SI 5 "s_register_operand" "+")
+[(set (match_operand:SI 5 "s_register_operand" "+")
(plus:SI (match_dup 5) (const_int 16)))
   (set (mem:SI (match_dup 5))
(match_operand:SI 1 "low_register_operand" ""))
@@ -491,7 +491,7 @@
  (define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation"
  [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 4 "s_register_operand" "lk")))
   (set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 4)
(const_int 4
@@ -522,7 +522,7 @@

  (define_insn "*thumb_ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 4 "s_register_operand" "+")
+[(set (match_operand:SI 4 "s_register_operand" "+")
(plus:SI (match_dup 4) (const_int 12)))
   (set (match_operand:SI 1 "low_register_operand" "")
(mem:SI (match_dup 4)))
@@ -568,7 +568,7 @@

  (define_insn "*thumb_stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
-[(set (match_operand:SI 4 "s_register_operand" "+")
+[(set (match_operand:SI 4 "s_register_operand" "+")
(plus:SI (match_dup 4) (const_int 12)))
   (set (mem:SI (match_dup 4))
(match_operand:SI 1 "low_register_operand" ""))
@@ -877,7 +877,7 @@
  (define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation"
  [(set (match_operand:SI 1 "low_register_operand" "")
-  (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
+  (mem:SI (match_operand:SI 3 "s_register_operand" "lk")))
   (set (match_operand:SI 2 "low_register_operand" "")
(mem:SI (plus:SI (match_dup 3)
(const_int 4])]
@@ -902,7 +902,7 @@

  (define_insn "*thumb_ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation"
-[(set (match_operand:SI 3 "s_register_operand" "+")
+[(set (match_operand:SI 3 

[PATCHv2] Re: [RFC][PATCH, ARM 1/8] Add support for ARMv8-M's Security Extensions flag and intrinsics

[Andre Vieira (lists)]

On 05/01/16 14:38, Andre Vieira wrote:

On 31/12/15 20:54, Joseph Myers wrote:

On Sat, 26 Dec 2015, Thomas Preud'homme wrote:


+#define CMSE_TT_ASM(flags) \
+{ \
+  cmse_address_info_t result; \
+   __asm__ ("tt" # flags " %0,%1" \
+   : "=r"(result) \
+   : "r"(p) \
+   : "memory"); \
+  return result; \


Are the identifiers "result" and "p" really meant to be reserved by this
header (so that users can't have macros with those names before including
it), or should they actually be __result and __p (and likewise for any
other identifiers in this file not specified as reserved)?


+__extension__ void *
+cmse_check_address_range (void *p, size_t size, int flags);


Are "size" and "flags" really meant to be reserved?


+@item -mcmse
+@opindex mcmse
+Generate secure code as per ARMv8-M Security Extensions.


I think you also need a section in extend.texi much like the existing
ACLE
section, to describe support for this as a language extension.



I'll change all non-reserved and 'not-ment-for-export' identifiers to be
preceded by '__' and Ill also look into adding a section for ARMv8-M
Security Extensions (CMSE) to extend.texi.

Thank you for your feedback.

BR,
Andre


Hi there,

Forgot to send the reworked patch upstream, here it is following 
Joseph's comments. Thank you again.


Is this OK?

Cheers,
Andre

*** gcc/ChangeLog ***
2016-01-29  Andre Vieira
Thomas Preud'homme  

* gcc/config.gcc (extra_headers): Added arm_cmse.h.
* gcc/config/arm/arm-arches.def (ARM_ARCH):
  (armv8-m): Add FL2_CMSE.
  (armv8-m.main): Likewise.
  (armv8-m.main+dsp): Likewise.
* gcc/config/arm/arm-c.c
  (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
* gcc/config/arm/arm-protos.h
  (arm_is_constant_pool_ref): Define FL2_CMSE.
* gcc/config/arm.c (arm_arch_cmse): New.
  (arm_option_override): New error for unsupported cmse target.
* gcc/config/arm/arm.h (arm_arch_cmse): New.
* gcc/config/arm/arm.opt (mcmse): New.
* gcc/doc/invoke.texi (ARM Options): Add -mcmse.
* gcc/doc/extend.texi (ACLE): Add CMSE.
* gcc/config/arm/arm_cmse.h: New file.
* libgcc/config/arm/cmse.c: Likewise.
* libgcc/config/arm/t-arm (HAVE_CMSE): New.


*** gcc/testsuite/ChangeLog ***
2016-01-29  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: New.
* gcc.target/arm/cmse/cmse-1.c: New.
* gcc.target/arm/cmse/cmse-12.c: New.
* lib/target-supports.exp
  (check_effective_target_arm_cmse_ok): New.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7c3ad8984d8032b984b0acb21e9c05fdcc40579a..5d42d00819e74ff1c5b665f36e1b6f4033fe357d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -323,7 +323,7 @@ arc*-*-*)
 arm*-*-*)
 	cpu_type=arm
 	extra_objs="arm-builtins.o aarch-common.o"
-	extra_headers="mmintrin.h arm_neon.h arm_acle.h"
+	extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_cmse.h"
 	target_type_format_char='%'
 	c_target_objs="arm-c.o"
 	cxx_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index be46521c9eaea54f9ad78a92874567589289dbdf..0e523959551cc3b1da31411ccdd1105b830db845 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -63,11 +63,11 @@ ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
 	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
 			 FL2_FOR_ARCH8_1A))
 ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,
-	 ARM_FSET_MAKE_CPU1 (			  FL_FOR_ARCH8M_BASE))
+	 ARM_FSET_MAKE (			  FL_FOR_ARCH8M_BASE, FL2_CMSE))
 ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
-	 ARM_FSET_MAKE_CPU1(FL_CO_PROC |	  FL_FOR_ARCH8M_MAIN))
+	 ARM_FSET_MAKE (FL_CO_PROC |		  FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("armv8-m.main+dsp", cortexm7, 8M_MAIN,
-	 ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN))
+	 ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("iwmmxt",  iwmmxt, 5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
 
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 195905fa25b36cd35fe9bc843c695333892106be..862bd095cb1c34626872194a03892ff915d18916 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -76,6 +76,14 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  if (arm_arch8 && !arm_arch_notm)
+{
+  if (arm_arch_cmse && use_cmse)
+	builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);
+  else
+	builtin_define ("__ARM_FEATURE_CMSE");
+}
+
   if (TARGET_ARM_FEATURE_LDREX)
 

[PING] Re: [RFC][PATCH, ARM 4/8] ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxns return

[Andre Vieira (lists)]

On 26/12/15 01:52, Thomas Preud'homme wrote:

[Sending on behalf of Andre Vieira]

Hello,

This patch extends support for the ARMv8-M Security Extensions 
'cmse_nonsecure_entry' attribute in two ways:

1) Generate two labels for the function, the regular function name and one with 
the function's name appended to '__acle_se_', this will trigger the linker to 
create a secure gateway veneer for this entry function.
2) Return from cmse_nonsecure_entry marked functions using bxns.

See Section 5.4 of ARM®v8-M Security Extensions 
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).


*** gcc/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc/config/arm/arm.c (use_return_insn): Change to return with  bxns
   when cmse_nonsecure_entry.
   (output_return_instruction): Likewise.
   (arm_output_function_prologue): Likewise.
   (thumb_pop): Likewise.
   (thumb_exit): Likewise.
   (arm_function_ok_for_sibcall): Disable sibcall for entry functions.
   (arm_asm_declare_function_name): New.
   (thumb1_cmse_nonsecure_entry_return): New.
 * gcc/config/arm/arm-protos.h (arm_asm_declare_function_name): New.
 * gcc/config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to
   use arm_asm_declare_function_name.

*** gcc/testsuite/ChangeLog ***
2015-10-27  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse-2.c: New.
 * gcc.target/arm/cmse/cmse-4.c: New.


diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
85dca057d63544c672188db39b05a33b1be10915..9ee8c333046d9a5bb0487f7b710a5aff42d2
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -31,6 +31,7 @@ extern int arm_volatile_func (void);
  extern void arm_expand_prologue (void);
  extern void arm_expand_epilogue (bool);
  extern void arm_declare_function_name (FILE *, const char *, tree);
+extern void arm_asm_declare_function_name (FILE *, const char *, tree);
  extern void thumb2_expand_return (bool);
  extern const char *arm_strip_name_encoding (const char *);
  extern void arm_asm_output_labelref (FILE *, const char *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
5b9e51b10e91eee64e3383c1ed50269c3e6cf24c..e530b772e3cc053c16421a2a2861d815d53ebb01
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3795,6 +3795,11 @@ use_return_insn (int iscond, rtx sibling)
return 0;
  }

+  /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
+ several instructions if anything needs to be popped.  */
+  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
+return 0;
+
/* If there are saved registers but the LR isn't saved, then we need
   two instructions for the return.  */
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
@@ -6820,6 +6825,11 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
if (IS_INTERRUPT (func_type))
  return false;

+  /* ARMv8-M non-secure entry functions need to return with bxns which is only
+ generated for entry functions themselves.  */
+  if (IS_CMSE_ENTRY (arm_current_func_type ()))
+return false;
+
if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl
  {
/* Check that the return value locations are the same.  For
@@ -19607,6 +19617,7 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
 (e.g. interworking) then we can load the return address
 directly into the PC.  Otherwise we must load it into LR.  */
if (really_return
+ && !IS_CMSE_ENTRY (func_type)
  && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
return_reg = reg_names[PC_REGNUM];
else
@@ -19742,8 +19753,12 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
  break;

default:
+ if (IS_CMSE_ENTRY (func_type))
+   {
+ snprintf (instr, sizeof (instr), "bxns%s\t%%|lr", conditional);
+   }
  /* Use bx if it's available.  */
- if (arm_arch5 || arm_arch4t)
+ else if (arm_arch5 || arm_arch4t)
sprintf (instr, "bx%s\t%%|lr", conditional);
  else
sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
@@ -19756,6 +19771,42 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
return "";
  }

+/* Output in FILE asm statements needed to declare the NAME of the function
+   defined by its DECL node.  */
+
+void
+arm_asm_declare_function_name (FILE *file, const char *name, tree decl)
+{
+  size_t cmse_name_len;
+  char *cmse_name = 0;
+  char cmse_prefix[] = "__acle_se_";
+
+  if (use_cmse && lookup_attribute ("cmse_nonsecure_entry",
+   

Re: [Ping^2][PATCH][GCC-5] Fix "#pragma GCC pop_options" warning.

[Andre Vieira (lists)]

On 15/02/16 10:33, Andre Vieira (lists) wrote:

On 18/01/16 11:04, Andre Vieira (lists) wrote:

Hi there,

Can we have the "#pragma GCC pop_options" fix backported to GCC-5?

Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
and was committed in r228794.

The same patch applies cleanly to gcc-5, which would otherwise not be
able to use this pragma even though the support is there.

Cheers,
Andre



Ping.


Ping.

Re: [PING^2][PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

Ping.

On 27/10/15 17:03, Andre Vieira wrote:

Ping.

BR,
Andre

On 13/10/15 18:01, Andre Vieira wrote:

This patch ports the aeabi_idiv routine from Linaro Cortex-Strings
(https://git.linaro.org/toolchain/cortex-strings.git), which was
contributed by ARM under Free BSD license.

The new aeabi_idiv routine is used to replace the one in
libgcc/config/arm/lib1funcs.S. This replacement happens within the
Thumb1 wrapper. The new routine is under LGPLv3 license.

The main advantage of this version is that it can improve the
performance of the aeabi_idiv function for Thumb1. This solution will
also increase the code size. So it will only be used if
__OPTIMIZE_SIZE__ is not defined.

Make check passed for armv6-m.

libgcc/ChangeLog:
2015-08-10  Hale Wang  
  Andre Vieira  

* config/arm/lib1funcs.S: Add new wrapper.

Re: [RFC][PATCH, ARM 7/8] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call]

[Andre Vieira (lists)]

On 16/01/16 14:49, Senthil Kumar Selvaraj wrote:

User-agent: mu4e 0.9.13; emacs 24.5.1

Hi,

Apologies for the bad posting style (I don't have the
original email handy), but shouldn't _gnu_cmse_nonsecure_call be defined
with the .global directive in the below hunk (to make it visible when linking)?

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cm=
se_nonsecure_call.S
new file mode 100644
index ..bdc140f5bbe87c6599db225b1b9=
b7bbc7d606710
--- /dev/null
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -0,0 +1,87 @@
+.syntax unified
+.thumb
+__gnu_cmse_nonsecure_call:

Right now, it ends up as a local symbol, and compiling and linking a
program with cmse_nonsecure_call (say cmse-11.c), results in a linker
error - the linker doesn't find the symbol even if it is present in
libgcc.a. I found the problem that way - dumping symbols for my variant
of libgcc.a and grepping showed the symbol to be available but local.

Regards
Senthil


Hi Senthil,

Thanks for catching that!

Cheers,
Andre

[Ping][PATCH][GCC-5] Fix "#pragma GCC pop_options" warning.

[Andre Vieira (lists)]

On 18/01/16 11:04, Andre Vieira (lists) wrote:

Hi there,

Can we have the "#pragma GCC pop_options" fix backported to GCC-5?

Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
and was committed in r228794.

The same patch applies cleanly to gcc-5, which would otherwise not be
able to use this pragma even though the support is there.

Cheers,
Andre



Ping.

[PATCH][ARM] Make Cortex-R8 use ARMv7 multilib

[Andre Vieira (lists)]

Hi there,

This patch adds cortex-r8 to the list of cores using the armv7 multilib.

This patch is based on Thomas' multilib patch series:
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01584.html
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01585.html
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01586.html

Is this OK?

2016-03-09  Andre Vieira  

  * gcc/config/arm/t-baremetal: Add cortex-r8.
diff --git a/gcc/config/arm/t-baremetal b/gcc/config/arm/t-baremetal
index 
ffd29815e6ec22c747e77747ed9b69e0ae21b63a..6794b1cc02e73ca5b53a6350f09f9ae3afd171dc
 100644
--- a/gcc/config/arm/t-baremetal
+++ b/gcc/config/arm/t-baremetal
@@ -33,6 +33,7 @@ MULTILIB_MATCHES  += march?armv7=mcpu?cortex-r4
 MULTILIB_MATCHES  += march?armv7=mcpu?cortex-r4f
 MULTILIB_MATCHES  += march?armv7=mcpu?cortex-r5
 MULTILIB_MATCHES  += march?armv7=mcpu?cortex-r7
+MULTILIB_MATCHES  += march?armv7=mcpu?cortex-r8
 MULTILIB_MATCHES  += march?armv7=mcpu?generic-armv7-a
 MULTILIB_MATCHES  += march?armv7=mcpu?cortex-a5
 MULTILIB_MATCHES  += march?armv7=mcpu?cortex-a7

Re: [PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

On 08/03/16 14:56, Kyrill Tkachov wrote:
> Hi Andre,
> 
> On 08/03/16 11:05, Andre Vieira (lists) wrote:
>> On 03/03/16 11:28, Kyrill Tkachov wrote:
>>> Hi Andre,
>>>
>>> On 02/03/16 12:21, Andre Vieira (lists) wrote:
>>>> Hi,
>>>>
>>>> Tests used to check for "r8" which will not work because cortex-r8
>>>> string is now included in the assembly. Fixed by checking for
>>>> "[^\-]r8".
>>>>
>>>> Is this Ok?
>>>>
>>>> Cheers,
>>>> Andre
>>>>
>>>> gcc/testsuite/ChangeLog:
>>>>
>>>> 2016-03-02  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>
>>>>* gcc.target/arm/pr45701-1.c: Change assembler scan to not
>>>>trigger for cortex-r8, when scanning for register r8.
>>>>* gcc.target/arm/pr45701-2.c: Likewise.
>>> Ok.
>>> Thanks,
>>> Kyrill
>>>
>> Thomas commited on my behalf at revision r234040.
>>
>> Had to rebase arm-tune.md and invoke.texi, these were all obvious
>> changes.
> 
> I'm seeing a DejaGNU error while testing
> RUNTESTFLAGS="arm.exp=pr45701-*.c":
> ERROR: (DejaGnu) proc "^-" does not exist.
> The error code is NONE
> The info on the error is:
> invalid command name "^-"
> while executing
> "::tcl_unknown ^-"
> ("uplevel" body line 1)
> invoked from within
> "uplevel 1 ::tcl_unknown $args"
> 
> That's due to the scan-assembler-not test:
> /* { dg-final { scan-assembler-not "[^\-]r8" } } */
> 
> The '[' and ']' need to be escaped by a backslash.
> Can you please post a patch to add the escapes.
> Sorry for missing this in the original review...
> 
> Kyrill
> 
>> Cheers,
>> Andre
>>
> 
Hi there,

Sorry for missing those too.

2016-03-09 Andre Vieira <andre.simoesdiasvie...@arm.com>

* gcc.target/arm/pr45701-1.c: Escape brackets.
* gcc.target/arm/pr45701-2.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/arm/pr45701-1.c 
b/gcc/testsuite/gcc.target/arm/pr45701-1.c
index 
a5db56fc6f2f3cb334b514a72ff500308c361832..01db15abfd03eb916676e39b5db14a39596cbad6
 100644
--- a/gcc/testsuite/gcc.target/arm/pr45701-1.c
+++ b/gcc/testsuite/gcc.target/arm/pr45701-1.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
 /* { dg-options "-mthumb -Os" }  */
 /* { dg-final { scan-assembler "push\t\{r3" } } */
-/* { dg-final { scan-assembler-not "[^\-]r8" } } */
+/* { dg-final { scan-assembler-not "\[^\-\]r8" } } */
 
 extern int hist_verify;
 extern int a1;
diff --git a/gcc/testsuite/gcc.target/arm/pr45701-2.c 
b/gcc/testsuite/gcc.target/arm/pr45701-2.c
index 
765981b90db38f534e13e9e8a8f538c8408f798a..ce66d7509d1769fb96bb05e0d274be27e28a7188
 100644
--- a/gcc/testsuite/gcc.target/arm/pr45701-2.c
+++ b/gcc/testsuite/gcc.target/arm/pr45701-2.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
 /* { dg-options "-mthumb -Os" }  */
 /* { dg-final { scan-assembler "push\t\{r3" } } */
-/* { dg-final { scan-assembler-not "[^\-]r8" } } */
+/* { dg-final { scan-assembler-not "\[^\-\]r8" } } */
 
 extern int hist_verify;
 extern int a1;

Re: [PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

On 09/03/16 17:03, Mike Stump wrote:
> On Mar 9, 2016, at 8:57 AM, Andre Vieira (lists) 
> <andre.simoesdiasvie...@arm.com> wrote:
>>> I'm seeing a DejaGNU error while testing
>>> RUNTESTFLAGS="arm.exp=pr45701-*.c":
>>> ERROR: (DejaGnu) proc "^-" does not exist.
> 
>> 2016-03-09 Andre Vieira <andre.simoesdiasvie...@arm.com>
>>
>> * gcc.target/arm/pr45701-1.c: Escape brackets.
> 
> Be sure to run test cases with dejagnu before check in.
> 
Hi Mike,

I did run them but apparently tcl errors dont appear as a FAIL and I
failed to spot the tcl error message. Ill keep an eye out for those in
the future.

Cheers,
Andre

[arm-embedded][PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

On 02/03/16 12:21, Andre Vieira (lists) wrote:
> Hi,
> 
> Tests used to check for "r8" which will not work because cortex-r8
> string is now included in the assembly. Fixed by checking for "[^\-]r8".
> 
> Is this Ok?
> 
> Cheers,
> Andre
> 
> gcc/testsuite/ChangeLog:
> 
> 2016-03-02  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> 
>  * gcc.target/arm/pr45701-1.c: Change assembler scan to not
>  trigger for cortex-r8, when scanning for register r8.
>  * gcc.target/arm/pr45701-2.c: Likewise.
> 
Hi,

We decided to apply the following patch to the ARM embedded 5 branch.

Best regards,
Andre

[arm-embedded][PATCH][ARM] Make Cortex-R8 use ARMv7 multilib

[Andre Vieira (lists)]

On 09/03/16 16:55, Andre Vieira (lists) wrote:
> Hi there,
> 
> This patch adds cortex-r8 to the list of cores using the armv7 multilib.
> 
> This patch is based on Thomas' multilib patch series:
> https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01584.html
> https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01585.html
> https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01586.html
> 
> Is this OK?
> 
> 2016-03-09  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> 
>   * gcc/config/arm/t-baremetal: Add cortex-r8.
> 
Hi,

We decided to apply the following patch to the ARM embedded 5 branch.

Best regards,
Andre

[arm-embedded][PATCH 1/2][GCC][ARM] Add support for Cortex-R8

[Andre Vieira (lists)]

On 02/03/16 12:20, Andre Vieira (lists) wrote:
> 
> gcc/ChangeLog:
> 
> 2016-03-02  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> 
>  * config/arm/arm-cores.def (cortex-r8): New.
>  * config/arm/arm-tables.opt (cortex-r8): New.
>  * config/arm/arm-tune.md: Regenerate.
>  * gcc/doc/invoke.texi: Add cortex-r8 to list of cpu values.
> 
Hi,

We decided to apply the following patch to the ARM embedded 5 branch.

Best regards,
Andre

[arm-embedded][PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

On 09/03/16 16:57, Andre Vieira (lists) wrote:
> On 08/03/16 14:56, Kyrill Tkachov wrote:
>> Hi Andre,
>>
>> On 08/03/16 11:05, Andre Vieira (lists) wrote:
>>> On 03/03/16 11:28, Kyrill Tkachov wrote:
>>>> Hi Andre,
>>>>
>>>> On 02/03/16 12:21, Andre Vieira (lists) wrote:
>>>>> Hi,
>>>>>
>>>>> Tests used to check for "r8" which will not work because cortex-r8
>>>>> string is now included in the assembly. Fixed by checking for
>>>>> "[^\-]r8".
>>>>>
>>>>> Is this Ok?
>>>>>
>>>>> Cheers,
>>>>> Andre
>>>>>
>>>>> gcc/testsuite/ChangeLog:
>>>>>
>>>>> 2016-03-02  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>>
>>>>>* gcc.target/arm/pr45701-1.c: Change assembler scan to not
>>>>>trigger for cortex-r8, when scanning for register r8.
>>>>>* gcc.target/arm/pr45701-2.c: Likewise.
>>>> Ok.
>>>> Thanks,
>>>> Kyrill
>>>>
>>> Thomas commited on my behalf at revision r234040.
>>>
>>> Had to rebase arm-tune.md and invoke.texi, these were all obvious
>>> changes.
>>
>> I'm seeing a DejaGNU error while testing
>> RUNTESTFLAGS="arm.exp=pr45701-*.c":
>> ERROR: (DejaGnu) proc "^-" does not exist.
>> The error code is NONE
>> The info on the error is:
>> invalid command name "^-"
>> while executing
>> "::tcl_unknown ^-"
>> ("uplevel" body line 1)
>> invoked from within
>> "uplevel 1 ::tcl_unknown $args"
>>
>> That's due to the scan-assembler-not test:
>> /* { dg-final { scan-assembler-not "[^\-]r8" } } */
>>
>> The '[' and ']' need to be escaped by a backslash.
>> Can you please post a patch to add the escapes.
>> Sorry for missing this in the original review...
>>
>> Kyrill
>>
>>> Cheers,
>>> Andre
>>>
>>
> Hi there,
> 
> Sorry for missing those too.
> 
> 2016-03-09 Andre Vieira <andre.simoesdiasvie...@arm.com>
> 
> * gcc.target/arm/pr45701-1.c: Escape brackets.
> * gcc.target/arm/pr45701-2.c: Likewise.
> 
Hi,

We decided to apply the following patch to the ARM embedded 5 branch.

Best regards,
Andre

Re: [PATCH][ARM][testsuite][committed] Do not override -mcpu in no-volatile-in-it.c

[Andre Vieira (lists)]

On 16/07/15 16:31, Kyrill Tkachov wrote:
> Hi all,
> 
> This scan-assembler test was failing for me when testing with an
> explicit /-march=armv7-a variant because
> it clashed with the -mcpu=cortex-m7 and overrode it.
> 
> This patch skips the test if the user forces an incompatible -march or
> -mcpu option.
> The test now appears as UNSUPPORTED in these conditions and PASSes
> normally.
> 
> Applied as obvious with r225892.
> 
> Thanks,
> Kyrill
> 
> 2015-07-16  Kyrylo Tkachov  
> 
> * gcc.target/arm/no-volatile-in-it.c: Skip if -mcpu is overriden.

OK to backport this to gcc-5-branch?

Cheers,
Andre

[Patch testsuite obvious][gcc-5] g++.dg/ext/pr57735.C should not run if the testsuite is explicitly passing -mfloat-abi=hard

[Andre Vieira (lists)]

On 09/06/15 14:07, James Greenhalgh wrote:
> 
> Hi,
> 
> g++.dg/ext/pr57735.C is failing for test runs which explicitly pass
> -mfloat-abi=hard. Looking at the test, it seems the best fix would be
> to check before adding -mfloat-abi=soft that we are not testing some other
> float-abi. We also fail to check that it is OK to add -march=armv5te
> and -marm.
> 
> Fixed using the same mechanisms we use elsewhere in the gcc.target/arm/
> tests with the attached, applied as obvious as revision 224280.
> 
> Thanks,
> James
> 
> ---
> gcc/testsuite/
> 
> 2015-06-09  James Greenhalgh  
> 
>   * g++.dg/ext/pr57735.C: Do not override -mfloat-abi directives
>   passed by the testsuite driver.
> 

Thomas committed this on my behalf to gcc-5-branch as obvious as
revision r234326.

Cheers,
Andre

Re: [RFC][PATCH v2, ARM 5/8] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

On 29/01/16 17:07, Andre Vieira (lists) wrote:
> On 26/12/15 01:54, Thomas Preud'homme wrote:
>> [Sending on behalf of Andre Vieira]
>>
>> Hello,
>>
>> This patch extends support for the ARMv8-M Security Extensions
>> 'cmse_nonsecure_entry' attribute to safeguard against leak of
>> information through unbanked registers.
>>
>> When returning from a nonsecure entry function we clear all
>> caller-saved registers that are not used to pass return values, by
>> writing either the LR, in case of general purpose registers, or the
>> value 0, in case of FP registers. We use the LR to write to APSR and
>> FPSCR too. We currently only support 32 FP registers as in we only
>> clear D0-D7.
>> We currently do not support entry functions that pass arguments or
>> return variables on the stack and we diagnose this. This patch relies
>> on the existing code to make sure callee-saved registers used in
>> cmse_nonsecure_entry functions are saved and restored thus retaining
>> their nonsecure mode value, this should be happening already as it is
>> required by AAPCS.
>>
>>
>> *** gcc/ChangeLog ***
>> 2015-10-27  Andre Vieira<andre.simoesdiasvie...@arm.com>
>>  Thomas Preud'homme  <thomas.preudho...@arm.com>
>>
>>  * gcc/config/arm/arm.c (output_return_instruction): Clear
>>registers.
>>(thumb2_expand_return): Likewise.
>>(thumb1_expand_epilogue): Likewise.
>>(arm_expand_epilogue): Likewise.
>>(cmse_nonsecure_entry_clear_before_return): New.
>>  * gcc/config/arm/arm.h (TARGET_DSP_ADD): New macro define.
>>  * gcc/config/arm/thumb1.md (*epilogue_insns): Change length
>> attribute.
>>  * gcc/config/arm/thumb2.md (*thumb2_return): Likewise.
>>
>> *** gcc/testsuite/ChangeLog ***
>> 2015-10-27  Andre Vieira<andre.simoesdiasvie...@arm.com>
>>  Thomas Preud'homme  <thomas.preudho...@arm.com>
>>
>>  * gcc.target/arm/cmse/cmse.exp: Test different multilibs
>> separate.
>>  * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers
>> are cleared.
>>  * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
>>  * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
>>  * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
>>  * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
>>  * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.
>>
>>
>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
>> index
>> f12e3c93bbe24b10ed8eee6687161826773ef649..b06e0586a3da50f57645bda13629bc4dbd3d53b7
>> 100644
>> --- a/gcc/config/arm/arm.h
>> +++ b/gcc/config/arm/arm.h
>> @@ -230,6 +230,9 @@ extern void
>> (*arm_lang_output_object_attributes_hook)(void);
>>   /* Integer SIMD instructions, and extend-accumulate instructions.  */
>>   #define TARGET_INT_SIMD \
>> (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
>> +/* Parallel addition and subtraction instructions.  */
>> +#define TARGET_DSP_ADD \
>> +  (TARGET_ARM_ARCH >= 6 && (arm_arch_notm || arm_arch7em))
>>
>>   /* Should MOVW/MOVT be used in preference to a constant pool.  */
>>   #define TARGET_USE_MOVT \
>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>> index
>> e530b772e3cc053c16421a2a2861d815d53ebb01..0700478ca38307f35d0cb01f83ea182802ba28fa
>> 100644
>> --- a/gcc/config/arm/arm.c
>> +++ b/gcc/config/arm/arm.c
>> @@ -19755,6 +19755,24 @@ output_return_instruction (rtx operand, bool
>> really_return, bool reverse,
>>   default:
>> if (IS_CMSE_ENTRY (func_type))
>>   {
>> +  char flags[12] = "APSR_nzcvq";
>> +  /* Check if we have to clear the 'GE bits' which is only
>> used if
>> + parallel add and subtraction instructions are available.  */
>> +  if (TARGET_DSP_ADD)
>> +{
>> +  /* If so also clear the ge flags.  */
>> +  flags[10] = 'g';
>> +  flags[11] = '\0';
>> +}
>> +  snprintf (instr, sizeof (instr),  "msr%s\t%s, %%|lr",
>> conditional,
>> +flags);
>> +  output_asm_insn (instr, & operand);
>> +  if (TARGET_HARD_FLOAT && TARGET_VFP)
>> +{
>> +  snprintf (instr, sizeof (instr), "vmsr%s\tfpscr, %%|lr",
>> +conditional);
>> +  out

Re: [RFC][PATCH, ARM 0/8] ARMv8-M Security Extensions

[Andre Vieira (lists)]

On 26/12/15 01:39, Thomas Preud'homme wrote:
> [Sending on behalf of Andre Vieira]
> 
> Hello,
> 
> This patch series aims at implementing an alpha status support for ARMv8-M's 
> Security Extensions. It is only posted as RFC at this stage. You can find the 
> specification of ARMV8-M Security Extensions in: ARM®v8-M Security 
> Extensions: Requirements on Development Tools 
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
> 
> We currently:
> - do not support passing arguments or returning on the stack for 
> cmse_nonsecure_{call,entry} functions,
> - do not guarantee padding bits are cleared for arguments or return variables 
> of cmse_nonsecure_{call,entry} functions,
> - only test Security Extensions for -mfpu=fpv5-d16 and fpv5-sp-d16 and only 
> support single and double precision FPU's with d16.
> 
> 
> Andre Vieira (8):
>  Add support for ARMv8-M's Security Extensions flag and intrinsics
>  Add RTL patterns for thumb1 push/pop
>  Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute
>  ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxns 
> return
>  ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers
>  Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute
>  ARMv8-M Security Extension's cmse_nonsecure_call: use 
> __gnu_cmse_nonsecure_call
>  Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic
> 
> 
> Cheers,
> 
> Andre
> 

Hi there, with the second version of the patch to clear registers when
returning from cmse_nonsecure_entry functions we guarantee that padding
bits are cleared when returning from a cmse_nonsecure_entry function.
However, we still do not guarantee this happens for when passing
compound types as arguments to cmse_nonsecure_call's.

Furthermore patch 2/8 has been dropped since it was no longer relevant.

Andre Vieira (8):
 Add support for ARMv8-M's Security Extensions flag and intrinsics
 Add RTL patterns for thumb1 push/pop (DROPPED)
 Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute
 ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and
bxns return
 ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers
 Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute
 ARMv8-M Security Extension's cmse_nonsecure_call: use
__gnu_cmse_nonsecure_call
 Added support for ARMV8-M Security Extension cmse_nonsecure_caller
intrinsic


Cheers,
Andre

[PATCH 3/8, GCC, V8M][arm-embedded] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Andre Vieira (lists)]

Hi,

Applied https://gcc.gnu.org/ml/gcc-patches/2015-12/msg02150.html on
embedded-5-branch using the included patch at revision r234583.

*** gcc ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
(arm_attribute_table): Added cmse_nonsecure_entry
(arm_compute_func_type): Handle cmse_nonsecure_entry.
(cmse_func_args_or_return_in_stack): New.
(arm_handle_cmse_nonsecure_entry): New.
* config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
(IS_CMSE_ENTRY): Likewise.

*** gcc/testsuite ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: New.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
7574064936e5217c8e553e7ab744cbe9320346d2..3467a9ea3d3c59b0b41a59f22f14f277153cff0e
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1510,6 +1510,7 @@ do {  
  \
 #define ARM_FT_VOLATILE(1 << 4) /* Does not return.  */
 #define ARM_FT_NESTED  (1 << 5) /* Embedded inside another func.  */
 #define ARM_FT_STACKALIGN  (1 << 6) /* Called with misaligned stack.  */
+#define ARM_FT_CMSE_ENTRY  (1 << 7) /* ARMv8-M non-secure entry function.  
*/
 
 /* Some macros to test these flags.  */
 #define ARM_FUNC_TYPE(t)   (t & ARM_FT_TYPE_MASK)
@@ -1518,6 +1519,7 @@ do {  
  \
 #define IS_NAKED(t)(t & ARM_FT_NAKED)
 #define IS_NESTED(t)   (t & ARM_FT_NESTED)
 #define IS_STACKALIGN(t)   (t & ARM_FT_STACKALIGN)
+#define IS_CMSE_ENTRY(t)   (t & ARM_FT_CMSE_ENTRY)
 
 
 /* Structure used to hold the function stack frame layout.  Offsets are
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
8c951490f0fa4eb5a5d14a1ca75a51bdbe03..d53d96e7e52cdcc3c2340d714d277e12a1ee07f6
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -167,6 +167,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
+static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -368,6 +369,9 @@ static const struct attribute_spec arm_attribute_table[] =
   { "notshared",0, 0, false, true, false, arm_handle_notshared_attribute,
 false },
 #endif
+  /* ARMv8-M Security Extensions support.  */
+  { "cmse_nonsecure_entry", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_entry, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -3354,6 +3358,9 @@ arm_compute_func_type (void)
   else
 type |= arm_isr_value (TREE_VALUE (a));
 
+  if (lookup_attribute ("cmse_nonsecure_entry", attr))
+type |= ARM_FT_CMSE_ENTRY;
+
   return type;
 }
 
@@ -6348,6 +6355,109 @@ arm_handle_notshared_attribute (tree *node,
 }
 #endif
 
+/* This function is used to check whether functions with attributes
+   cmse_nonsecure_call or cmse_nonsecure_entry use the stack to pass arguments
+   or return variables.  If the function does indeed use the stack this
+   function returns true and diagnoses this, otherwise it returns false.  */
+
+static bool
+cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
+
+  /* Error out if any argument is passed on the stack.  */
+  arm_init_cumulative_args (_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+{
+  rtx arg_rtx;
+  machine_mode arg_mode = TYPE_MODE (arg_type);
+
+  prev_arg_type = arg_type;
+  if (VOID_TYPE_P (arg_type))
+   continue;
+
+  if (!first_param)
+   arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
+  arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
+  if (!arg_rtx
+ || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
+   {
+ error ("%qE attribute not available to functions with arguments "
+"passed on the stack", name);
+ return true;
+   }
+  first_param = false;
+}
+
+  /* Error out for variadic functions since we cannot control how many
+ arguments will be passed and thus stack could be used.  stdarg_p () is not
+  

[PATCH v2, GCC, V8M 5/8][arm-embedded] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

Applied the patch in
https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01524.html on
embedded-5-branch at revision r234585.

Cheers,
Andre

[PATCH 8/8, GCC, V8M][arm-embedded] Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic

[Andre Vieira (lists)]

Hi,

Applied https://gcc.gnu.org/ml/gcc-patches/2015-12/msg02155.html on
embedded-5-branch using included patch at revision r234589.

*** gcc/ ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* config/arm/arm-builtins.c (arm_builtins): Define
ARM_BUILTIN_CMSE_NONSECURE_CALLER.
(bdesc_2arg): Add line for cmse_nonsecure_caller.
(arm_init_builtins): Init for cmse_nonsecure_caller.
(arm_expand_builtin): Handle cmse_nonsecure_caller.
* config/arm/arm_cmse.h (cmse_nonsecure_caller): New.

*** gcc/testsuite/ ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-1.c: Add test for
cmse_nonsecure_caller.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
7a451133f861a476a7cad359bd0374e3c4f06f35..277046fe6a6d517d0b33797e45f5535d1d59c11a
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -508,6 +508,8 @@ enum arm_builtins
   ARM_BUILTIN_GET_FPSCR,
   ARM_BUILTIN_SET_FPSCR,
 
+  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -1224,6 +1226,10 @@ static const struct builtin_description bdesc_2arg[] =
   FP_BUILTIN (set_fpscr, SET_FPSCR)
 #undef FP_BUILTIN
 
+  {FL_CMSE, CODE_FOR_andsi3,
+   "__builtin_arm_cmse_nonsecure_caller", ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+   UNKNOWN, 0},
+
 #define CRC32_BUILTIN(L, U) \
   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
UNKNOWN, 0},
@@ -1753,6 +1759,17 @@ arm_init_builtins (void)
= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
 }
+
+  if (arm_arch_cmse)
+{
+  tree ftype_cmse_nonsecure_caller
+   = build_function_type_list (unsigned_type_node, NULL);
+  arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
+   = add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
+   ftype_cmse_nonsecure_caller,
+   ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
+   NULL, NULL_TREE);
+}
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -2272,6 +2289,14 @@ arm_expand_builtin (tree exp,
   emit_insn (pat);
   return target;
 
+case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
+  icode = CODE_FOR_andsi3;
+  target = gen_reg_rtx (SImode);
+  op0 = arm_return_addr (0, NULL_RTX);
+  pat = GEN_FCN (icode) (target, op0, const1_rtx);
+  emit_insn (pat);
+  return target;
+
 case ARM_BUILTIN_TEXTRMSB:
 case ARM_BUILTIN_TEXTRMUB:
 case ARM_BUILTIN_TEXTRMSH:
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c 
b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
index 
1c3d4e9e934f4b1166d4d98383cf4ae8c3515117..ccecf396d3cda76536537b4d146bbb5f70589fd5
 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
@@ -66,3 +66,32 @@ int foo (char * p)
 /* { dg-final { scan-assembler-times "ttat " 2 } } */
 /* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
 /* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
+
+typedef int (*int_ret_funcptr_t) (void);
+typedef int __attribute__ ((cmse_nonsecure_call)) (*int_ret_nsfuncptr_t) 
(void);
+
+int __attribute__ ((cmse_nonsecure_entry))
+baz (void)
+{
+  return cmse_nonsecure_caller ();
+}
+
+int __attribute__ ((cmse_nonsecure_entry))
+qux (int_ret_funcptr_t int_ret_funcptr)
+{
+  int_ret_nsfuncptr_t int_ret_nsfunc_ptr;
+
+  if (cmse_is_nsfptr (int_ret_funcptr))
+{
+  int_ret_nsfunc_ptr = cmse_nsfptr_create (int_ret_funcptr);
+  return int_ret_nsfunc_ptr ();
+}
+  return 0;
+}
+/* { dg-final { scan-assembler "baz:" } } */
+/* { dg-final { scan-assembler "__acle_se_baz:" } } */
+/* { dg-final { scan-assembler-not "\tcmse_nonsecure_caller" } } */
+/* { dg-final { scan-rtl-dump "and.*reg.*const_int 1" expand } } */
+/* { dg-final { scan-assembler "bic" } } */
+/* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" } } */

[PATCH 6/8, GCC, V8M][arm-embedded] Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute

[Andre Vieira (lists)]

Hi,

Applied https://gcc.gnu.org/ml/gcc-patches/2015-12/msg02153.html on
embedded-5-branch using included patch at revision r234586.

*** gcc ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (gimplify.h): New include.
(arm_handle_cmse_nonsecure_call): New.
(arm_attribute_table): Added cmse_nonsecure_call.

*** gcc/testsuite ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: Add tests.
* gcc.target/arm/cmse/cmse-4.c: Add tests.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
d1be6eed1ac153903d50160f3b08d325187acf0b..d13bc2d49508863cf5b45a5f447a70fb468a115c
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -98,6 +98,7 @@
 #include "tm-constrs.h"
 #include "rtl-iter.h"
 #include "sched-int.h"
+#include "gimplify.h"
 
 /* Forward definitions of types.  */
 typedef struct minipool_nodeMnode;
@@ -168,6 +169,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
 static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
+static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -372,6 +374,8 @@ static const struct attribute_spec arm_attribute_table[] =
   /* ARMv8-M Security Extensions support.  */
   { "cmse_nonsecure_entry", 0, 0, true, false, false,
 arm_handle_cmse_nonsecure_entry, false },
+  { "cmse_nonsecure_call", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_call, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -6463,6 +6467,76 @@ arm_handle_cmse_nonsecure_entry (tree *node, tree name,
   return NULL_TREE;
 }
 
+
+/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
+   function will check whether the attribute is allowed here and will add the
+   attribute to the function type tree or otherwise issue a diagnose.  The
+   reason we check this at declaration time is to only allow the use of the
+   attribute with declartions of function pointers and not function
+   declartions.  */
+
+static tree
+arm_handle_cmse_nonsecure_call (tree *node, tree name,
+tree /* args */,
+int /* flags */,
+bool *no_add_attrs)
+{
+  tree decl = NULL_TREE;
+  tree type, fntype, main_variant;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}
+
+  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
+{
+  decl = *node;
+  type = TREE_TYPE (decl);
+}
+
+  if (!decl
+  || (!(TREE_CODE (type) == POINTER_TYPE
+   && TREE_CODE (TREE_TYPE (type)) == FUNCTION_TYPE)
+ && TREE_CODE (type) != FUNCTION_TYPE))
+{
+   warning (OPT_Wattributes, "%qE attribute only applies to base type of a 
"
+"function pointer", name);
+   *no_add_attrs = true;
+   return NULL_TREE;
+}
+
+  /* type is either a function pointer, when the attribute is used on a 
function
+   * pointer, or a function type when used in a typedef.  */
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+fntype = type;
+  else
+fntype = TREE_TYPE (type);
+
+  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
+
+  if (*no_add_attrs)
+return NULL_TREE;
+
+  /* Prevent tree's being shared among function types with and without
+ cmse_nonsecure_call attribute.  Do however make sure they keep the same
+ main_variant, this is required for correct DIE output.  */
+  main_variant = TYPE_MAIN_VARIANT (fntype);
+  fntype = build_distinct_type_copy (fntype);
+  TYPE_MAIN_VARIANT (fntype) = main_variant;
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+TREE_TYPE (decl) = fntype;
+  else
+TREE_TYPE (type) = fntype;
+
+  /* Construct a type attribute and add it to the function type.  */
+  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
+ TYPE_ATTRIBUTES (fntype));
+  TYPE_ATTRIBUTES (fntype) = attrs;
+  return NULL_TREE;
+}
+
 /* Return 0 if the attributes for two types are incompatible, 1 if they
are compatible, and 2 if they are nearly compatible (which causes a
warning to be generated).  */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-3.c 
b/gcc/testsuite/gcc.target/arm/cmse/cmse-3.c
index 
f806951e90256e8286d2d0f9467b51a73a522e2b..0fe6eff45d2884736ba7049ce4ed5b9785b1018d
 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-3.c
+++ 

[PATCH 7/8, GCC, V8M][arm-embedded] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call

[Andre Vieira (lists)]

Hi,

Applied https://gcc.gnu.org/ml/gcc-patches/2016-01/msg02334.html on
embedded-5-branch using the included patch at revision r234587.

*** gcc/ ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (detect_cmse_nonsecure_call): New.
(cmse_nonsecure_call_clear_caller_saved): New.
* config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
* config/arm/arm.md (call): Handle cmse_nonsecure_entry.
(call_value): Likewise.
(nonsecure_call_internal): New.
(nonsecure_call_value_internal): New.
* config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
(*nonsecure_call_value_reg_thumb1_v5): New.
* config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
(*nonsecure_call_value_reg_thumb2): New.
* config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.

*** libgcc/ ***
2016-03-30 Andre Vieira 
Thomas Preud'homme 

* config/arm/cmse_nonsecure_call.S: New.
* config/arm/t-arm: Compile cmse_nonsecure_call.S


*** gcc/testsuite/ ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/baseline/cmse-11.c: New.
* gcc.target/arm/cmse/baseline/cmse-13.c: New.
* gcc.target/arm/cmse/baseline/cmse-6.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
066e2318967e11f0eeba79ef80d990c149992426..27173fea25df0b56bef68656d5f0224c5b817fde
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -135,6 +135,7 @@ extern int arm_const_double_inline_cost (rtx);
 extern bool arm_const_double_by_parts (rtx);
 extern bool arm_const_double_by_immediates (rtx);
 extern void arm_emit_call_insn (rtx, rtx, bool);
+bool detect_cmse_nonsecure_call (tree);
 extern const char *output_call (rtx *);
 extern const char *output_call_mem (rtx *);
 void arm_emit_movpair (rtx, rtx);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
d13bc2d49508863cf5b45a5f447a70fb468a115c..ec303e871f60485d06e35308b98154c1089bf330
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17415,6 +17415,129 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT 
address, int do_pushes)
   return;
 }
 
+/* Saves callee saved registers, clears callee saved registers and caller saved
+   registers not used to pass arguments before a cmse_nonsecure_call.  And
+   restores the callee saved registers after.  */
+
+static void
+cmse_nonsecure_call_clear_caller_saved (void)
+{
+  basic_block bb;
+
+  FOR_EACH_BB_FN (bb, cfun)
+{
+  rtx_insn *insn;
+
+  FOR_BB_INSNS (bb, insn)
+   {
+ uint64_t to_clear_mask, float_mask;
+ rtx_insn *seq;
+ rtx pat, call, unspec, link, reg, cleared_reg, tmp;
+ unsigned int regno, maxregno;
+ rtx address;
+
+ if (!NONDEBUG_INSN_P (insn))
+   continue;
+
+ if (!CALL_P (insn))
+   continue;
+
+ pat = PATTERN (insn);
+ gcc_assert (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 0);
+ call = XVECEXP (pat, 0, 0);
+
+ /* Get the real call RTX if the insn sets a value, ie. returns.  */
+ if (GET_CODE (call) == SET)
+ call = SET_SRC (call);
+
+ /* Check if it is a cmse_nonsecure_call.  */
+ unspec = XEXP (call, 0);
+ if (GET_CODE (unspec) != UNSPEC
+ || XINT (unspec, 1) != UNSPEC_NONSECURE_MEM)
+   continue;
+
+ /* Determine the caller-saved registers we need to clear.  */
+ to_clear_mask = (1LL << (NUM_ARG_REGS)) - 1;
+ maxregno = NUM_ARG_REGS - 1;
+ if (TARGET_HARD_FLOAT && TARGET_VFP)
+   {
+ float_mask = (1LL << (D7_VFP_REGNUM + 1)) - 1;
+ float_mask &= ~((1LL << FIRST_VFP_REGNUM) - 1);
+ to_clear_mask |= float_mask;
+ maxregno = D7_VFP_REGNUM;
+   }
+
+ /* Make sure the register 

[PATCHv2 1/8, GCC, V8M][arm-embedded] Add support for ARMv8-M's Security Extensions flag and intrinsics

[Andre Vieira (lists)]

Hi there,

Applied https://gcc.gnu.org/ml/gcc-patches/2015-12/msg02148.html on
embedded-5-branch using the included patch at revision r234582.


Cheers,
Andre

*** gcc ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* config.gcc (extra_headers): Added arm_cmse.h.
* config/arm/arm-arches.def (armv8-m.base): Add FL_CMSE.
(armv8-m.main): Likewise.
(armv8-m.main+dsp): Likewise.
* config/arm/arm-protos.h (arm_is_constant_pool_ref): Define
FL_CMSE.
* config/arm.c (arm_arch_cmse): New.
(arm_option_override): New error for unsupported cmse target.
* config/arm/arm.h (arm_arch_cmse): New.
(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
* config/arm/arm.opt (mcmse): New.
* doc/invoke.texi (ARM Options): Add -mcmse.
* doc/extend.texi (ACLE): Add CMSE.
* config/arm/arm_cmse.h: New file.

*** libgcc ***
2016-03-30 Andre Vieira 
Thomas Preud'homme 

* config/arm/cmse.c: Likewise.
* config/arm/t-arm (HAVE_CMSE): New.


*** gcc/testsuite ***
2016-03-30  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: New.
* gcc.target/arm/cmse/cmse-1.c: New.
* gcc.target/arm/cmse/cmse-12.c: New.
* lib/target-supports.exp
(check_effective_target_arm_cmse_ok): New.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 
9ee1024bd4d5f92d5dd28e763d37ee8324a7..4ec62db49f13642142b932d36f444f5ec9c74fd2
 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -319,7 +319,7 @@ arc*-*-*)
 arm*-*-*)
cpu_type=arm
extra_objs="arm-builtins.o aarch-common.o"
-   extra_headers="mmintrin.h arm_neon.h arm_acle.h"
+   extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_cmse.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
cxx_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 
d44179f290134eb2ec7894b47aa5ccb74b42..8a7d8a3a3895aaf07a9b7e3c2f231357f8c81e21
 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -56,8 +56,8 @@ ARM_ARCH("armv7-m", cortexm3, 7M,  FL_CO_PROC | 
FL_FOR_ARCH7M)
 ARM_ARCH("armv7e-m", cortexm4,  7EM, FL_CO_PROC |FL_FOR_ARCH7EM)
 ARM_ARCH("armv8-a", cortexa53,  8A,  FL_CO_PROC | FL_FOR_ARCH8A)
 ARM_ARCH("armv8-a+crc",cortexa53, 8A,FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A)
-ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,  
FL_FOR_ARCH8M_BASE)
-ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN, FL_CO_PROC |  
FL_FOR_ARCH8M_MAIN)
-ARM_ARCH("armv8-m.main+dsp",cortexm7,8M_MAIN,FL_CO_PROC|FL_ARCH7EM|FL_FOR_ARCH8M_MAIN)
+ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,  
FL_FOR_ARCH8M_BASE |  FL_CMSE)
+ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN, FL_CO_PROC |  
FL_FOR_ARCH8M_MAIN | FL_CMSE)
+ARM_ARCH("armv8-m.main+dsp",cortexm7,8M_MAIN,FL_CO_PROC|FL_ARCH7EM|FL_FOR_ARCH8M_MAIN
 |FL_CMSE)
 ARM_ARCH("iwmmxt",  iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | 
FL_XSCALE | FL_IWMMXT)
 ARM_ARCH("iwmmxt2", iwmmxt2,5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | 
FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
f48366b2a77f59f91d339358912746f45de55a63..05acdfada28c619102059959bdcfa2a8223524ec
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -368,6 +368,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 
 #define FL_IWMMXT (1 << 29)  /* XScale v2 or "Intel Wireless 
MMX technology".  */
 #define FL_IWMMXT2(1 << 30)   /* "Intel Wireless MMX2 technology".  */
+#define FL_CMSE  (1 << 31)   /* ARMv8-M Security Extensions.  
*/
 
 /* Flags that only effect tuning, not available instructions.  */
 #define FL_TUNE(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
d8d3ba5cba9807070989350644868fd88a98b4dc..7574064936e5217c8e553e7ab744cbe9320346d2
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -62,6 +62,13 @@ extern char arm_arch_name[];
  builtin_define ("__ARM_FEATURE_CRC32");   \
if (TARGET_32BIT)   \
  builtin_define ("__ARM_32BIT_STATE"); \
+   if (arm_arch8 && !arm_arch_notm)\
+ { \
+   if (arm_arch_cmse && use_cmse)  \
+ builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);  \
+   else\
+ builtin_define 

[RFC][PATCHv3, ARM 7/8] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call]

[Andre Vieira (lists)]

On 29/01/16 17:08, Andre Vieira (lists) wrote:
> On 19/01/16 15:28, Andre Vieira (lists) wrote:
>> On 16/01/16 14:49, Senthil Kumar Selvaraj wrote:
>>> User-agent: mu4e 0.9.13; emacs 24.5.1
>>>
>>> Hi,
>>>
>>> Apologies for the bad posting style (I don't have the
>>> original email handy), but shouldn't _gnu_cmse_nonsecure_call be defined
>>> with the .global directive in the below hunk (to make it visible when
>>> linking)?
>>>
>>> diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
>>> b/libgcc/config/arm/cm=
>>> se_nonsecure_call.S
>>> new file mode 100644
>>> index
>>> ..bdc140f5bbe87c6599db225b1b9=
>>> b7bbc7d606710
>>> --- /dev/null
>>> +++ b/libgcc/config/arm/cmse_nonsecure_call.S
>>> @@ -0,0 +1,87 @@
>>> +.syntax unified
>>> +.thumb
>>> +__gnu_cmse_nonsecure_call:
>>>
>>> Right now, it ends up as a local symbol, and compiling and linking a
>>> program with cmse_nonsecure_call (say cmse-11.c), results in a linker
>>> error - the linker doesn't find the symbol even if it is present in
>>> libgcc.a. I found the problem that way - dumping symbols for my variant
>>> of libgcc.a and grepping showed the symbol to be available but local.
>>>
>>> Regards
>>> Senthil
>>>
>> Hi Senthil,
>>
>> Thanks for catching that!
>>
>> Cheers,
>> Andre
>>
> Hi there,
> 
> Added missing global symbol.
> 
> Is this OK?
> 
> Cheers,
> Andre
> 
> *** gcc/ChangeLog ***
> 2016-01-29  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc/config/arm/arm.c (detect_cmse_nonsecure_call): New.
>   (cmse_nonsecure_call_clear_caller_saved): New.
> * gcc/config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
> * gcc/config/arm/arm.md (call): Handle cmse_nonsecure_entry.
>   (call_value): Likewise.
>   (nonsecure_call_internal): New.
>   (nonsecure_call_value_internal): New.
> * gcc/config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
>   (*nonsecure_call_value_reg_thumb1_v5): New.
> * gcc/config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
>   (*nonsecure_call_value_reg_thumb2): New.
> * gcc/config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.
> * libgcc/config/arm/cmse_nonsecure_call.S: New.
> * libgcc/config/arm/t-arm: Compile cmse_nonsecure_call.S
> 
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-01-29  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-11.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-13.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-6.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.

Hi there,

Forgot to add a copyright header to the cmse_nonsecure_call.S in
https://gcc.gnu.org/ml/gcc-patches/2016-01/msg02334.html.
Rectified with this patch.

Any comments?

Cheers,
Andre

*** gcc/ChangeLog ***
2016-03-30  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc/config/arm/arm.c (detect_cmse_nonsecure_call): New.
  (cmse_nonsecure_call_clear_caller_saved): New.
* gcc/config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
* gcc/config/arm/arm.md (call): Handle cmse_nonsecure_entry.
  (call_value): Likewise.
  (nonsecure_call_internal): New

[COMMITTED] Add myself as GCC maintainer

[Andre Vieira (lists)]

Hi,

I have added myself to the "Write After Approval" maintainers list.
Committed revision r234902.

Cheers,
Andre

ChangeLog:
2016-04-12  Andre Vieira  

* MAINTAINERS (Write After Approval): Add myself.



Index: ChangeLog
===
--- ChangeLog	(revision 234902)
+++ ChangeLog	(revision 234903)
@@ -1,3 +1,7 @@
+2016-04-12  Andre Vieira  
+
+	* MAINTAINERS (Write After Approval): Add myself.
+
 2016-04-09  Steven G. Kargl  
 
 	* MAINTAINERS (Fortran maintainer): Remove myself.
Index: MAINTAINERS
===
--- MAINTAINERS	(revision 234902)
+++ MAINTAINERS	(revision 234903)
@@ -606,6 +606,7 @@
 Andre Vehreschild
 Alex Velenko	
 Ilya Verbin	
+Andre Vieira	
 Kugan Vivekanandarajah
 Ville Voutilainen
 Tom de Vries	

Re: [RFA 1/2]: Don't ignore target_header_dir when deciding inhibit_libc

[Andre Vieira (lists)]

On 17/03/16 16:33, Andre Vieira (lists) wrote:
> On 23/10/15 12:31, Bernd Schmidt wrote:
>> On 10/12/2015 11:58 AM, Ulrich Weigand wrote:
>>>
>>> Index: gcc/configure.ac
>>> ===
>>> --- gcc/configure.ac(revision 228530)
>>> +++ gcc/configure.ac(working copy)
>>> @@ -1993,7 +1993,7 @@ elif test "x$TARGET_SYSTEM_ROOT" != x; t
>>>   fi
>>>
>>>   if test x$host != x$target || test "x$TARGET_SYSTEM_ROOT" != x; then
>>> -  if test "x$with_headers" != x; then
>>> +  if test "x$with_headers" != x && test "x$with_headers" != xyes; then
>>>   target_header_dir=$with_headers
>>> elif test "x$with_sysroot" = x; then
>>>  
>>> target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
>>>
>>
>> I'm missing the beginning of this conversation, but this looks like a
>> reasonable change (avoiding target_header_dir=yes for --with-headers).
>> So, approved.
>>
>>
>> Bernd
>>
> Hi there,
> 
> I was wondering why this never made it to trunk. I am currently running
> into an issue that this patch would fix.
> 
> Cheers,
> Andre
> 
Ping.

Re: [RFA 1/2]: Don't ignore target_header_dir when deciding inhibit_libc

[Andre Vieira (lists)]

On 23/10/15 12:31, Bernd Schmidt wrote:
> On 10/12/2015 11:58 AM, Ulrich Weigand wrote:
>>
>> Index: gcc/configure.ac
>> ===
>> --- gcc/configure.ac(revision 228530)
>> +++ gcc/configure.ac(working copy)
>> @@ -1993,7 +1993,7 @@ elif test "x$TARGET_SYSTEM_ROOT" != x; t
>>   fi
>>
>>   if test x$host != x$target || test "x$TARGET_SYSTEM_ROOT" != x; then
>> -  if test "x$with_headers" != x; then
>> +  if test "x$with_headers" != x && test "x$with_headers" != xyes; then
>>   target_header_dir=$with_headers
>> elif test "x$with_sysroot" = x; then
>>  
>> target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
>>
> 
> I'm missing the beginning of this conversation, but this looks like a
> reasonable change (avoiding target_header_dir=yes for --with-headers).
> So, approved.
> 
> 
> Bernd
> 
Hi there,

I was wondering why this never made it to trunk. I am currently running
into an issue that this patch would fix.

Cheers,
Andre

Re: Re: [PATCH][Testsuite] Add --param sra-max-scalarization-size-Ospeed to sra-12.c

[Andre Vieira (lists)]

On 21/10/15 16:59, Jeff Law wrote:
> On 10/21/2015 09:52 AM, Alan Lawrence wrote:
>> gcc.dg/tree-ssa/sra-12.c is skipped on a bunch of targets, including
>> AArch64,
>> because the default max-scalarization-size depends on MOVE_RATIO, and
>> on those
>> targets thus ends up being too small for SRA to optimize the testcase.
>> Recently
>> I noticed that the test has been failing for some time on ARM too.
>> This patch
>> fixes the test on ARM, AArch64, avr, and sh, and by extension I
>> believe also on
>> nds32, although I haven't managed to build a nds32 compiler to check.
>>
>> There is an argument that instead we should skip the test on ARM too;
>> or rather,
>> since at least ARM and AArch64 would like the test to pass, we should
>> xfail it
>> on those platforms until we have time to experiment with the
>> threshold/param for
>> SRA. I hope to do some more investigation on that front as part of (or
>> followup
>> to) PR/63679.
>>
>> Is this OK for trunk?
>>
>> Cheers,
>> Alan
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.dg/tree-ssa/sra-12.c: Enable test on all targets; add --param
>> sra-max-scalarization-size-Ospeed.
> OK.
> jeff
> 

OK to backport this to gcc-5-branch?

Cheers,
Andre

[GCC][ARM] Skip tests that assume target supports arm mode, when testing M profiles

[Andre Vieira (lists)]

Hello,

This patch skips four tests that assume a target supports ARM mode when
testing M-profiles.
Tested it by running the four tests for A-profiles and M-profiles.

Is this ok?

Cheers,
Andre

gcc/testsuite/ChangeLog:
2016-03-17  Andre Vieira  

* gcc/testsuite/gcc.target/arm/attr-align1.c: Skip if M-profile.
* gcc/testsuite/gcc.target/arm/attr-align3.c: Likewise.
* gcc/testsuite/gcc.target/arm/attr_arm.c: Likewise.
* gcc/testsuite/gcc.target/arm/flip-thumb.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/arm/attr-align1.c 
b/gcc/testsuite/gcc.target/arm/attr-align1.c
index 
96d29a9eed5a81306cb90393a2eb4fe7236ae50b..a53f16706860b69fcc60071b818fbc9f89fc33c7
 100644
--- a/gcc/testsuite/gcc.target/arm/attr-align1.c
+++ b/gcc/testsuite/gcc.target/arm/attr-align1.c
@@ -2,6 +2,7 @@
Verify alignment when both attribute optimize and target are used.  */
 /* { dg-do compile } */
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-skip-if "" arm_cortex_m } */
 
 void
 __attribute__ ((target ("arm")))
diff --git a/gcc/testsuite/gcc.target/arm/attr-align3.c 
b/gcc/testsuite/gcc.target/arm/attr-align3.c
index 
edcf64b45e053eca4ae5f0be2de3afd7b674f464..593d7fbc2b999d264cb06f54363c471480117f32
 100644
--- a/gcc/testsuite/gcc.target/arm/attr-align3.c
+++ b/gcc/testsuite/gcc.target/arm/attr-align3.c
@@ -2,6 +2,7 @@
Verify alignment when attribute target is used.  */
 /* { dg-do compile } */
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-skip-if "" arm_cortex_m } */
 /* { dg-options "-Os -mthumb" }  */
 
 /* Check that arm code is always 4 bytes aligned.  */
diff --git a/gcc/testsuite/gcc.target/arm/attr_arm.c 
b/gcc/testsuite/gcc.target/arm/attr_arm.c
index 
f5c70ef690fc68425e0c4a0f458cd73ebde2f0ab..d765d121e2965a440234a1793688bc97aa60d831
 100644
--- a/gcc/testsuite/gcc.target/arm/attr_arm.c
+++ b/gcc/testsuite/gcc.target/arm/attr_arm.c
@@ -1,5 +1,6 @@
 /* Check that attribute target arm is recognized.  */
 /* { dg-do compile } */
+/* { dg-skip-if "" arm_cortex_m } */
 /* { dg-final { scan-assembler "\\.arm" } } */
 /* { dg-final { scan-assembler-not "\\.thumb_func" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/flip-thumb.c 
b/gcc/testsuite/gcc.target/arm/flip-thumb.c
index 
355d66377558d9007f58056180940122fcf148e0..4bbe546b6325b2cbc9f9b7f7c52c29815c231916
 100644
--- a/gcc/testsuite/gcc.target/arm/flip-thumb.c
+++ b/gcc/testsuite/gcc.target/arm/flip-thumb.c
@@ -2,6 +2,7 @@
 /* { dg-do compile } */
 /* Make sure the current multilib supports thumb.  */
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-skip-if "" arm_cortex_m } */
 /* { dg-options "-O2 -mflip-thumb -mno-restrict-it" } */
 /* { dg-final { scan-assembler "\\.arm" } } */
 /* { dg-final { scan-assembler-times "\\.thumb_func" 1} } */

Re: [GCC][ARM] Skip tests that assume target supports arm mode, when testing M profiles

[Andre Vieira (lists)]

On 21/03/16 10:39, Ramana Radhakrishnan wrote:
> On Thu, Mar 17, 2016 at 4:39 PM, Andre Vieira (lists)
> <andre.simoesdiasvie...@arm.com> wrote:
>> Hello,
>>
>> This patch skips four tests that assume a target supports ARM mode when
>> testing M-profiles.
>> Tested it by running the four tests for A-profiles and M-profiles.
>>
>> Is this ok?
> 
> OK.
> 
> Ramana
>>
>> Cheers,
>> Andre
>>
>> gcc/testsuite/ChangeLog:
>> 2016-03-17  Andre Vieira  <andre.simoesdiasvieira@arm>
>>
>> * gcc/testsuite/gcc.target/arm/attr-align1.c: Skip if M-profile.
>> * gcc/testsuite/gcc.target/arm/attr-align3.c: Likewise.
>> * gcc/testsuite/gcc.target/arm/attr_arm.c: Likewise.
>> * gcc/testsuite/gcc.target/arm/flip-thumb.c: Likewise.
> 
Committed by Thomas on revision r234373 with fixed ChangeLog (removed
the 'gcc/testsuite' parts.

Cheers,
Andre

Re: [PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

On 03/03/16 11:28, Kyrill Tkachov wrote:
> Hi Andre,
> 
> On 02/03/16 12:21, Andre Vieira (lists) wrote:
>> Hi,
>>
>> Tests used to check for "r8" which will not work because cortex-r8
>> string is now included in the assembly. Fixed by checking for "[^\-]r8".
>>
>> Is this Ok?
>>
>> Cheers,
>> Andre
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2016-03-02  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>
>>   * gcc.target/arm/pr45701-1.c: Change assembler scan to not
>>   trigger for cortex-r8, when scanning for register r8.
>>   * gcc.target/arm/pr45701-2.c: Likewise.
> 
> Ok.
> Thanks,
> Kyrill
> 
Thomas commited on my behalf at revision r234040.

Had to rebase arm-tune.md and invoke.texi, these were all obvious changes.

Cheers,
Andre

Re: [Ping^2][PATCH][GCC-5] Fix "#pragma GCC pop_options" warning.

[Andre Vieira (lists)]

On 29/02/16 10:47, Andre Vieira (lists) wrote:
> On 15/02/16 10:33, Andre Vieira (lists) wrote:
>> On 18/01/16 11:04, Andre Vieira (lists) wrote:
>>> Hi there,
>>>
>>> Can we have the "#pragma GCC pop_options" fix backported to GCC-5?
>>>
>>> Patch found in https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
>>> and was committed in r228794.
>>>
>>> The same patch applies cleanly to gcc-5, which would otherwise not be
>>> able to use this pragma even though the support is there.
>>>
>>> Cheers,
>>> Andre
>>>
>>
>> Ping.
>>
> Ping.
> 
I understood it was a good idea to CC the appropriate maintainer on
this, so adding Bernd Schmidt to the CC.

Sorry for the noise.

Cheers,
Andre

Re: [Ping^2][PATCH][GCC-5] Fix "#pragma GCC pop_options" warning.

[Andre Vieira (lists)]

On 03/03/16 12:11, Bernd Schmidt wrote:
> On 03/03/2016 11:45 AM, Andre Vieira (lists) wrote:
>> On 29/02/16 10:47, Andre Vieira (lists) wrote:
>>> On 15/02/16 10:33, Andre Vieira (lists) wrote:
>>>> On 18/01/16 11:04, Andre Vieira (lists) wrote:
>>>>> Hi there,
>>>>>
>>>>> Can we have the "#pragma GCC pop_options" fix backported to GCC-5?
>>>>>
>>>>> Patch found in
>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-10/msg01261.html
>>>>> and was committed in r228794.
>>>>>
>>>>> The same patch applies cleanly to gcc-5, which would otherwise not be
>>>>> able to use this pragma even though the support is there.
> 
>> I understood it was a good idea to CC the appropriate maintainer on
>> this, so adding Bernd Schmidt to the CC.
> 
> Yeah, I think I remember this one. Ok.
> 
> 
> Bernd
> 

Thomas committed on my behalf at revision r233939.

2016-03-03  Andre Vieira  <andre.simoesdiasvie...@arm.com>

Backport from mainline
2015-10-14  Dominik Vogt  <v...@linux.vnet.ibm.com>

Fix "#pragma GCC pop_options"

gcc/ChangeLog

* targhooks.c (default_target_option_pragma_parse): Do not warn if
called on behalf of "#pragma GCC pop_options".

gcc/testsuite/ChangeLog
* gcc.dg/pragma-pop_options-1.c: New test.

Thank you Thomas and Bernd.

Cheers,
Andre

[PATCH 2/2][GCC][ARM] Fix testcases after introduction of Cortex-R8

[Andre Vieira (lists)]

Hi,

Tests used to check for "r8" which will not work because cortex-r8
string is now included in the assembly. Fixed by checking for "[^\-]r8".

Is this Ok?

Cheers,
Andre

gcc/testsuite/ChangeLog:

2016-03-02  Andre Vieira  

 * gcc.target/arm/pr45701-1.c: Change assembler scan to not
 trigger for cortex-r8, when scanning for register r8.
 * gcc.target/arm/pr45701-2.c: Likewise.
>From 57f8d328b7e20db4e3776eb5c4d8094d170836ba Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira 
Date: Tue, 16 Feb 2016 12:01:48 +
Subject: [PATCH 2/5] Fix testcases for Cortex-R8

---
 gcc/testsuite/gcc.target/arm/pr45701-1.c | 2 +-
 gcc/testsuite/gcc.target/arm/pr45701-2.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/pr45701-1.c b/gcc/testsuite/gcc.target/arm/pr45701-1.c
index 454a087eedbabad95cd7144eb1bb49b591730e54..a5db56fc6f2f3cb334b514a72ff500308c361832 100644
--- a/gcc/testsuite/gcc.target/arm/pr45701-1.c
+++ b/gcc/testsuite/gcc.target/arm/pr45701-1.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
 /* { dg-options "-mthumb -Os" }  */
 /* { dg-final { scan-assembler "push\t\{r3" } } */
-/* { dg-final { scan-assembler-not "r8" } } */
+/* { dg-final { scan-assembler-not "[^\-]r8" } } */
 
 extern int hist_verify;
 extern int a1;
diff --git a/gcc/testsuite/gcc.target/arm/pr45701-2.c b/gcc/testsuite/gcc.target/arm/pr45701-2.c
index afe0840d44b197ca6b1b6b316d9d21a97598837f..765981b90db38f534e13e9e8a8f538c8408f798a 100644
--- a/gcc/testsuite/gcc.target/arm/pr45701-2.c
+++ b/gcc/testsuite/gcc.target/arm/pr45701-2.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
 /* { dg-options "-mthumb -Os" }  */
 /* { dg-final { scan-assembler "push\t\{r3" } } */
-/* { dg-final { scan-assembler-not "r8" } } */
+/* { dg-final { scan-assembler-not "[^\-]r8" } } */
 
 extern int hist_verify;
 extern int a1;
-- 
1.9.1

[PATCH 0/2][GCC][ARM] Add support for Cortex-R8

[Andre Vieira (lists)]

Hi there,

This patch series adds support for the recently announced ARM core
Cortex-R8.

Andre Vieira(2)
Add support for Cortex-R8
Fix testcases after introduction of Cortex-R8

Tested by comparing regression runs of Cortex-R7 vs Cortex-R8 for both
ARM and THUMB modes.

Is this OK?

Cheers,
Andre

[PATCH 1/2][GCC][ARM] Add support for Cortex-R8

[Andre Vieira (lists)]

gcc/ChangeLog:

2016-03-02  Andre Vieira  

 * config/arm/arm-cores.def (cortex-r8): New.
 * config/arm/arm-tables.opt (cortex-r8): New.
 * config/arm/arm-tune.md: Regenerate.
 * gcc/doc/invoke.texi: Add cortex-r8 to list of cpu values.
>From 8d10507bd80fd0a1db221669a67785f57ffc304f Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira 
Date: Tue, 16 Feb 2016 12:01:28 +
Subject: [PATCH 1/5] Add Cortex-R8

---
 gcc/config/arm/arm-cores.def  |  1 +
 gcc/config/arm/arm-tables.opt |  3 +++
 gcc/config/arm/arm-tune.md| 11 ++-
 gcc/doc/invoke.texi   |  2 +-
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 6538861898689e64a3554f709c5a3355cffad187..0908c6996ecd799f463b8501d31f0b74bada5828 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -155,6 +155,7 @@ ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED |
 ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
 ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
 ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r8",		cortexr8, cortexr7,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
 ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
 ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7EM), v7m)
 ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7M), v7m)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 6d6ee96828146fe076a6a1ee285f6a1d578b6c85..8fc6a331241a7928bc274250bcfa7d8438bf41aa 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -286,6 +286,9 @@ EnumValue
 Enum(processor_type) String(cortex-r7) Value(cortexr7)
 
 EnumValue
+Enum(processor_type) String(cortex-r8) Value(cortexr8)
+
+EnumValue
 Enum(processor_type) String(cortex-m7) Value(cortexm7)
 
 EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 1c842180cee6afd7a560ef51b63632bb0f83b932..0a6906563c2f5b4e4f6e6c91e978db4e7bdf907f 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -30,9 +30,10 @@
 	cortexa8,cortexa9,cortexa12,
 	cortexa15,cortexa17,cortexr4,
 	cortexr4f,cortexr5,cortexr7,
-	cortexm7,cortexm4,cortexm3,
-	marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
-	cortexa35,cortexa53,cortexa57,
-	cortexa72,exynosm1,qdf24xx,
-	xgene1,cortexa57cortexa53,cortexa72cortexa53"
+	cortexr8,cortexm7,cortexm4,
+	cortexm3,marvell_pj4,cortexa15cortexa7,
+	cortexa17cortexa7,cortexa35,cortexa53,
+	cortexa57,cortexa72,exynosm1,
+	qdf24xx,xgene1,cortexa57cortexa53,
+	cortexa72cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0a2a6f45d7cf916a84dc48b6885cf04d43b12d8a..52cbdd26c453fd54562b43c23428a8671e74254d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13876,7 +13876,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
 @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
 @samp{cortex-r4},
-@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
+@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-m7},
 @samp{cortex-m4},
 @samp{cortex-m3},
 @samp{cortex-m1},
-- 
1.9.1

Re: [patch, testsuite, ARM] don't try to execute simd.exp tests on targets without NEON

[Andre Vieira (lists)]

On 21/05/15 10:01, Kyrill Tkachov wrote:
> Hi Sandra,
> 
> On 21/05/15 06:43, Sandra Loosemore wrote:
>> This is another patch aimed at fixing bugs relating to trying to execute
>> NEON code on a target that doesn't support it revealed by my
>> arm-none-eabi testing on a gazillion different multilibs.  Inspired by
>> what vect.exp does and my other patch in this group to fix
>> advsimd-intrinsics.exp, I've hacked simd.exp to test for NEON
>> compilation and execution support and use set dg-do-what-default to
>> either "compile" or "run" as appropriate, or skip the whole set of tests
>> if neither is present.  And, I've removed the explicit "dg-do run" and
>> arm_neon_ok test (which only tests for compilation support, not
>> execution support) from all the individual test cases.
>>
>> OK to commit?
> 
> This is ok and there is one less headache with NEON testing :)
> Thanks,
> Kyrill
> 
>>
>> -Sandra
>>
> 
Could we have this backported to the gcc-5-branch? The patch seems to
apply cleanly and it would clean up testing for simd/neon for gcc-5.

Cheers,
Andre

Re: [PATCH][Testsuite] Add --param sra-max-scalarization-size-Ospeed to sra-12.c

[Andre Vieira (lists)]

On 18/03/16 10:34, Andre Vieira (lists) wrote:
> On 21/10/15 16:59, Jeff Law wrote:
>> On 10/21/2015 09:52 AM, Alan Lawrence wrote:
>>> gcc.dg/tree-ssa/sra-12.c is skipped on a bunch of targets, including
>>> AArch64,
>>> because the default max-scalarization-size depends on MOVE_RATIO, and
>>> on those
>>> targets thus ends up being too small for SRA to optimize the testcase.
>>> Recently
>>> I noticed that the test has been failing for some time on ARM too.
>>> This patch
>>> fixes the test on ARM, AArch64, avr, and sh, and by extension I
>>> believe also on
>>> nds32, although I haven't managed to build a nds32 compiler to check.
>>>
>>> There is an argument that instead we should skip the test on ARM too;
>>> or rather,
>>> since at least ARM and AArch64 would like the test to pass, we should
>>> xfail it
>>> on those platforms until we have time to experiment with the
>>> threshold/param for
>>> SRA. I hope to do some more investigation on that front as part of (or
>>> followup
>>> to) PR/63679.
>>>
>>> Is this OK for trunk?
>>>
>>> Cheers,
>>> Alan
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.dg/tree-ssa/sra-12.c: Enable test on all targets; add --param
>>> sra-max-scalarization-size-Ospeed.
>> OK.
>> jeff
>>
> 
> OK to backport this to gcc-5-branch?
> 
> Cheers,
> Andre
> 
Ping.

[arm-embedded]: Don't ignore target_header_dir when deciding inhibit_libc

[Andre Vieira (lists)]

On 17/03/16 16:33, Andre Vieira (lists) wrote:
> On 23/10/15 12:31, Bernd Schmidt wrote:
>> On 10/12/2015 11:58 AM, Ulrich Weigand wrote:
>>>
>>> Index: gcc/configure.ac
>>> ===
>>> --- gcc/configure.ac(revision 228530)
>>> +++ gcc/configure.ac(working copy)
>>> @@ -1993,7 +1993,7 @@ elif test "x$TARGET_SYSTEM_ROOT" != x; t
>>>   fi
>>>
>>>   if test x$host != x$target || test "x$TARGET_SYSTEM_ROOT" != x; then
>>> -  if test "x$with_headers" != x; then
>>> +  if test "x$with_headers" != x && test "x$with_headers" != xyes; then
>>>   target_header_dir=$with_headers
>>> elif test "x$with_sysroot" = x; then
>>>  
>>> target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
>>>
>>
>> I'm missing the beginning of this conversation, but this looks like a
>> reasonable change (avoiding target_header_dir=yes for --with-headers).
>> So, approved.
>>
>>
>> Bernd
>>
> Hi there,
> 
> I was wondering why this never made it to trunk. I am currently running
> into an issue that this patch would fix.
> 
> Cheers,
> Andre
> 
We decided to apply this to the embedded-5-branch at revision r234576.

Cheers,
Andre

[RFC][PATCH v3, ARM 5/8] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

On 29/03/16 17:49, Andre Vieira (lists) wrote:
> On 29/01/16 17:07, Andre Vieira (lists) wrote:
>> On 26/12/15 01:54, Thomas Preud'homme wrote:
>>> [Sending on behalf of Andre Vieira]
>>>
>>> Hello,
>>>
>>> This patch extends support for the ARMv8-M Security Extensions
>>> 'cmse_nonsecure_entry' attribute to safeguard against leak of
>>> information through unbanked registers.
>>>
>>> When returning from a nonsecure entry function we clear all
>>> caller-saved registers that are not used to pass return values, by
>>> writing either the LR, in case of general purpose registers, or the
>>> value 0, in case of FP registers. We use the LR to write to APSR and
>>> FPSCR too. We currently only support 32 FP registers as in we only
>>> clear D0-D7.
>>> We currently do not support entry functions that pass arguments or
>>> return variables on the stack and we diagnose this. This patch relies
>>> on the existing code to make sure callee-saved registers used in
>>> cmse_nonsecure_entry functions are saved and restored thus retaining
>>> their nonsecure mode value, this should be happening already as it is
>>> required by AAPCS.
>>>
>>>
>>> *** gcc/ChangeLog ***
>>> 2015-10-27  Andre Vieira<andre.simoesdiasvie...@arm.com>
>>>  Thomas Preud'homme  <thomas.preudho...@arm.com>
>>>
>>>  * gcc/config/arm/arm.c (output_return_instruction): Clear
>>>registers.
>>>(thumb2_expand_return): Likewise.
>>>(thumb1_expand_epilogue): Likewise.
>>>(arm_expand_epilogue): Likewise.
>>>(cmse_nonsecure_entry_clear_before_return): New.
>>>  * gcc/config/arm/arm.h (TARGET_DSP_ADD): New macro define.
>>>  * gcc/config/arm/thumb1.md (*epilogue_insns): Change length
>>> attribute.
>>>  * gcc/config/arm/thumb2.md (*thumb2_return): Likewise.
>>>
>>> *** gcc/testsuite/ChangeLog ***
>>> 2015-10-27  Andre Vieira<andre.simoesdiasvie...@arm.com>
>>>  Thomas Preud'homme  <thomas.preudho...@arm.com>
>>>
>>>  * gcc.target/arm/cmse/cmse.exp: Test different multilibs
>>> separate.
>>>  * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers
>>> are cleared.
>>>  * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
>>>  * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
>>>  * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
>>>  * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
>>>  * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.
>>>
>>>
>>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
>>> index
>>> f12e3c93bbe24b10ed8eee6687161826773ef649..b06e0586a3da50f57645bda13629bc4dbd3d53b7
>>> 100644
>>> --- a/gcc/config/arm/arm.h
>>> +++ b/gcc/config/arm/arm.h
>>> @@ -230,6 +230,9 @@ extern void
>>> (*arm_lang_output_object_attributes_hook)(void);
>>>   /* Integer SIMD instructions, and extend-accumulate instructions.  */
>>>   #define TARGET_INT_SIMD \
>>> (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
>>> +/* Parallel addition and subtraction instructions.  */
>>> +#define TARGET_DSP_ADD \
>>> +  (TARGET_ARM_ARCH >= 6 && (arm_arch_notm || arm_arch7em))
>>>
>>>   /* Should MOVW/MOVT be used in preference to a constant pool.  */
>>>   #define TARGET_USE_MOVT \
>>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>>> index
>>> e530b772e3cc053c16421a2a2861d815d53ebb01..0700478ca38307f35d0cb01f83ea182802ba28fa
>>> 100644
>>> --- a/gcc/config/arm/arm.c
>>> +++ b/gcc/config/arm/arm.c
>>> @@ -19755,6 +19755,24 @@ output_return_instruction (rtx operand, bool
>>> really_return, bool reverse,
>>>   default:
>>> if (IS_CMSE_ENTRY (func_type))
>>>   {
>>> +  char flags[12] = "APSR_nzcvq";
>>> +  /* Check if we have to clear the 'GE bits' which is only
>>> used if
>>> + parallel add and subtraction instructions are available.  */
>>> +  if (TARGET_DSP_ADD)
>>> +{
>>> +  /* If so also clear the ge flags.  */
>>> +  flags[10] = 'g';
>>> +  flags[11] = '\0';
>>> +}
>>&g

[PING^3][PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

Ping for GCC-7, patch applies cleanly, passed make check for cortex-m0.

Might be worth mentioning that this patch has been used in three
releases of the GNU ARM embedded toolchain, using GCC versions 4.9 and
5, and no issues have been reported so far.

On 25/01/16 17:15, Andre Vieira (lists) wrote:
> Ping.
> 
> On 27/10/15 17:03, Andre Vieira wrote:
>> Ping.
>>
>> BR,
>> Andre
>>
>> On 13/10/15 18:01, Andre Vieira wrote:
>>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings
>>> (https://git.linaro.org/toolchain/cortex-strings.git), which was
>>> contributed by ARM under Free BSD license.
>>>
>>> The new aeabi_idiv routine is used to replace the one in
>>> libgcc/config/arm/lib1funcs.S. This replacement happens within the
>>> Thumb1 wrapper. The new routine is under LGPLv3 license.
>>>
>>> The main advantage of this version is that it can improve the
>>> performance of the aeabi_idiv function for Thumb1. This solution will
>>> also increase the code size. So it will only be used if
>>> __OPTIMIZE_SIZE__ is not defined.
>>>
>>> Make check passed for armv6-m.
>>>
>>> libgcc/ChangeLog:
>>> 2015-08-10  Hale Wang  <hale.w...@arm.com>
>>>   Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>
>>> * config/arm/lib1funcs.S: Add new wrapper.
>>>
> 

Re: [patch] libstdc++/69703 ignore endianness in codecvt_utf8

[Andre Vieira (lists)]

On 20/04/16 18:40, Jonathan Wakely wrote:
> On 19/04/16 19:07 +0100, Jonathan Wakely wrote:
>> This was reported as a bug in the Filesystem library, but it's
>> actually a problem in the codecvt_utf8 facet that it uses.
> 
> The fix had a silly typo meaning it didn't work for big endian
> targets, which was revealed by the improved tests I added.
> 
> Tested x86_64-linux and powerpc64-linux, committed to trunk.
> 
> 
Hi Jonathan,

We are seeing experimental/filesystem/path/native/string.cc fail on
baremetal targets. I'm guessing this is missing a
'dg-require-filesystem-ts', as seen on other tests like
experimental/filesystem/path/modifiers/swap.cc.

Cheers,
Andre

Re: [RFA 1/2]: Don't ignore target_header_dir when deciding inhibit_libc

[Andre Vieira (lists)]

On 07/04/16 10:30, Andre Vieira (lists) wrote:
> On 17/03/16 16:33, Andre Vieira (lists) wrote:
>> On 23/10/15 12:31, Bernd Schmidt wrote:
>>> On 10/12/2015 11:58 AM, Ulrich Weigand wrote:
>>>>
>>>> Index: gcc/configure.ac
>>>> ===
>>>> --- gcc/configure.ac(revision 228530)
>>>> +++ gcc/configure.ac(working copy)
>>>> @@ -1993,7 +1993,7 @@ elif test "x$TARGET_SYSTEM_ROOT" != x; t
>>>>   fi
>>>>
>>>>   if test x$host != x$target || test "x$TARGET_SYSTEM_ROOT" != x; then
>>>> -  if test "x$with_headers" != x; then
>>>> +  if test "x$with_headers" != x && test "x$with_headers" != xyes; then
>>>>   target_header_dir=$with_headers
>>>> elif test "x$with_sysroot" = x; then
>>>>  
>>>> target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
>>>>
>>>
>>> I'm missing the beginning of this conversation, but this looks like a
>>> reasonable change (avoiding target_header_dir=yes for --with-headers).
>>> So, approved.
>>>
>>>
>>> Bernd
>>>
>> Hi there,
>>
>> I was wondering why this never made it to trunk. I am currently running
>> into an issue that this patch would fix.
>>
>> Cheers,
>> Andre
>>
> Ping.
> 
Ping.

[PATCHv2, PING][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 11/07/16 17:56, Andre Vieira (lists) wrote:
> On 07/07/16 13:30, mickael guene wrote:
>> Hi Andre,
>>
>>  Another feedback on your purecode patch.
>>  You have to disable casesi pattern since then it will
>> generate wrong code with -mpure-code option.
>>  Indeed it will generate an 'adr rx, .Lx' (aka
>> 'subs rx, PC, #offset') which will not work in our
>> case since 'Lx' label is put in an .rodata section.
>> So offset value is unknown and can be impossible
>> to encode correctly.
>>
>> Regards
>> Mickael
>>
>> On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:
>>> Hello,
>>>
>>> This patch adds the -mpure-code option for ARM. This option ensures
>>> functions are put into sections that contain only code and no data. To
>>> ensure this throughout compilation we give these sections the ARM
>>> processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
>>> is only supported for non-pic code for armv7-m targets.
>>>
>>> This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
>>> This target hook enables a target to use the numeric value for elf
>>> section attributes rather than their alphabetical representation. If
>>> TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
>>> 'default_elf_asm_named_section', will print the numeric value of the
>>> section attributes for the current section. This target hook has two
>>> parameters:
>>> unsigned int FLAGS, the input parameter that tells the function the
>>> current section's attributes;
>>> unsigned int *NUM, used to pass down the numerical representation of the
>>> section's attributes.
>>>
>>> The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
>>> false, so existing behavior is not changed.
>>>
>>> Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
>>> arm-none-eabi with a Cortex-M3 target.
>>>
>>>
>>> gcc/ChangeLog:
>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>> Terry Guo  <terry@arm.com>
>>>
>>> * target.def (elf_flags_numeric): New target hook.
>>> * targhooks.h (default_asm_elf_flags_numeric): New.
>>> * varasm.c (default_asm_elf_flags_numeric): New.
>>>   (default_elf_asm_named_section): Use new target hook.
>>> * config/arm/arm.opt (mpure-code): New.
>>> * config/arm/arm.h (SECTION_ARM_PURECODE): New.
>>> * config/arm/arm.c (arm_asm_init_sections): Add section
>>>   attribute to default text section if -mpure-code.
>>>   (arm_option_check_internal): Diagnose use of option with
>>>   non supported targets and/or options.
>>>   (arm_asm_elf_flags_numeric): New.
>>>   (arm_function_section): New.
>>>   (arm_elf_section_type_flags): New.
>>> * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
>>>   for -mpure-code.
>>> * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
>>> * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.
>>>
>>>
>>>
>>> gcc/testsuite/ChangeLog:
>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>> Terry Guo  <terry@arm.com>
>>>
>>> * gcc.target/arm/pure-code/ffunction-sections.c: New.
>>> * gcc.target/arm/pure-code/no-literal-pool.c: New.
>>> * gcc.target/arm/pure-code/pure-code.exp: New.
>>>
>>
> Hi Sandra, Mickael,
> 
> Thank you for your comments. I changed the description of -mpure-code in
> invoke.texi to better reflect the error message you get wrt supported
> targets.
> 
> As for the target hook description, I hope the text is clearer now. Let
> me know if you think it needs further explanation.
> 
> I also fixed the double '%' in the text string for unnamed text sections
> and disabled the casesi pattern.
> 
> I duplicated the original casesi test
> 'gcc/testsuite/gcc.c-torture/compile/pr46934.c' for pure-code to make
> sure the casesi was disabled and other patterns were selected instead.
> 
> Reran regressions for pure-code.exp for Cortex-M3.
> 
> Cheers,
> Andre
> 
> 
> gcc/ChangeLog:
> 2016-07-11  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> Terry Guo  <terry@arm.com>
> 
> * target.def (elf_flags_numeric): New target hook.
>

[PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions

[Andre Vieira (lists)]

[PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions

Hello,

This is a respin of a previous patch series for ARMv8-M Security
Extensions. In this version I have removed one patch, rebased the rest
and changed some of them.

This patch series aims at implementing support for ARMv8-M's Security
Extensions. You can find the specification of ARMV8-M Security
Extensions in: ARM®v8-M Security Extensions: Requirements on Development
Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently:
- do not support passing arguments or returning on the stack for
cmse_nonsecure_{call,entry} functions,
- only test Security Extensions for -mfpu=fpv5-d16 and fpv5-sp-d16 and
only support single and double precision FPU's with d16.

Bootstrapped and tested on arm-none-linux-gnueabihf and tested on
arm-none-eabi with ARMv8-M Baseline and Mainline targets.

Andre Vieira (7):
 Add support for ARMv8-M's Security Extensions flag and intrinsics
 Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute
 ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and
bxns return
 ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers
 Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute
 ARMv8-M Security Extension's cmse_nonsecure_call: use
__gnu_cmse_nonsecure_call
 Added support for ARMV8-M Security Extension cmse_nonsecure_caller
intrinsic

[PATCH 2/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Andre Vieira (lists)]

This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute. In this patch we implement the
attribute handling and diagnosis around the attribute. See Section 5.4
of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
(arm_attribute_table): Added cmse_nonsecure_entry
(arm_compute_func_type): Handle cmse_nonsecure_entry.
(cmse_func_args_or_return_in_stack): New.
(arm_handle_cmse_nonsecure_entry): New.
* config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
(IS_CMSE_ENTRY): Likewise.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: New.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
e3697bbcb425999db31ac2b4f47e14bb3f2ffa89..5307ec8f904230db5ea44150ef471d928926ab6d
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1373,6 +1373,7 @@ enum reg_class
 #define ARM_FT_VOLATILE(1 << 4) /* Does not return.  */
 #define ARM_FT_NESTED  (1 << 5) /* Embedded inside another func.  */
 #define ARM_FT_STACKALIGN  (1 << 6) /* Called with misaligned stack.  */
+#define ARM_FT_CMSE_ENTRY  (1 << 7) /* ARMv8-M non-secure entry function.  
*/
 
 /* Some macros to test these flags.  */
 #define ARM_FUNC_TYPE(t)   (t & ARM_FT_TYPE_MASK)
@@ -1381,6 +1382,7 @@ enum reg_class
 #define IS_NAKED(t)(t & ARM_FT_NAKED)
 #define IS_NESTED(t)   (t & ARM_FT_NESTED)
 #define IS_STACKALIGN(t)   (t & ARM_FT_STACKALIGN)
+#define IS_CMSE_ENTRY(t)   (t & ARM_FT_CMSE_ENTRY)
 
 
 /* Structure used to hold the function stack frame layout.  Offsets are
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
9903d9cd8c5ff68a2318a643bdf31cf48016eba4..11417ab3c2f7101866ee5d6b100913480e5c336e
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -134,6 +134,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
+static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -343,6 +344,9 @@ static const struct attribute_spec arm_attribute_table[] =
   { "notshared",0, 0, false, true, false, arm_handle_notshared_attribute,
 false },
 #endif
+  /* ARMv8-M Security Extensions support.  */
+  { "cmse_nonsecure_entry", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_entry, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -3633,6 +3637,9 @@ arm_compute_func_type (void)
   else
 type |= arm_isr_value (TREE_VALUE (a));
 
+  if (lookup_attribute ("cmse_nonsecure_entry", attr))
+type |= ARM_FT_CMSE_ENTRY;
+
   return type;
 }
 
@@ -6634,6 +6641,110 @@ arm_handle_notshared_attribute (tree *node,
 }
 #endif
 
+/* This function returns true if a function with declaration FNDECL, name
+   NAME and type FNTYPE uses the stack to pass arguments or return variables
+   and false otherwise.  This is used for functions with the attributes
+   'cmse_nonsecure_call' or 'cmse_nonsecure_entry' and this function will issue
+   diagnostic messages if the stack is used.  */
+
+static bool
+cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
+
+  /* Error out if any argument is passed on the stack.  */
+  arm_init_cumulative_args (_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+{
+  rtx arg_rtx;
+  machine_mode arg_mode = TYPE_MODE (arg_type);
+
+  prev_arg_type = arg_type;
+  if (VOID_TYPE_P (arg_type))
+   continue;
+
+  if (!first_param)
+   arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
+  arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
+  if (!arg_rtx
+ || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
+   {
+ error ("%qE attribute not available to functions with arguments "
+"passed on the stack", name);
+ return true;
+   }
+  first_param = false;
+}
+
+  /* Error out for variadic functions since we 

[PATCH 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR and FPSCR too. We currently do
not support entry functions that pass arguments or return variables on
the stack and we diagnose this. This patch relies on the existing code
to make sure callee-saved registers used in cmse_nonsecure_entry
functions are saved and restored thus retaining their nonsecure mode
value, this should be happening already as it is required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (output_return_instruction): Clear
registers.
(thumb2_expand_return): Likewise.
(thumb1_expand_epilogue): Likewise.
(thumb_exit): Likewise.
(arm_expand_epilogue): Likewise.
(cmse_nonsecure_entry_clear_before_return): New.
(comp_not_to_clear_mask_str_un): New.
(compute_not_to_clear_mask): New.
* config/arm/thumb1.md (*epilogue_insns): Change length attribute.
* config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
* gcc.target/arm/cmse/struct-1.c: New.
* gcc.target/arm/cmse/bitfield-1.c: New.
* gcc.target/arm/cmse/bitfield-2.c: New.
* gcc.target/arm/cmse/bitfield-3.c: New.
* gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are
cleared.
* gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
9fba371768b1eba3a11dc8aa5d6acf8cc30f464d..81a9d9a6fb29d0956a661734d60dd2e44cb554b8
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17473,6 +17473,279 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT 
address, int do_pushes)
   return;
 }
 
+/* This function computes the clear mask and PADDING_BITS_TO_CLEAR for structs
+   and unions in the context of ARMv8-M Security Extensions.  It is used as a
+   helper function for both 'cmse_nonsecure_call' and 'cmse_nonsecure_entry'
+   functions.  The PADDING_BITS_TO_CLEAR pointer can be the base to either one
+   or four masks, depending on whether it is being computed for a
+   'cmse_nonsecure_entry' return value or a 'cmse_nonsecure_call' argument
+   respectively.  The tree for the type of the argument or a field within an
+   argument is passed in ARG_TYPE, the current register this argument or field
+   starts in is kept in the pointer REGNO and updated accordingly, the bit this
+   argument or field starts at is passed in STARTING_BIT and the last used bit
+   is kept in LAST_USED_BIT which is also updated accordingly.  */
+
+static unsigned HOST_WIDE_INT
+comp_not_to_clear_mask_str_un (tree arg_type, int * regno,
+  uint32_t * padding_bits_to_clear,
+  unsigned starting_bit, int * last_used_bit)
+
+{
+  unsigned HOST_WIDE_INT not_to_clear_reg_mask = 0;
+
+  if (TREE_CODE (arg_type) == RECORD_TYPE)
+{
+  unsigned current_bit = starting_bit;
+  tree field;
+  long int offset, size;
+
+
+  field = TYPE_FIELDS (arg_type);
+  while (field)
+   {
+ /* The offset within a structure is always an offset from
+the start of that structure.  Make sure we take that into the
+calculation of the register based offset that we use here.  */
+ offset = starting_bit;
+ offset += TREE_INT_CST_ELT (DECL_FIELD_BIT_OFFSET (field), 0);
+ offset %= 32;
+
+ /* This is the actual size of the field, for bitfields this is the
+bitfield width and not the container size.  */
+ size = TREE_INT_CST_ELT (DECL_SIZE (field), 0);
+
+ if (*last_used_bit != offset)
+   {
+ if (offset < *last_used_bit)
+   {
+ /* This field's 

[PATCH 7/7, GCC, ARM, V8M] Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic

[Andre Vieira (lists)]

This patch adds support ARMv8-M's Security Extension's
cmse_nonsecure_caller intrinsic. This intrinsic is used to check whether
an entry function was called from a non-secure state.
See Section 5.4.3 of ARM®v8-M Security Extensions: Requirements on
Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html)
for further details.

The FIXME in config/arm/arm_cmse.h is for a diagnostic message that is
suggested in the ARMv8-M Security Extensions document mentioned above,
to diagnose the use of the cmse_nonsecure_caller intrinsic outside of
functions with the 'cmse_nonsecure_entry' attribute.  Checking whether
the intrinsic is called from within such functions can easily be done
inside 'arm_expand_builtin'. However, making the warning point to the
right location is more complicated.  The ARMv8-M Security Extensions
specification does mention that such a diagnostic might become
mandatory, so I might have to pick this up later, otherwise it is left
as a potential extra feature.


*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm-builtins.c (arm_builtins): Define
ARM_BUILTIN_CMSE_NONSECURE_CALLER.
(bdesc_2arg): Add line for cmse_nonsecure_caller.
(arm_expand_builtin): Handle cmse_nonsecure_caller.
* config/arm/arm_cmse.h (cmse_nonsecure_caller): New.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-1.c: Add test for
cmse_nonsecure_caller.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
68b2839879f78e8d819444fbc11d2a91f8d6279a..2589ec2d1233f3daff94a1d35ebf63c8a9b93ecf
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -515,6 +515,8 @@ enum arm_builtins
   ARM_BUILTIN_GET_FPSCR,
   ARM_BUILTIN_SET_FPSCR,
 
+  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -1789,6 +1791,17 @@ arm_init_builtins (void)
= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
 }
+
+  if (arm_arch_cmse)
+{
+  tree ftype_cmse_nonsecure_caller
+   = build_function_type_list (unsigned_type_node, NULL);
+  arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
+   = add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
+   ftype_cmse_nonsecure_caller,
+   ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
+   NULL, NULL_TREE);
+}
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -2368,6 +2381,12 @@ arm_expand_builtin (tree exp,
   emit_insn (pat);
   return target;
 
+case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
+  target = gen_reg_rtx (SImode);
+  op0 = arm_return_addr (0, NULL_RTX);
+  emit_insn (gen_addsi3 (target, op0, const1_rtx));
+  return target;
+
 case ARM_BUILTIN_TEXTRMSB:
 case ARM_BUILTIN_TEXTRMUB:
 case ARM_BUILTIN_TEXTRMSH:
diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h
index 
c9afdcbf48160a963fc254795543a1d9e981a215..989d09f9d08268224e745da5a2e0aa85916cd3a9
 100644
--- a/gcc/config/arm/arm_cmse.h
+++ b/gcc/config/arm/arm_cmse.h
@@ -163,6 +163,13 @@ __attribute__ ((__always_inline__))
 cmse_TTAT (void *__p)
 __CMSE_TT_ASM (at)
 
+/* FIXME: diagnose use outside cmse_nonsecure_entry functions.  */
+__extension__ static __inline int __attribute__ ((__always_inline__))
+cmse_nonsecure_caller (void)
+{
+  return __builtin_arm_cmse_nonsecure_caller ();
+}
+
 #define CMSE_AU_NONSECURE  2
 #define CMSE_MPU_NONSECURE 16
 #define CMSE_NONSECURE 18
@@ -177,7 +184,7 @@ __extension__ void *
 cmse_check_address_range (void *, size_t, int);
 
 #define cmse_check_pointed_object(p, f) \
-  ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
+  ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
 
 #define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1))
 
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c 
b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
index 
d5b9a2d9d59569de170da814ae660e9fb2b943e7..ddcf12a30a6c1806969d239c448da81ccf49532e
 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
@@ -65,3 +65,32 @@ int foo (char * p)
 /* { dg-final { scan-assembler-times "ttat " 2 } } */
 /* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
 /* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
+
+typedef int (*int_ret_funcptr_t) (void);
+typedef int __attribute__ ((cmse_nonsecure_call)) (*int_ret_nsfuncptr_t) 
(void);
+
+int __attribute__ ((cmse_nonsecure_entry))
+baz (void)
+{
+  

[PATCH 3/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and bxns return

[Andre Vieira (lists)]

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute in two ways:

1) Generate two labels for the function, the regular function name and
one with the function's name appended to '__acle_se_', this will trigger
the linker to create a secure gateway veneer for this entry function.
2) Return from cmse_nonsecure_entry marked functions using bxns.

See Section 5.4 of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).


*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (use_return_insn): Change to return with  bxns
when cmse_nonsecure_entry.
(output_return_instruction): Likewise.
(arm_output_function_prologue): Likewise.
(thumb_pop): Likewise.
(thumb_exit): Likewise.
(arm_function_ok_for_sibcall): Disable sibcall for entry functions.
(arm_asm_declare_function_name): New.
* config/arm/arm-protos.h (arm_asm_declare_function_name): New.
* config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to
use arm_asm_declare_function_name.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-2.c: New.
* gcc.target/arm/cmse/cmse-4.c: New.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
0754fb7252a8b86ffacc0cee4598686752af6e56..1d2e35b52f631570450b6c8eaf077e18e9b99203
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -31,6 +31,7 @@ extern int arm_volatile_func (void);
 extern void arm_expand_prologue (void);
 extern void arm_expand_epilogue (bool);
 extern void arm_declare_function_name (FILE *, const char *, tree);
+extern void arm_asm_declare_function_name (FILE *, const char *, tree);
 extern void thumb2_expand_return (bool);
 extern const char *arm_strip_name_encoding (const char *);
 extern void arm_asm_output_labelref (FILE *, const char *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
11417ab3c2f7101866ee5d6b100913480e5c336e..9fba371768b1eba3a11dc8aa5d6acf8cc30f464d
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3866,6 +3866,11 @@ use_return_insn (int iscond, rtx sibling)
return 0;
 }
 
+  /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
+ several instructions if anything needs to be popped.  */
+  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
+return 0;
+
   /* If there are saved registers but the LR isn't saved, then we need
  two instructions for the return.  */
   if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
@@ -6903,6 +6908,11 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
   if (IS_INTERRUPT (func_type))
 return false;
 
+  /* ARMv8-M non-secure entry functions need to return with bxns which is only
+ generated for entry functions themselves.  */
+  if (IS_CMSE_ENTRY (arm_current_func_type ()))
+return false;
+
   if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl
 {
   /* Check that the return value locations are the same.  For
@@ -19739,6 +19749,7 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
 (e.g. interworking) then we can load the return address
 directly into the PC.  Otherwise we must load it into LR.  */
   if (really_return
+ && !IS_CMSE_ENTRY (func_type)
  && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
return_reg = reg_names[PC_REGNUM];
   else
@@ -19879,8 +19890,10 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
  break;
 
default:
+ if (IS_CMSE_ENTRY (func_type))
+   snprintf (instr, sizeof (instr), "bxns%s\t%%|lr", conditional);
  /* Use bx if it's available.  */
- if (arm_arch5 || arm_arch4t)
+ else if (arm_arch5 || arm_arch4t)
sprintf (instr, "bx%s\t%%|lr", conditional);
  else
sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
@@ -19893,6 +19906,42 @@ output_return_instruction (rtx operand, bool 
really_return, bool reverse,
   return "";
 }
 
+/* Output in FILE asm statements needed to declare the NAME of the function
+   defined by its DECL node.  */
+
+void
+arm_asm_declare_function_name (FILE *file, const char *name, tree decl)
+{
+  size_t cmse_name_len;
+  char *cmse_name = 0;
+  char cmse_prefix[] = "__acle_se_";
+
+  if (use_cmse && lookup_attribute ("cmse_nonsecure_entry",
+   DECL_ATTRIBUTES (decl)))
+{
+  cmse_name_len = sizeof (cmse_prefix) + strlen (name);
+  cmse_name = XALLOCAVEC (char, cmse_name_len);
+  snprintf (cmse_name, cmse_name_len, "%s%s", cmse_prefix, name);
+  

[PATCH 6/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call

[Andre Vieira (lists)]

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_call' to use a new library function
'__gnu_cmse_nonsecure_call'. This library function is responsible for
(without using r0-r3 or d0-d7):
1) saving and clearing all callee-saved registers using the secure stack
2) clearing the LSB of the address passed in r4 and using blxns to
'jump' to it
3) clearing ASPR, including the 'ge bits' if DSP is enabled
4) clearing FPSCR if using non-soft float-abi
5) restoring callee-saved registers.

The decisions whether to include DSP 'ge bits' clearing and floating
point registers (single/double precision) all depends on the multilib used.

See Section 5.5 of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (detect_cmse_nonsecure_call): New.
(cmse_nonsecure_call_clear_caller_saved): New.
(arm_reorg): Use cmse_nonsecure_call_clear_caller_saved.
* config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
* config/arm/arm.md (call): Handle cmse_nonsecure_entry.
(call_value): Likewise.
(nonsecure_call_internal): New.
(nonsecure_call_value_internal): New.
* config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
(*nonsecure_call_value_reg_thumb1_v5): New.
* config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
(*nonsecure_call_value_reg_thumb2): New.
* config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.

*** libgcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/cmse_nonsecure_call.S: New.
* config/arm/t-arm: Compile cmse_nonsecure_call.S


*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir.
* gcc.target/arm/cmse/cmse-9.c: Added some extra tests.
* gcc.target/arm/cmse/baseline/bitfield-4.c: New.
* gcc.target/arm/cmse/baseline/bitfield-5.c: New.
* gcc.target/arm/cmse/baseline/bitfield-6.c: New.
* gcc.target/arm/cmse/baseline/bitfield-7.c: New.
* gcc.target/arm/cmse/baseline/bitfield-8.c: New.
* gcc.target/arm/cmse/baseline/bitfield-9.c: New.
* gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New.
* gcc.target/arm/cmse/baseline/cmse-11.c: New.
* gcc.target/arm/cmse/baseline/cmse-13.c: New.
* gcc.target/arm/cmse/baseline/cmse-6.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/union-1.c: New.
* gcc/testsuite/gcc.target/arm/cmse/baseline/union-2.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
1d2e35b52f631570450b6c8eaf077e18e9b99203..e7e223f7a932163cba8beeb76c10b4c90eae9234
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -133,6 +133,7 @@ extern int arm_const_double_inline_cost (rtx);
 extern bool arm_const_double_by_parts (rtx);
 extern bool arm_const_double_by_immediates (rtx);
 extern void arm_emit_call_insn (rtx, rtx, bool);
+bool detect_cmse_nonsecure_call (tree);
 extern const char *output_call (rtx *);
 void arm_emit_movpair (rtx, rtx);
 extern const char *output_mov_long_double_arm_from_arm (rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
128baae92e4b65507eb18b679874b1ad24ca7c4a..fd0bc10083026ce544bf56244ce0eb740295e5d3
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -17822,6 +17822,197 @@ compute_not_to_clear_mask (tree arg_type, rtx 
arg_rtx, int regno,
   return not_to_clear_mask;
 }
 
+/* Saves callee saved registers, clears callee saved registers and caller saved
+   registers not used to pass arguments before a cmse_nonsecure_call.  And
+   restores the callee saved registers after.  */
+
+static void

[PATCH 5/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute

[Andre Vieira (lists)]

This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_call' attribute. This attribute may only be used for
function types and when used in combination with the '-mcmse'
compilation flag. See Section 5.5 of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently do not support cmse_nonsecure_call functions that pass
arguments or return variables on the stack and we diagnose this.

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/arm.c (gimplify.h): New include.
(arm_handle_cmse_nonsecure_call): New.
(arm_attribute_table): Added cmse_nonsecure_call.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse-3.c: Add tests.
* gcc.target/arm/cmse/cmse-4.c: Add tests.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
81a9d9a6fb29d0956a661734d60dd2e44cb554b8..128baae92e4b65507eb18b679874b1ad24ca7c4a
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -61,6 +61,7 @@
 #include "builtins.h"
 #include "tm-constrs.h"
 #include "rtl-iter.h"
+#include "gimplify.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -135,6 +136,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
 static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
+static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -347,6 +349,8 @@ static const struct attribute_spec arm_attribute_table[] =
   /* ARMv8-M Security Extensions support.  */
   { "cmse_nonsecure_entry", 0, 0, true, false, false,
 arm_handle_cmse_nonsecure_entry, false },
+  { "cmse_nonsecure_call", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_call, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -6750,6 +6754,78 @@ arm_handle_cmse_nonsecure_entry (tree *node, tree name,
   return NULL_TREE;
 }
 
+
+/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
+   function will check whether the attribute is allowed here and will add the
+   attribute to the function type tree or otherwise issue a diagnostic.  The
+   reason we check this at declaration time is to only allow the use of the
+   attribute with declarations of function pointers and not function
+   declarations.  This function checks NODE is of the expected type and issues
+   diagnostics otherwise using NAME.  If it is not of the expected type
+   *NO_ADD_ATTRS will be set to true.  */
+
+static tree
+arm_handle_cmse_nonsecure_call (tree *node, tree name,
+tree /* args */,
+int /* flags */,
+bool *no_add_attrs)
+{
+  tree decl = NULL_TREE;
+  tree type, fntype, main_variant;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}
+
+  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
+{
+  decl = *node;
+  type = TREE_TYPE (decl);
+}
+
+  if (!decl
+  || (!(TREE_CODE (type) == POINTER_TYPE
+   && TREE_CODE (TREE_TYPE (type)) == FUNCTION_TYPE)
+ && TREE_CODE (type) != FUNCTION_TYPE))
+{
+   warning (OPT_Wattributes, "%qE attribute only applies to base type of a 
"
+"function pointer", name);
+   *no_add_attrs = true;
+   return NULL_TREE;
+}
+
+  /* type is either a function pointer, when the attribute is used on a 
function
+   * pointer, or a function type when used in a typedef.  */
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+fntype = type;
+  else
+fntype = TREE_TYPE (type);
+
+  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
+
+  if (*no_add_attrs)
+return NULL_TREE;
+
+  /* Prevent trees being shared among function types with and without
+ cmse_nonsecure_call attribute.  Do however make sure they keep the same
+ main_variant, this is required for correct DIE output.  */
+  main_variant = TYPE_MAIN_VARIANT (fntype);
+  fntype = build_distinct_type_copy (fntype);
+  TYPE_MAIN_VARIANT (fntype) = main_variant;
+  if (TREE_CODE (type) == FUNCTION_TYPE)
+TREE_TYPE (decl) = fntype;
+  else
+TREE_TYPE (type) = fntype;
+
+  /* Construct a type attribute and add it to the function type.  */
+  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
+ TYPE_ATTRIBUTES (fntype));
+  TYPE_ATTRIBUTES 

[PATCH 1/7, GCC, ARM, V8M] Add support for ARMv8-M's Secure Extensions flag and intrinsics

[Andre Vieira (lists)]

This patch adds the support of the '-mcmse' option to enable ARMv8-M's
Security Extensions and supports the following intrinsics:
cmse_TT
cmse_TT_fptr
cmse_TTT
cmse_TTT_fptr
cmse_TTA
cmse_TTA_fptr
cmse_TTAT
cmse_TTAT_fptr
cmse_check_address_range
cmse_check_pointed_object
cmse_is_nsfptr
cmse_nsfptr_create

It also defines the mandatory cmse_address_info struct and the
__ARM_FEATURE_CMSE macro.
See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
Extensions: Requirements on Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config.gcc (extra_headers): Added arm_cmse.h.
* config/arm/arm-arches.def (ARM_ARCH):
(armv8-m): Add FL2_CMSE.
(armv8-m.main): Likewise.
(armv8-m.main+dsp): Likewise.
* config/arm/arm-c.c
(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
* config/arm/arm-protos.h
(arm_is_constant_pool_ref): Define FL2_CMSE.
* config/arm.c (arm_arch_cmse): New.
(arm_option_override): New error for unsupported cmse target.
* config/arm/arm.h (arm_arch_cmse): New.
* config/arm/arm.opt (mcmse): New.
* doc/invoke.texi (ARM Options): Add -mcmse.
* config/arm/arm_cmse.h: New file.

*** libgcc/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* config/arm/cmse.c: Likewise.
* config/arm/t-arm (HAVE_CMSE): New.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
Thomas Preud'homme  

* gcc.target/arm/cmse/cmse.exp: New.
* gcc.target/arm/cmse/cmse-1.c: New.
* gcc.target/arm/cmse/cmse-12.c: New.
* lib/target-supports.exp
(check_effective_target_arm_cmse_ok): New.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 
1f75f17877334c2bb61cd16b69539ec7514db8ae..8555bbf19d81b517493c86b38aff31a633ac50eb
 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -320,7 +320,7 @@ arc*-*-*)
 arm*-*-*)
cpu_type=arm
extra_objs="arm-builtins.o aarch-common.o"
-   extra_headers="mmintrin.h arm_neon.h arm_acle.h"
+   extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_cmse.h"
target_type_format_char='%'
c_target_objs="arm-c.o"
cxx_target_objs="arm-c.o"
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 
be46521c9eaea54f9ad78a92874567589289dbdf..0e523959551cc3b1da31411ccdd1105b830db845
 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -63,11 +63,11 @@ ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
 FL2_FOR_ARCH8_1A))
 ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,
-ARM_FSET_MAKE_CPU1 ( FL_FOR_ARCH8M_BASE))
+ARM_FSET_MAKE (  FL_FOR_ARCH8M_BASE, FL2_CMSE))
 ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
-ARM_FSET_MAKE_CPU1(FL_CO_PROC |  FL_FOR_ARCH8M_MAIN))
+ARM_FSET_MAKE (FL_CO_PROC |  FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("armv8-m.main+dsp", cortexm7, 8M_MAIN,
-ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN))
+ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
 ARM_ARCH("iwmmxt",  iwmmxt, 5TE,   ARM_FSET_MAKE_CPU1 (FL_LDSCHED | 
FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,5TE,   ARM_FSET_MAKE_CPU1 (FL_LDSCHED | 
FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
 
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 
b98470fff45b20a5398c2534bc3bb3edfb7bfd01..ad2fb09d1f9ca14300c6283f3831a527db656267
 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -76,6 +76,14 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 
   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
 
+  if (arm_arch8 && !arm_arch_notm)
+{
+  if (arm_arch_cmse && use_cmse)
+   builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);
+  else
+   builtin_define ("__ARM_FEATURE_CMSE");
+}
+
   if (TARGET_ARM_FEATURE_LDREX)
 builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
   TARGET_ARM_FEATURE_LDREX);
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 
49c3a92dba80db32b698a0b44ad72d56111c1358..0754fb7252a8b86ffacc0cee4598686752af6e56
 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -391,6 +391,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_ARCH6KZ(1 << 31)   /* ARMv6KZ architecture.  */
 
 #define FL2_ARCH8_1   (1 << 0)   /* Architecture 8.1.  */

Re: [PATCHv2, PING 2][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 25/07/16 11:52, Andre Vieira (lists) wrote:
> On 11/07/16 17:56, Andre Vieira (lists) wrote:
>> On 07/07/16 13:30, mickael guene wrote:
>>> Hi Andre,
>>>
>>>  Another feedback on your purecode patch.
>>>  You have to disable casesi pattern since then it will
>>> generate wrong code with -mpure-code option.
>>>  Indeed it will generate an 'adr rx, .Lx' (aka
>>> 'subs rx, PC, #offset') which will not work in our
>>> case since 'Lx' label is put in an .rodata section.
>>> So offset value is unknown and can be impossible
>>> to encode correctly.
>>>
>>> Regards
>>> Mickael
>>>
>>> On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:
>>>> Hello,
>>>>
>>>> This patch adds the -mpure-code option for ARM. This option ensures
>>>> functions are put into sections that contain only code and no data. To
>>>> ensure this throughout compilation we give these sections the ARM
>>>> processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
>>>> is only supported for non-pic code for armv7-m targets.
>>>>
>>>> This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
>>>> This target hook enables a target to use the numeric value for elf
>>>> section attributes rather than their alphabetical representation. If
>>>> TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
>>>> 'default_elf_asm_named_section', will print the numeric value of the
>>>> section attributes for the current section. This target hook has two
>>>> parameters:
>>>> unsigned int FLAGS, the input parameter that tells the function the
>>>> current section's attributes;
>>>> unsigned int *NUM, used to pass down the numerical representation of the
>>>> section's attributes.
>>>>
>>>> The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
>>>> false, so existing behavior is not changed.
>>>>
>>>> Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
>>>> arm-none-eabi with a Cortex-M3 target.
>>>>
>>>>
>>>> gcc/ChangeLog:
>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>> Terry Guo  <terry@arm.com>
>>>>
>>>> * target.def (elf_flags_numeric): New target hook.
>>>> * targhooks.h (default_asm_elf_flags_numeric): New.
>>>> * varasm.c (default_asm_elf_flags_numeric): New.
>>>>   (default_elf_asm_named_section): Use new target hook.
>>>> * config/arm/arm.opt (mpure-code): New.
>>>> * config/arm/arm.h (SECTION_ARM_PURECODE): New.
>>>> * config/arm/arm.c (arm_asm_init_sections): Add section
>>>>   attribute to default text section if -mpure-code.
>>>>   (arm_option_check_internal): Diagnose use of option with
>>>>   non supported targets and/or options.
>>>>   (arm_asm_elf_flags_numeric): New.
>>>>   (arm_function_section): New.
>>>>   (arm_elf_section_type_flags): New.
>>>> * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
>>>>   for -mpure-code.
>>>> * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
>>>> * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.
>>>>
>>>>
>>>>
>>>> gcc/testsuite/ChangeLog:
>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>> Terry Guo  <terry@arm.com>
>>>>
>>>> * gcc.target/arm/pure-code/ffunction-sections.c: New.
>>>> * gcc.target/arm/pure-code/no-literal-pool.c: New.
>>>> * gcc.target/arm/pure-code/pure-code.exp: New.
>>>>
>>>
>> Hi Sandra, Mickael,
>>
>> Thank you for your comments. I changed the description of -mpure-code in
>> invoke.texi to better reflect the error message you get wrt supported
>> targets.
>>
>> As for the target hook description, I hope the text is clearer now. Let
>> me know if you think it needs further explanation.
>>
>> I also fixed the double '%' in the text string for unnamed text sections
>> and disabled the casesi pattern.
>>
>> I duplicated the original casesi test
>> 'gcc/testsuite/gcc.c-torture/compile/pr46934.c' for pure-code to m

Re: [PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions

[Andre Vieira (lists)]

On 09/08/16 17:47, Sandra Loosemore wrote:
> On 08/09/2016 06:01 AM, Andre Vieira (lists) wrote:
>> [snip]
>>
>> The documentation is in the ARMV8-M Security Extensions in: ARM®v8-M
>> Security Extensions: Requirements on Development Tools document I linked
>> in the email above and subsequent emails
>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
>>
>> Also per patch I refer to the relevant sections. So for instance in
>> PATCH 3/7 refers to Section 5.4, which describes Entry functions and
>> mentions the cmse_nonsecure_entry attribute. Whereas PATCH 7/7 refers to
>> Section 5.4.3 of the same document which describes the
>> cmse_nonsecure_caller intrinsic which that patch implements.
>>
>> Is there a specific intrinsic/attribute you are missing?
> 
> You need to at least add entries to the relevant sections in extend.texi
> for the new target-specific intrinsic and attributes.  The documentation
> there doesn't need to be terribly detailed (one sentence and a link to
> the external document is probably all you need), but it's important that
> these things be listed in GCC's supported extensions so that users know
> they can use them and so that people who see them in code written by
> other people can find out what they mean.
> 
> -Sandra
> 


I see, I did add a new entry to extend.texi for ARMv8-M Security
Extensions. I will also mention all intrinsics and attributes there.

Thank you.

Andre

Re: [PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

On 11/07/16 18:09, Andre Vieira (lists) wrote:
> On 06/07/16 11:52, Andre Vieira (lists) wrote:
>> On 01/07/16 14:40, Ramana Radhakrishnan wrote:
>>>
>>>
>>> On 13/10/15 18:01, Andre Vieira wrote:
>>>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings 
>>>> (https://git.linaro.org/toolchain/cortex-strings.git), which was 
>>>> contributed by ARM under Free BSD license.
>>>>
>>>> The new aeabi_idiv routine is used to replace the one in 
>>>> libgcc/config/arm/lib1funcs.S. This replacement happens within the Thumb1 
>>>> wrapper. The new routine is under LGPLv3 license.
>>>
>>> This is not under LGPLv3 . It is under GPLv3 with the runtime library 
>>> exception license, there's a difference. Assuming your licensing 
>>> expectation is ok  read on for more of a review.
>>>
>>>>
>>>> The main advantage of this version is that it can improve the performance 
>>>> of the aeabi_idiv function for Thumb1. This solution will also increase 
>>>> the code size. So it will only be used if __OPTIMIZE_SIZE__ is not defined.
>>>>
>>>> Make check passed for armv6-m.
>>>>
>>>> libgcc/ChangeLog:
>>>> 2015-08-10  Hale Wang  <hale.w...@arm.com>
>>>> Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>
>>>>   * config/arm/lib1funcs.S: Add new wrapper.
>>>>
>>>> 0001-integer-division.patch
>>>>
>>>>
>>>> From 832a3d6af6f06399f70b5a4ac3727d55960c93b7 Mon Sep 17 00:00:00 2001
>>>> From: Andre Simoes Dias Vieira <andsi...@arm.com>
>>>> Date: Fri, 21 Aug 2015 14:23:28 +0100
>>>> Subject: [PATCH] new wrapper idivmod
>>>>
>>>> ---
>>>>  libgcc/config/arm/lib1funcs.S | 250 
>>>> --
>>>>  1 file changed, 217 insertions(+), 33 deletions(-)
>>>>
>>>> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
>>>> index 
>>>> 252efcbd5385cc58a5ce1e48c6816d36a6f4c797..c9e544114590da8cde88382bea0f67206e593816
>>>>  100644
>>>> --- a/libgcc/config/arm/lib1funcs.S
>>>> +++ b/libgcc/config/arm/lib1funcs.S
>>>> @@ -306,34 +306,12 @@ LSYM(Lend_fde):
>>>>  #ifdef __ARM_EABI__
>>>>  .macro THUMB_LDIV0 name signed
>>>>  #if defined(__ARM_ARCH_6M__)
>>>> -  .ifc \signed, unsigned
>>>> -  cmp r0, #0
>>>> -  beq 1f
>>>> -  mov r0, #0
>>>> -  mvn r0, r0  @ 0x
>>>> -1:
>>>> -  .else
>>>> -  cmp r0, #0
>>>> -  beq 2f
>>>> -  blt 3f
>>>> +
>>>> +  push{r0, lr}
>>>>mov r0, #0
>>>> -  mvn r0, r0
>>>> -  lsr r0, r0, #1  @ 0x7fff
>>>> -  b   2f
>>>> -3:mov r0, #0x80
>>>> -  lsl r0, r0, #24 @ 0x8000
>>>> -2:
>>>> -  .endif
>>>> -  push{r0, r1, r2}
>>>> -  ldr r0, 4f
>>>> -  adr r1, 4f
>>>> -  add r0, r1
>>>> -  str r0, [sp, #8]
>>>> -  @ We know we are not on armv4t, so pop pc is safe.
>>>> -  pop {r0, r1, pc}
>>>> -  .align  2
>>>> -4:
>>>> -  .word   __aeabi_idiv0 - 4b
>>>> +  bl  SYM(__aeabi_idiv0)
>>>> +  pop {r1, pc}
>>>> +
>>>
>>> I'd still retain the comment about pop pc here because there's often a 
>>> misconception of merging armv4t and armv6m code.
>>>
>>>>  #elif defined(__thumb2__)
>>>>.syntax unified
>>>>.ifc \signed, unsigned
>>>> @@ -945,7 +923,170 @@ LSYM(Lover7):
>>>>add dividend, work
>>>>.endif
>>>>  LSYM(Lgot_result):
>>>> -.endm 
>>>> +.endm
>>>> +
>>>> +#if defined(__prefer_thumb__) && !defined(__OPTIMIZE_SIZE__)
>>>> +/* If performance is preferred, the following functions are provided.  */
>>>> +
>>>
>>> Comment above #if please and also check elsewhere in patch.
>>>
>>>> +/* Branch to div(n), and jump to label if curbit is lo than divisior.  */
>>>> +.macro BranchToDiv n, label
>>>> +  lsr curbit, dividend, \n
>>>> +  cmp curb

Re: [PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

On 01/07/16 14:40, Ramana Radhakrishnan wrote:
> 
> 
> On 13/10/15 18:01, Andre Vieira wrote:
>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings 
>> (https://git.linaro.org/toolchain/cortex-strings.git), which was contributed 
>> by ARM under Free BSD license.
>>
>> The new aeabi_idiv routine is used to replace the one in 
>> libgcc/config/arm/lib1funcs.S. This replacement happens within the Thumb1 
>> wrapper. The new routine is under LGPLv3 license.
> 
> This is not under LGPLv3 . It is under GPLv3 with the runtime library 
> exception license, there's a difference. Assuming your licensing expectation 
> is ok  read on for more of a review.
> 
>>
>> The main advantage of this version is that it can improve the performance of 
>> the aeabi_idiv function for Thumb1. This solution will also increase the 
>> code size. So it will only be used if __OPTIMIZE_SIZE__ is not defined.
>>
>> Make check passed for armv6-m.
>>
>> libgcc/ChangeLog:
>> 2015-08-10  Hale Wang  
>> Andre Vieira  
>>
>>   * config/arm/lib1funcs.S: Add new wrapper.
>>
>> 0001-integer-division.patch
>>
>>
>> From 832a3d6af6f06399f70b5a4ac3727d55960c93b7 Mon Sep 17 00:00:00 2001
>> From: Andre Simoes Dias Vieira 
>> Date: Fri, 21 Aug 2015 14:23:28 +0100
>> Subject: [PATCH] new wrapper idivmod
>>
>> ---
>>  libgcc/config/arm/lib1funcs.S | 250 
>> --
>>  1 file changed, 217 insertions(+), 33 deletions(-)
>>
>> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
>> index 
>> 252efcbd5385cc58a5ce1e48c6816d36a6f4c797..c9e544114590da8cde88382bea0f67206e593816
>>  100644
>> --- a/libgcc/config/arm/lib1funcs.S
>> +++ b/libgcc/config/arm/lib1funcs.S
>> @@ -306,34 +306,12 @@ LSYM(Lend_fde):
>>  #ifdef __ARM_EABI__
>>  .macro THUMB_LDIV0 name signed
>>  #if defined(__ARM_ARCH_6M__)
>> -.ifc \signed, unsigned
>> -cmp r0, #0
>> -beq 1f
>> -mov r0, #0
>> -mvn r0, r0  @ 0x
>> -1:
>> -.else
>> -cmp r0, #0
>> -beq 2f
>> -blt 3f
>> +
>> +push{r0, lr}
>>  mov r0, #0
>> -mvn r0, r0
>> -lsr r0, r0, #1  @ 0x7fff
>> -b   2f
>> -3:  mov r0, #0x80
>> -lsl r0, r0, #24 @ 0x8000
>> -2:
>> -.endif
>> -push{r0, r1, r2}
>> -ldr r0, 4f
>> -adr r1, 4f
>> -add r0, r1
>> -str r0, [sp, #8]
>> -@ We know we are not on armv4t, so pop pc is safe.
>> -pop {r0, r1, pc}
>> -.align  2
>> -4:
>> -.word   __aeabi_idiv0 - 4b
>> +bl  SYM(__aeabi_idiv0)
>> +pop {r1, pc}
>> +
> 
> I'd still retain the comment about pop pc here because there's often a 
> misconception of merging armv4t and armv6m code.
> 
>>  #elif defined(__thumb2__)
>>  .syntax unified
>>  .ifc \signed, unsigned
>> @@ -945,7 +923,170 @@ LSYM(Lover7):
>>  add dividend, work
>>.endif
>>  LSYM(Lgot_result):
>> -.endm   
>> +.endm
>> +
>> +#if defined(__prefer_thumb__) && !defined(__OPTIMIZE_SIZE__)
>> +/* If performance is preferred, the following functions are provided.  */
>> +
> 
> Comment above #if please and also check elsewhere in patch.
> 
>> +/* Branch to div(n), and jump to label if curbit is lo than divisior.  */
>> +.macro BranchToDiv n, label
>> +lsr curbit, dividend, \n
>> +cmp curbit, divisor
>> +blo \label
>> +.endm
>> +
>> +/* Body of div(n).  Shift the divisor in n bits and compare the divisor
>> +   and dividend.  Update the dividend as the substruction result.  */
>> +.macro DoDiv n
>> +lsr curbit, dividend, \n
>> +cmp curbit, divisor
>> +bcc 1f
>> +lsl curbit, divisor, \n
>> +sub dividend, dividend, curbit
>> +
>> +1:  adc result, result
>> +.endm
>> +
>> +/* The body of division with positive divisor.  Unless the divisor is very
>> +   big, shift it up in multiples of four bits, since this is the amount of
>> +   unwinding in the main division loop.  Continue shifting until the divisor
>> +   is larger than the dividend.  */
>> +.macro THUMB1_Div_Positive
>> +mov result, #0
>> +BranchToDiv #1, LSYM(Lthumb1_div1)
>> +BranchToDiv #4, LSYM(Lthumb1_div4)
>> +BranchToDiv #8, LSYM(Lthumb1_div8)
>> +BranchToDiv #12, LSYM(Lthumb1_div12)
>> +BranchToDiv #16, LSYM(Lthumb1_div16)
>> +LSYM(Lthumb1_div_large_positive):
>> +mov result, #0xff
>> +lsl divisor, divisor, #8
>> +rev result, result
>> +lsr curbit, dividend, #16
>> +cmp curbit, divisor
>> +blo 1f
>> +asr result, #8
>> +lsl divisor, divisor, #8
>> +beq LSYM(Ldivbyzero_waypoint)
>> +
>> +1:  lsr curbit, dividend, #12
>> +cmp curbit, divisor
>> +blo LSYM(Lthumb1_div12)
>> +b   LSYM(Lthumb1_div16)
>> +LSYM(Lthumb1_div_loop):
>> +lsr divisor, divisor, 

[PATCHv2][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 07/07/16 13:30, mickael guene wrote:
> Hi Andre,
> 
>  Another feedback on your purecode patch.
>  You have to disable casesi pattern since then it will
> generate wrong code with -mpure-code option.
>  Indeed it will generate an 'adr rx, .Lx' (aka
> 'subs rx, PC, #offset') which will not work in our
> case since 'Lx' label is put in an .rodata section.
> So offset value is unknown and can be impossible
> to encode correctly.
> 
> Regards
> Mickael
> 
> On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:
>> Hello,
>>
>> This patch adds the -mpure-code option for ARM. This option ensures
>> functions are put into sections that contain only code and no data. To
>> ensure this throughout compilation we give these sections the ARM
>> processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
>> is only supported for non-pic code for armv7-m targets.
>>
>> This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
>> This target hook enables a target to use the numeric value for elf
>> section attributes rather than their alphabetical representation. If
>> TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
>> 'default_elf_asm_named_section', will print the numeric value of the
>> section attributes for the current section. This target hook has two
>> parameters:
>> unsigned int FLAGS, the input parameter that tells the function the
>> current section's attributes;
>> unsigned int *NUM, used to pass down the numerical representation of the
>> section's attributes.
>>
>> The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
>> false, so existing behavior is not changed.
>>
>> Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
>> arm-none-eabi with a Cortex-M3 target.
>>
>>
>> gcc/ChangeLog:
>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>> Terry Guo  <terry@arm.com>
>>
>> * target.def (elf_flags_numeric): New target hook.
>> * targhooks.h (default_asm_elf_flags_numeric): New.
>> * varasm.c (default_asm_elf_flags_numeric): New.
>>   (default_elf_asm_named_section): Use new target hook.
>> * config/arm/arm.opt (mpure-code): New.
>> * config/arm/arm.h (SECTION_ARM_PURECODE): New.
>> * config/arm/arm.c (arm_asm_init_sections): Add section
>>   attribute to default text section if -mpure-code.
>>   (arm_option_check_internal): Diagnose use of option with
>>   non supported targets and/or options.
>>   (arm_asm_elf_flags_numeric): New.
>>   (arm_function_section): New.
>>   (arm_elf_section_type_flags): New.
>> * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
>>   for -mpure-code.
>> * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
>> * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.
>>
>>
>>
>> gcc/testsuite/ChangeLog:
>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>> Terry Guo  <terry@arm.com>
>>
>> * gcc.target/arm/pure-code/ffunction-sections.c: New.
>> * gcc.target/arm/pure-code/no-literal-pool.c: New.
>> * gcc.target/arm/pure-code/pure-code.exp: New.
>>
> 
Hi Sandra, Mickael,

Thank you for your comments. I changed the description of -mpure-code in
invoke.texi to better reflect the error message you get wrt supported
targets.

As for the target hook description, I hope the text is clearer now. Let
me know if you think it needs further explanation.

I also fixed the double '%' in the text string for unnamed text sections
and disabled the casesi pattern.

I duplicated the original casesi test
'gcc/testsuite/gcc.c-torture/compile/pr46934.c' for pure-code to make
sure the casesi was disabled and other patterns were selected instead.

Reran regressions for pure-code.exp for Cortex-M3.

Cheers,
Andre


gcc/ChangeLog:
2016-07-11  Andre Vieira  <andre.simoesdiasvie...@arm.com>
Terry Guo  <terry@arm.com>

* target.def (elf_flags_numeric): New target hook.
* hooks.c (hook_uint_uintp_false): New generic hook.
* varasm.c (default_elf_asm_named_section): Use new target hook.
* config/arm/arm.opt (mpure-code): New.
* config/arm/arm.h (SECTION_ARM_PURECODE): New.
* config/arm/arm.c (arm_asm_init_sections): Add section
attribute to default text section if -mpure-code.
(arm_option_check_internal): Diagnose use of option with
non supported targets and/or options.
(arm_asm_elf_fla

Re: [PATCHv2, ARM, libgcc] New aeabi_idiv function for armv6-m

[Andre Vieira (lists)]

On 06/07/16 11:52, Andre Vieira (lists) wrote:
> On 01/07/16 14:40, Ramana Radhakrishnan wrote:
>>
>>
>> On 13/10/15 18:01, Andre Vieira wrote:
>>> This patch ports the aeabi_idiv routine from Linaro Cortex-Strings 
>>> (https://git.linaro.org/toolchain/cortex-strings.git), which was 
>>> contributed by ARM under Free BSD license.
>>>
>>> The new aeabi_idiv routine is used to replace the one in 
>>> libgcc/config/arm/lib1funcs.S. This replacement happens within the Thumb1 
>>> wrapper. The new routine is under LGPLv3 license.
>>
>> This is not under LGPLv3 . It is under GPLv3 with the runtime library 
>> exception license, there's a difference. Assuming your licensing expectation 
>> is ok  read on for more of a review.
>>
>>>
>>> The main advantage of this version is that it can improve the performance 
>>> of the aeabi_idiv function for Thumb1. This solution will also increase the 
>>> code size. So it will only be used if __OPTIMIZE_SIZE__ is not defined.
>>>
>>> Make check passed for armv6-m.
>>>
>>> libgcc/ChangeLog:
>>> 2015-08-10  Hale Wang  <hale.w...@arm.com>
>>> Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>
>>>   * config/arm/lib1funcs.S: Add new wrapper.
>>>
>>> 0001-integer-division.patch
>>>
>>>
>>> From 832a3d6af6f06399f70b5a4ac3727d55960c93b7 Mon Sep 17 00:00:00 2001
>>> From: Andre Simoes Dias Vieira <andsi...@arm.com>
>>> Date: Fri, 21 Aug 2015 14:23:28 +0100
>>> Subject: [PATCH] new wrapper idivmod
>>>
>>> ---
>>>  libgcc/config/arm/lib1funcs.S | 250 
>>> --
>>>  1 file changed, 217 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
>>> index 
>>> 252efcbd5385cc58a5ce1e48c6816d36a6f4c797..c9e544114590da8cde88382bea0f67206e593816
>>>  100644
>>> --- a/libgcc/config/arm/lib1funcs.S
>>> +++ b/libgcc/config/arm/lib1funcs.S
>>> @@ -306,34 +306,12 @@ LSYM(Lend_fde):
>>>  #ifdef __ARM_EABI__
>>>  .macro THUMB_LDIV0 name signed
>>>  #if defined(__ARM_ARCH_6M__)
>>> -   .ifc \signed, unsigned
>>> -   cmp r0, #0
>>> -   beq 1f
>>> -   mov r0, #0
>>> -   mvn r0, r0  @ 0x
>>> -1:
>>> -   .else
>>> -   cmp r0, #0
>>> -   beq 2f
>>> -   blt 3f
>>> +
>>> +   push{r0, lr}
>>> mov r0, #0
>>> -   mvn r0, r0
>>> -   lsr r0, r0, #1  @ 0x7fff
>>> -   b   2f
>>> -3: mov r0, #0x80
>>> -   lsl r0, r0, #24 @ 0x8000
>>> -2:
>>> -   .endif
>>> -   push{r0, r1, r2}
>>> -   ldr r0, 4f
>>> -   adr r1, 4f
>>> -   add r0, r1
>>> -   str r0, [sp, #8]
>>> -   @ We know we are not on armv4t, so pop pc is safe.
>>> -   pop {r0, r1, pc}
>>> -   .align  2
>>> -4:
>>> -   .word   __aeabi_idiv0 - 4b
>>> +   bl  SYM(__aeabi_idiv0)
>>> +   pop {r1, pc}
>>> +
>>
>> I'd still retain the comment about pop pc here because there's often a 
>> misconception of merging armv4t and armv6m code.
>>
>>>  #elif defined(__thumb2__)
>>> .syntax unified
>>> .ifc \signed, unsigned
>>> @@ -945,7 +923,170 @@ LSYM(Lover7):
>>> add dividend, work
>>>.endif
>>>  LSYM(Lgot_result):
>>> -.endm  
>>> +.endm
>>> +
>>> +#if defined(__prefer_thumb__) && !defined(__OPTIMIZE_SIZE__)
>>> +/* If performance is preferred, the following functions are provided.  */
>>> +
>>
>> Comment above #if please and also check elsewhere in patch.
>>
>>> +/* Branch to div(n), and jump to label if curbit is lo than divisior.  */
>>> +.macro BranchToDiv n, label
>>> +   lsr curbit, dividend, \n
>>> +   cmp curbit, divisor
>>> +   blo \label
>>> +.endm
>>> +
>>> +/* Body of div(n).  Shift the divisor in n bits and compare the divisor
>>> +   and dividend.  Update the dividend as the substruction result.  */
>>> +.macro DoDiv n
>>> +   lsr curbit, dividend, \n
>>> +   cmp curbit, divisor
>>> +   bcc 1f
>>> +   lsl curbit, divisor, \n
>>> +   sub

Re: [PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions

[Andre Vieira (lists)]

On 08/08/16 05:19, Sandra Loosemore wrote:
> On 07/25/2016 07:17 AM, Andre Vieira (lists) wrote:
>> [PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions
>>
>> Hello,
>>
>> This is a respin of a previous patch series for ARMv8-M Security
>> Extensions. In this version I have removed one patch, rebased the rest
>> and changed some of them.
>>
>> This patch series aims at implementing support for ARMv8-M's Security
>> Extensions. You can find the specification of ARMV8-M Security
>> Extensions in: ARM®v8-M Security Extensions: Requirements on Development
>> Tools
>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
>>
>> We currently:
>> - do not support passing arguments or returning on the stack for
>> cmse_nonsecure_{call,entry} functions,
>> - only test Security Extensions for -mfpu=fpv5-d16 and fpv5-sp-d16 and
>> only support single and double precision FPU's with d16.
>>
>> Bootstrapped and tested on arm-none-linux-gnueabihf and tested on
>> arm-none-eabi with ARMv8-M Baseline and Mainline targets.
>>
>> Andre Vieira (7):
>>   Add support for ARMv8-M's Security Extensions flag and intrinsics
>>   Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute
>>   ARMv8-M Security Extension's cmse_nonsecure_entry: __acle_se label and
>> bxns return
>>   ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers
>>   Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute
>>   ARMv8-M Security Extension's cmse_nonsecure_call: use
>> __gnu_cmse_nonsecure_call
>>   Added support for ARMV8-M Security Extension cmse_nonsecure_caller
>> intrinsic
> 
> I didn't see any documentation here for the new attributes and built-in
> function.
> 
> -Sandra
> 

Hi Sandra,

The documentation is in the ARMV8-M Security Extensions in: ARM®v8-M
Security Extensions: Requirements on Development Tools document I linked
in the email above and subsequent emails
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

Also per patch I refer to the relevant sections. So for instance in
PATCH 3/7 refers to Section 5.4, which describes Entry functions and
mentions the cmse_nonsecure_entry attribute. Whereas PATCH 7/7 refers to
Section 5.4.3 of the same document which describes the
cmse_nonsecure_caller intrinsic which that patch implements.

Is there a specific intrinsic/attribute you are missing?

Cheers,
Andre

[PATCH][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

Hello,

This patch adds the -mpure-code option for ARM. This option ensures
functions are put into sections that contain only code and no data. To
ensure this throughout compilation we give these sections the ARM
processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
is only supported for non-pic code for armv7-m targets.

This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
This target hook enables a target to use the numeric value for elf
section attributes rather than their alphabetical representation. If
TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
'default_elf_asm_named_section', will print the numeric value of the
section attributes for the current section. This target hook has two
parameters:
unsigned int FLAGS, the input parameter that tells the function the
current section's attributes;
unsigned int *NUM, used to pass down the numerical representation of the
section's attributes.

The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
false, so existing behavior is not changed.

Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
arm-none-eabi with a Cortex-M3 target.


gcc/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* target.def (elf_flags_numeric): New target hook.
* targhooks.h (default_asm_elf_flags_numeric): New.
* varasm.c (default_asm_elf_flags_numeric): New.
  (default_elf_asm_named_section): Use new target hook.
* config/arm/arm.opt (mpure-code): New.
* config/arm/arm.h (SECTION_ARM_PURECODE): New.
* config/arm/arm.c (arm_asm_init_sections): Add section
  attribute to default text section if -mpure-code.
  (arm_option_check_internal): Diagnose use of option with
  non supported targets and/or options.
  (arm_asm_elf_flags_numeric): New.
  (arm_function_section): New.
  (arm_elf_section_type_flags): New.
* config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
  for -mpure-code.
* gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
* gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.



gcc/testsuite/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* gcc.target/arm/pure-code/ffunction-sections.c: New.
* gcc.target/arm/pure-code/no-literal-pool.c: New.
* gcc.target/arm/pure-code/pure-code.exp: New.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f0cdd669191689bc5dcf3a7c2b60da5a2d201e3f..d10605cee0e6e0e07bbb4e1910d30c91443f8d17 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2263,4 +2263,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 /* For switching between functions with different target attributes.  */
 #define SWITCHABLE_TARGET 1
 
+/* Define SECTION_ARM_PURECODE as the ARM specific section attribute
+   representation for SHF_ARM_PURECODE in GCC.  */
+#define SECTION_ARM_PURECODE SECTION_MACH_DEP
+
 #endif /* ! GCC_ARM_H */
>From 6f3e37973e0c4dbd393325addf42265c42726240 Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira 
Date: Tue, 14 Jun 2016 11:17:12 +0100
Subject: [PATCH] -mpure-code for ARM

---
 gcc/config/arm/arm.c   | 150 -
 gcc/config/arm/arm.h   |   4 +
 gcc/config/arm/arm.opt |   6 +
 gcc/config/arm/elf.h   |   3 +-
 gcc/doc/invoke.texi|  11 +-
 gcc/doc/tm.texi|   6 +
 gcc/doc/tm.texi.in |   2 +
 gcc/target.def |  10 ++
 gcc/targhooks.h|   2 +
 .../gcc.target/arm/pure-code/ffunction-sections.c  |  17 +++
 .../gcc.target/arm/pure-code/no-literal-pool.c |  73 ++
 .../gcc.target/arm/pure-code/pure-code.exp |  54 
 gcc/varasm.c   |  57 +---
 13 files changed, 366 insertions(+), 29 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/pure-code/ffunction-sections.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f60955438d6f1cc5d996e7eacd4b453213044181..f5cb301a0efb23dc66e4d220b4a8f32e3670e744 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -214,8 +214,8 @@ static bool arm_return_in_memory (const_tree, const_tree);
 static void arm_unwind_emit (FILE *, rtx_insn *);
 static bool arm_output_ttype (rtx);
 static void arm_asm_emit_except_personality (rtx);
-static void arm_asm_init_sections (void);
 #endif
+static void arm_asm_init_sections (void);
 static rtx 

[arm-embedded][committed] Update Coprocessor Intrinsics code after mainline changes

[Andre Vieira (lists)]

Hi,

I committed this patch to the embedded-6-branch to update this branch's
version of the Coprocessor Intrinsics implementation.  The code
committed earlier to implement the Coprocessor Intrinsics was based on a
version of the mainline patch that had not been upstreamed yet and that
patch changed since then, this patch makes the necessary changes such
that they are equivalent.

gcc/ChangeLog.arm:
2017-01-24  Andre Vieira  

* config/arm/arm.md (*ldcstc): Split into ...
(*ldc): ... this and ...
(*stc): ... this.
(ldcstc): Split into ...
(ldc): ... this and ...
(stc): ... this.
(cdp,*ldc,*stc,mrc,mcr,mrrc,mcrr): Add operand constraints.
(mrc, mrrc): Add source mode to coprocessor pattern SETs.
* config/arm/arm.c (arm_coproc_builtin_available): Put function
name on
new line and fix availability of MCRR2 and MRRC2 builtins.
(arm_coproc_ldc_stc_legitimate_address): Put function name on
new line.
* config/arm/arm-builtins.c (arm_type_qualifiers): Style fix.
* config/arm/arm_acle.h: Fix availability of __arm_mcrr2 and
__arm_mrrc2 intrinsics.
* config/arm/constraints.md (Uz): Finish sentence explaining the
constraint.
* config/arm/iterators.md (LDCSTCI,LDCSTC,ldcstc): Split into ...
(LDCI,LDC,ldc): ... this and ...
(STCI,STC,stc): ... this.
* gcc/doc/sourcebuild.texi (arm_coproc2_ok,arm_coproc3_ok): Fix
language.
(arm_coproc4_ok): New.

gcc/testsuite/ChangeLog.arm
2017-01-24  Andre Vieira  

* lib/target-supports.exp (arm_coproc2_ok,arm_coproc3_ok): Fix
language
in comments.
(arm_coproc4_ok): New.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
f569dd98ac7092248aa91d3ad2aee9921d3d0859..ca622519b7de95a2585caa0db6e5591dba30b73e
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -49,7 +49,7 @@ enum arm_type_qualifiers
   qualifier_const = 0x2, /* 1 << 1  */
   /* T *foo.  */
   qualifier_pointer = 0x4, /* 1 << 2  */
-  /* const T * foo */
+  /* const T * foo.  */
   qualifier_const_pointer = 0x6,
   /* Used when expanding arguments if an operand could
  be an immediate.  */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
a76c950c53dba315ea051cd451a64173025b89d9..418f1eabfc4f057f33dfc941e99b8292a7f3fd5e
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31506,7 +31506,8 @@ arm_elf_section_type_flags (tree decl, const char 
*name, int reloc)
 false otherwise.  If a BUILTIN is passed for which this function has not
 been implemented it will cause an exception.  */
 
-bool arm_coproc_builtin_available (enum unspecv builtin)
+bool
+arm_coproc_builtin_available (enum unspecv builtin)
 {
   /* None of these builtins are available in Thumb mode if the target only
  supports Thumb-1.  */
@@ -31538,14 +31539,17 @@ bool arm_coproc_builtin_available (enum unspecv 
builtin)
  return true;
break;
   case VUNSPEC_MCRR:
-  case VUNSPEC_MCRR2:
   case VUNSPEC_MRRC:
-  case VUNSPEC_MRRC2:
/* Only present in ARMv5TE, ARMv6 (but not ARMv6-M), ARMv7* and
   ARMv8-{A,M}.  */
if (arm_arch6 || arm_arch5te)
  return true;
break;
+  case VUNSPEC_MCRR2:
+  case VUNSPEC_MRRC2:
+   if (arm_arch6)
+ return true;
+   break;
   default:
gcc_unreachable ();
 }
@@ -31555,7 +31559,8 @@ bool arm_coproc_builtin_available (enum unspecv builtin)
 /* This function returns true if OP is a valid memory operand for the ldc and
stc coprocessor instructions and false otherwise.  */
 
-bool arm_coproc_ldc_stc_legitimate_address (rtx op)
+bool
+arm_coproc_ldc_stc_legitimate_address (rtx op)
 {
   int range;
   /* Has to be a memory operand.  */
@@ -31585,7 +31590,7 @@ bool arm_coproc_ldc_stc_legitimate_address (rtx op)
  range = INTVAL (op);
 
  /* Within the range of [-1020,1020].  */
- if (range < -1020 || range > 1020)
+ if (!IN_RANGE (range, -1020, 1020))
return false;
 
  /* And a multiple of 4.  */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 
28f063c7a6bad7554b969518540b2869334ac7f8..3ff77f2bf09734f8a113ce969efa959f185ec443
 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11496,12 +11496,12 @@
 })
 
 (define_insn ""
-  [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
-(match_operand:SI 1 "immediate_operand")
-(match_operand:SI 2 "immediate_operand")
-(match_operand:SI 3 "immediate_operand")
-(match_operand:SI 4 "immediate_operand")
-(match_operand:SI 5 "immediate_operand")] CDPI)]
+  [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
+

Re: [PATCH, ARM] PR71607: New approach to arm_disable_literal_pool

[Andre Vieira (lists)]

On 20/01/17 14:08, Ramana Radhakrishnan wrote:
> On Wed, Dec 28, 2016 at 9:58 AM, Andre Vieira (lists)
> <andre.simoesdiasvie...@arm.com> wrote:
>> On 29/11/16 09:45, Andre Vieira (lists) wrote:
>>> On 17/11/16 10:00, Ramana Radhakrishnan wrote:
>>>> On Thu, Oct 6, 2016 at 2:57 PM, Andre Vieira (lists)
>>>> <andre.simoesdiasvie...@arm.com> wrote:
>>>>> Hello,
>>>>>
>>>>> This patch tackles the issue reported in PR71607. This patch takes a
>>>>> different approach for disabling the creation of literal pools. Instead
>>>>> of disabling the patterns that would normally transform the rtl into
>>>>> actual literal pools, it disables the creation of this literal pool rtl
>>>>> by making the target hook TARGET_CANNOT_FORCE_CONST_MEM return true if
>>>>> arm_disable_literal_pool is true. I added patterns to split floating
>>>>> point constants for both SF and DFmode. A pattern to handle the
>>>>> addressing of label_refs had to be included as well since all
>>>>> "memory_operand" patterns are disabled when
>>>>> TARGET_CANNOT_FORCE_CONST_MEM returns true. Also the pattern for
>>>>> splitting 32-bit immediates had to be changed, it was not accepting
>>>>> unsigned 32-bit unsigned integers with the MSB set. I believe
>>>>> const_int_operand expects the mode of the operand to be set to VOIDmode
>>>>> and not SImode. I have only changed it in the patterns that were
>>>>> affecting this code, though I suggest looking into changing it in the
>>>>> rest of the ARM backend.
>>>>>
>>>>> I added more test cases. No regressions for arm-none-eabi with
>>>>> Cortex-M0, Cortex-M3 and Cortex-M7.
>>>>>
>>>>> Is this OK for trunk?
>>>>
>>>> Including -mslow-flash-data in your multilib flags ? If no regressions
>>>> with that ok .
>>>>
>>>>
>>>> regards
>>>> Ramana
>>>>
>>>>>
>>>
>>> Hello,
>>>
>>> I found some new ICE's with the -mslow-flash-data testing so I had to
>>> rework this patch. I took the opportunity to rebase it as well.
>>>
>>> The problem was with the way the old version of the patch handled label
>>> references.  After some digging I found I wasn't using the right target
>>> hook and so I implemented the 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' for
>>> ARM.  This target hook determines whether a literal pool ends up in an
>>> 'object_block' structure. So I reverted the changes made in the old
>>> version of the patch to the ARM implementation of the
>>> 'TARGET_CANNOT_FORCE_CONST_MEM' hook and rely on
>>> 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' instead. This patch adds an ARM
>>> implementation for this hook that returns false if
>>> 'arm_disable_literal_pool' is set to true and true otherwise.
>>>
>>> This version of the patch also reverts back to using the check for
>>> 'SYMBOL_REF' in 'thumb2_legitimate_address_p' that was removed in the
>>> last version, this code is required to place the label references in
>>> rodata sections.
>>>
>>> Another thing this patch does is revert the changes made to the 32-bit
>>> constant split in arm.md. The reason this was needed before was because
>>> 'real_to_target' returns a long array and does not sign-extend values in
>>> it, which would make sense on hosts with 64-bit longs. To fix this the
>>> value is now casted to 'int' first.  It would probably be a good idea to
>>> change the 'real_to_target' function to return an array with
>>> 'HOST_WIDE_INT' elements instead and either use all 64-bits or
>>> sign-extend them.  Something for the future?
>>>
>>> I added more test cases in this patch and reran regression tests for:
>>> Cortex-M0, Cortex-M4 with and without -mslow-flash-data. Also did a
>>> bootstrap+regressions on arm-none-linux-gnueabihf.
>>>
>>> Is this OK for trunk?
>>>
>>> Cheers,
>>> Andre
>>>
>>> gcc/ChangeLog:
>>>
>>> 2016-11-29  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>
>>> PR target/71607
>>> * config/arm/arm.md (use_literal_pool): Removes.
>>> (64-bit immediate split): No longer takes cost into consideration
>>> if 'arm_disable_literal_pool' is enabled.
>>> * config/arm/arm.c (arm_use_b

Re: [PATCH, ARM] PR71607: New approach to arm_disable_literal_pool

[Andre Vieira (lists)]

On 27/01/17 12:13, Ramana Radhakrishnan wrote:
> On Thu, Jan 26, 2017 at 3:56 PM, Andre Vieira (lists)
> <andre.simoesdiasvie...@arm.com> wrote:
>> On 20/01/17 14:08, Ramana Radhakrishnan wrote:
>>> On Wed, Dec 28, 2016 at 9:58 AM, Andre Vieira (lists)
>>> <andre.simoesdiasvie...@arm.com> wrote:
>>>> On 29/11/16 09:45, Andre Vieira (lists) wrote:
>>>>> On 17/11/16 10:00, Ramana Radhakrishnan wrote:
>>>>>> On Thu, Oct 6, 2016 at 2:57 PM, Andre Vieira (lists)
>>>>>> <andre.simoesdiasvie...@arm.com> wrote:
>>>>>>> Hello,
>>>>>>>
>>>>>>> This patch tackles the issue reported in PR71607. This patch takes a
>>>>>>> different approach for disabling the creation of literal pools. Instead
>>>>>>> of disabling the patterns that would normally transform the rtl into
>>>>>>> actual literal pools, it disables the creation of this literal pool rtl
>>>>>>> by making the target hook TARGET_CANNOT_FORCE_CONST_MEM return true if
>>>>>>> arm_disable_literal_pool is true. I added patterns to split floating
>>>>>>> point constants for both SF and DFmode. A pattern to handle the
>>>>>>> addressing of label_refs had to be included as well since all
>>>>>>> "memory_operand" patterns are disabled when
>>>>>>> TARGET_CANNOT_FORCE_CONST_MEM returns true. Also the pattern for
>>>>>>> splitting 32-bit immediates had to be changed, it was not accepting
>>>>>>> unsigned 32-bit unsigned integers with the MSB set. I believe
>>>>>>> const_int_operand expects the mode of the operand to be set to VOIDmode
>>>>>>> and not SImode. I have only changed it in the patterns that were
>>>>>>> affecting this code, though I suggest looking into changing it in the
>>>>>>> rest of the ARM backend.
>>>>>>>
>>>>>>> I added more test cases. No regressions for arm-none-eabi with
>>>>>>> Cortex-M0, Cortex-M3 and Cortex-M7.
>>>>>>>
>>>>>>> Is this OK for trunk?
>>>>>>
>>>>>> Including -mslow-flash-data in your multilib flags ? If no regressions
>>>>>> with that ok .
>>>>>>
>>>>>>
>>>>>> regards
>>>>>> Ramana
>>>>>>
>>>>>>>
>>>>>
>>>>> Hello,
>>>>>
>>>>> I found some new ICE's with the -mslow-flash-data testing so I had to
>>>>> rework this patch. I took the opportunity to rebase it as well.
>>>>>
>>>>> The problem was with the way the old version of the patch handled label
>>>>> references.  After some digging I found I wasn't using the right target
>>>>> hook and so I implemented the 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' for
>>>>> ARM.  This target hook determines whether a literal pool ends up in an
>>>>> 'object_block' structure. So I reverted the changes made in the old
>>>>> version of the patch to the ARM implementation of the
>>>>> 'TARGET_CANNOT_FORCE_CONST_MEM' hook and rely on
>>>>> 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' instead. This patch adds an ARM
>>>>> implementation for this hook that returns false if
>>>>> 'arm_disable_literal_pool' is set to true and true otherwise.
>>>>>
>>>>> This version of the patch also reverts back to using the check for
>>>>> 'SYMBOL_REF' in 'thumb2_legitimate_address_p' that was removed in the
>>>>> last version, this code is required to place the label references in
>>>>> rodata sections.
>>>>>
>>>>> Another thing this patch does is revert the changes made to the 32-bit
>>>>> constant split in arm.md. The reason this was needed before was because
>>>>> 'real_to_target' returns a long array and does not sign-extend values in
>>>>> it, which would make sense on hosts with 64-bit longs. To fix this the
>>>>> value is now casted to 'int' first.  It would probably be a good idea to
>>>>> change the 'real_to_target' function to return an array with
>>>>> 'HOST_WIDE_INT' elements instead and either use all 64-bits or
>>>>> sign-extend them.  Something for the future?
>>>>>
>>>>

[PING][PATCH, ARM] PR71607: New approach to arm_disable_literal_pool

[Andre Vieira (lists)]

On 28/12/16 09:58, Andre Vieira (lists) wrote:
> On 29/11/16 09:45, Andre Vieira (lists) wrote:
>> On 17/11/16 10:00, Ramana Radhakrishnan wrote:
>>> On Thu, Oct 6, 2016 at 2:57 PM, Andre Vieira (lists)
>>> <andre.simoesdiasvie...@arm.com> wrote:
>>>> Hello,
>>>>
>>>> This patch tackles the issue reported in PR71607. This patch takes a
>>>> different approach for disabling the creation of literal pools. Instead
>>>> of disabling the patterns that would normally transform the rtl into
>>>> actual literal pools, it disables the creation of this literal pool rtl
>>>> by making the target hook TARGET_CANNOT_FORCE_CONST_MEM return true if
>>>> arm_disable_literal_pool is true. I added patterns to split floating
>>>> point constants for both SF and DFmode. A pattern to handle the
>>>> addressing of label_refs had to be included as well since all
>>>> "memory_operand" patterns are disabled when
>>>> TARGET_CANNOT_FORCE_CONST_MEM returns true. Also the pattern for
>>>> splitting 32-bit immediates had to be changed, it was not accepting
>>>> unsigned 32-bit unsigned integers with the MSB set. I believe
>>>> const_int_operand expects the mode of the operand to be set to VOIDmode
>>>> and not SImode. I have only changed it in the patterns that were
>>>> affecting this code, though I suggest looking into changing it in the
>>>> rest of the ARM backend.
>>>>
>>>> I added more test cases. No regressions for arm-none-eabi with
>>>> Cortex-M0, Cortex-M3 and Cortex-M7.
>>>>
>>>> Is this OK for trunk?
>>>
>>> Including -mslow-flash-data in your multilib flags ? If no regressions
>>> with that ok .
>>>
>>>
>>> regards
>>> Ramana
>>>
>>>>
>>
>> Hello,
>>
>> I found some new ICE's with the -mslow-flash-data testing so I had to
>> rework this patch. I took the opportunity to rebase it as well.
>>
>> The problem was with the way the old version of the patch handled label
>> references.  After some digging I found I wasn't using the right target
>> hook and so I implemented the 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' for
>> ARM.  This target hook determines whether a literal pool ends up in an
>> 'object_block' structure. So I reverted the changes made in the old
>> version of the patch to the ARM implementation of the
>> 'TARGET_CANNOT_FORCE_CONST_MEM' hook and rely on
>> 'TARGET_USE_BLOCKS_FOR_CONSTANT_P' instead. This patch adds an ARM
>> implementation for this hook that returns false if
>> 'arm_disable_literal_pool' is set to true and true otherwise.
>>
>> This version of the patch also reverts back to using the check for
>> 'SYMBOL_REF' in 'thumb2_legitimate_address_p' that was removed in the
>> last version, this code is required to place the label references in
>> rodata sections.
>>
>> Another thing this patch does is revert the changes made to the 32-bit
>> constant split in arm.md. The reason this was needed before was because
>> 'real_to_target' returns a long array and does not sign-extend values in
>> it, which would make sense on hosts with 64-bit longs. To fix this the
>> value is now casted to 'int' first.  It would probably be a good idea to
>> change the 'real_to_target' function to return an array with
>> 'HOST_WIDE_INT' elements instead and either use all 64-bits or
>> sign-extend them.  Something for the future?
>>
>> I added more test cases in this patch and reran regression tests for:
>> Cortex-M0, Cortex-M4 with and without -mslow-flash-data. Also did a
>> bootstrap+regressions on arm-none-linux-gnueabihf.
>>
>> Is this OK for trunk?
>>
>> Cheers,
>> Andre
>>
>> gcc/ChangeLog:
>>
>> 2016-11-29  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>
>> PR target/71607
>> * config/arm/arm.md (use_literal_pool): Removes.
>> (64-bit immediate split): No longer takes cost into consideration
>> if 'arm_disable_literal_pool' is enabled.
>> * config/arm/arm.c (arm_use_blocks_for_constant_p): New.
>> (TARGET_USE_BLOCKS_FOR_CONSTANT_P): Define.
>> (arm_max_const_double_inline_cost): Remove use of
>> arm_disable_literal_pool.
>> * config/arm/vfp.md (no_literal_pool_df_immediate): New.
>> (no_literal_pool_sf_immediate): New.
>>
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2016-11-29  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>

[PATCHv2 6/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call

[Andre Vieira (lists)]

On 25/07/16 14:26, Andre Vieira (lists) wrote:
> This patch extends support for the ARMv8-M Security Extensions
> 'cmse_nonsecure_call' to use a new library function
> '__gnu_cmse_nonsecure_call'. This library function is responsible for
> (without using r0-r3 or d0-d7):
> 1) saving and clearing all callee-saved registers using the secure stack
> 2) clearing the LSB of the address passed in r4 and using blxns to
> 'jump' to it
> 3) clearing ASPR, including the 'ge bits' if DSP is enabled
> 4) clearing FPSCR if using non-soft float-abi
> 5) restoring callee-saved registers.
> 
> The decisions whether to include DSP 'ge bits' clearing and floating
> point registers (single/double precision) all depends on the multilib used.
> 
> See Section 5.5 of ARM®v8-M Security Extensions
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/arm.c (detect_cmse_nonsecure_call): New.
> (cmse_nonsecure_call_clear_caller_saved): New.
> (arm_reorg): Use cmse_nonsecure_call_clear_caller_saved.
> * config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
> * config/arm/arm.md (call): Handle cmse_nonsecure_entry.
> (call_value): Likewise.
> (nonsecure_call_internal): New.
> (nonsecure_call_value_internal): New.
> * config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
> (*nonsecure_call_value_reg_thumb1_v5): New.
> * config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
> (*nonsecure_call_value_reg_thumb2): New.
> * config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.
> 
> *** libgcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/cmse_nonsecure_call.S: New.
>   * config/arm/t-arm: Compile cmse_nonsecure_call.S
> 
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir.
> * gcc.target/arm/cmse/cmse-9.c: Added some extra tests.
> * gcc.target/arm/cmse/baseline/bitfield-4.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-5.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-6.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-7.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-8.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-9.c: New.
> * gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New.
> * gcc.target/arm/cmse/baseline/cmse-11.c: New.
>   * gcc.target/arm/cmse/baseline/cmse-13.c: New.
>   * gcc.target/arm/cmse/baseline/cmse-6.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/baseline/union-1.c: New.
> * gcc/testsuite/gcc.target/arm/cmse/baseline/union-2.c: New.
>   * gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
>   * gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
>   * gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
>   * gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
>   * gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
>   * gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
>   * gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
>   * gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
>   * gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
>   * gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
>   * gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
>   * gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
>   * gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
>   * gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.
> 

Updated this patch to correctly clear only the cumulative
exception-status (0-4,7) and the condition code bits (28-31) of the FPSCR.



This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_call' to use a new library function
'__gnu_cmse_nonsecure_call'. This library function is responsible for
(without using r0-r3 or d0-d7):
1) saving and clearing all callee-saved registers using the secure stack
2) clearing the LSB of the address passed in r4 and using blxns to
'jump' to it
3) clearing ASPR, including the 'ge bits' if DSP is enabled
4) clearing the cumulative exception-status (0-4, 7) and the condition
bits (28-31) of the FPSCR if using non-soft float-abi
5) restoring callee-saved registers.

The decisions whether to include DSP 'ge bit

[PATCHv2 5/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_call attribute

[Andre Vieira (lists)]

On 25/07/16 14:25, Andre Vieira (lists) wrote:
> This patch adds support for the ARMv8-M Security Extensions
> 'cmse_nonsecure_call' attribute. This attribute may only be used for
> function types and when used in combination with the '-mcmse'
> compilation flag. See Section 5.5 of ARM®v8-M Security Extensions
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
> 
> We currently do not support cmse_nonsecure_call functions that pass
> arguments or return variables on the stack and we diagnose this.
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/arm.c (gimplify.h): New include.
> (arm_handle_cmse_nonsecure_call): New.
> (arm_attribute_table): Added cmse_nonsecure_call.
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse-3.c: Add tests.
> * gcc.target/arm/cmse/cmse-4.c: Add tests.
> 

Added more documentation as requested.

---

This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_call' attribute. This attribute may only be used for
function types and when used in combination with the '-mcmse'
compilation flag. See Section 5.5 of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

We currently do not support cmse_nonsecure_call functions that pass
arguments or return variables on the stack and we diagnose this.

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* config/arm/arm.c (gimplify.h): New include.
(arm_handle_cmse_nonsecure_call): New.
(arm_attribute_table): Added cmse_nonsecure_call.
* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.

*** gcc/testsuite/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc.target/arm/cmse/cmse-3.c: Add tests.
* gcc.target/arm/cmse/cmse-4.c: Add tests.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
680b648a218d166d49e89be78ee30397dac7e87f..647e41677834573db1b921d3e8445145767779c4
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -61,6 +61,7 @@
 #include "builtins.h"
 #include "tm-constrs.h"
 #include "rtl-iter.h"
+#include "gimplify.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -135,6 +136,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
 static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
+static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -347,6 +349,8 @@ static const struct attribute_spec arm_attribute_table[] =
   /* ARMv8-M Security Extensions support.  */
   { "cmse_nonsecure_entry", 0, 0, true, false, false,
 arm_handle_cmse_nonsecure_entry, false },
+  { "cmse_nonsecure_call", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_call, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -6750,6 +6754,78 @@ arm_handle_cmse_nonsecure_entry (tree *node, tree name,
   return NULL_TREE;
 }
 
+
+/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
+   function will check whether the attribute is allowed here and will add the
+   attribute to the function type tree or otherwise issue a diagnostic.  The
+   reason we check this at declaration time is to only allow the use of the
+   attribute with declarations of function pointers and not function
+   declarations.  This function checks NODE is of the expected type and issues
+   diagnostics otherwise using NAME.  If it is not of the expected type
+   *NO_ADD_ATTRS will be set to true.  */
+
+static tree
+arm_handle_cmse_nonsecure_call (tree *node, tree name,
+tree /* args */,
+int /* flags */,
+bool *no_add_attrs)
+{
+  tree decl = NULL_TREE;
+  tree type, fntype, main_variant;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}
+
+  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
+{
+  decl = *node;
+  type = TREE

Re: [PATCH 0/7, GCC, V8M] ARMv8-M Security Extensions

[Andre Vieira (lists)]

On 10/08/16 09:08, Andre Vieira (lists) wrote:
> On 09/08/16 17:47, Sandra Loosemore wrote:
>> On 08/09/2016 06:01 AM, Andre Vieira (lists) wrote:
>>> [snip]
>>>
>>> The documentation is in the ARMV8-M Security Extensions in: ARM®v8-M
>>> Security Extensions: Requirements on Development Tools document I linked
>>> in the email above and subsequent emails
>>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
>>>
>>> Also per patch I refer to the relevant sections. So for instance in
>>> PATCH 3/7 refers to Section 5.4, which describes Entry functions and
>>> mentions the cmse_nonsecure_entry attribute. Whereas PATCH 7/7 refers to
>>> Section 5.4.3 of the same document which describes the
>>> cmse_nonsecure_caller intrinsic which that patch implements.
>>>
>>> Is there a specific intrinsic/attribute you are missing?
>>
>> You need to at least add entries to the relevant sections in extend.texi
>> for the new target-specific intrinsic and attributes.  The documentation
>> there doesn't need to be terribly detailed (one sentence and a link to
>> the external document is probably all you need), but it's important that
>> these things be listed in GCC's supported extensions so that users know
>> they can use them and so that people who see them in code written by
>> other people can find out what they mean.
>>
>> -Sandra
>>
> 
> 
> I see, I did add a new entry to extend.texi for ARMv8-M Security
> Extensions. I will also mention all intrinsics and attributes there.
> 
> Thank you.
> 
> Andre
> 

I updated the patch series with more documentation in extend.texi and I
also fixed an issue with the clearing of FPSCR.

Cheers,
Andre

[PATCHv2 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

On 25/07/16 14:23, Andre Vieira (lists) wrote:
> This patch extends support for the ARMv8-M Security Extensions
> 'cmse_nonsecure_entry' attribute to safeguard against leak of
> information through unbanked registers.
> 
> When returning from a nonsecure entry function we clear all caller-saved
> registers that are not used to pass return values, by writing either the
> LR, in case of general purpose registers, or the value 0, in case of FP
> registers. We use the LR to write to APSR and FPSCR too. We currently do
> not support entry functions that pass arguments or return variables on
> the stack and we diagnose this. This patch relies on the existing code
> to make sure callee-saved registers used in cmse_nonsecure_entry
> functions are saved and restored thus retaining their nonsecure mode
> value, this should be happening already as it is required by AAPCS.
> 
> This patch also clears padding bits for cmse_nonsecure_entry functions
> with struct and union return types. For unions a bit is only considered
> a padding bit if it is an unused bit in every field of that union. The
> function that calculates these is used in a later patch to do the same
> for arguments of cmse_nonsecure_call's.
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/arm.c (output_return_instruction): Clear
> registers.
> (thumb2_expand_return): Likewise.
> (thumb1_expand_epilogue): Likewise.
> (thumb_exit): Likewise.
> (arm_expand_epilogue): Likewise.
> (cmse_nonsecure_entry_clear_before_return): New.
> (comp_not_to_clear_mask_str_un): New.
> (compute_not_to_clear_mask): New.
> * config/arm/thumb1.md (*epilogue_insns): Change length attribute.
> * config/arm/thumb2.md (*thumb2_return): Likewise.
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
> * gcc.target/arm/cmse/struct-1.c: New.
> * gcc.target/arm/cmse/bitfield-1.c: New.
> * gcc.target/arm/cmse/bitfield-2.c: New.
> * gcc.target/arm/cmse/bitfield-3.c: New.
> * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are
> cleared.
> * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
> * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
> * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
> * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
> * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.
> 

Updated this patch to correctly clear only the cumulative
exception-status (0-4,7) and the condition code bits (28-31) of the
FPSCR. I also adapted the code to be handle the bigger floating point
register files.



This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR. For FPSCR we clear only the
cumulative exception-status (0-4, 7) and the condition code bits
(28-31). We currently do not support entry functions that pass arguments
or return variables on the stack and we diagnose this. This patch relies
on the existing code to make sure callee-saved registers used in
cmse_nonsecure_entry functions are saved and restored thus retaining
their nonsecure mode value, this should be happening already as it is
required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* config/arm/arm.c (output_return_instruction): Clear
registers.
(thumb2_expand_return): Likewise.
(thumb1_expand_epilogue): Likewise.
(thumb_exit): Likewise.
(arm_expand_epilogue): Likewise.
(cmse_nonsecure_entry_clear_before_return): New.
(comp_not_to_clear_mask_str_un): New.
(compute_not_to_clear_mask): New.
* config/arm/thumb1.md (*epilogue_insns)

[PATCHv2 2/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Andre Vieira (lists)]

On 25/07/16 14:21, Andre Vieira (lists) wrote:
> This patch adds support for the ARMv8-M Security Extensions
> 'cmse_nonsecure_entry' attribute. In this patch we implement the
> attribute handling and diagnosis around the attribute. See Section 5.4
> of ARM®v8-M Security Extensions
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
> (arm_attribute_table): Added cmse_nonsecure_entry
> (arm_compute_func_type): Handle cmse_nonsecure_entry.
> (cmse_func_args_or_return_in_stack): New.
> (arm_handle_cmse_nonsecure_entry): New.
> * config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
> (IS_CMSE_ENTRY): Likewise.
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse-3.c: New.
>

Added more documentation as requested.



This patch adds support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute. In this patch we implement the
attribute handling and diagnosis around the attribute. See Section 5.4
of ARM®v8-M Security Extensions
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
(arm_attribute_table): Added cmse_nonsecure_entry
(arm_compute_func_type): Handle cmse_nonsecure_entry.
(cmse_func_args_or_return_in_stack): New.
(arm_handle_cmse_nonsecure_entry): New.
* config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
(IS_CMSE_ENTRY): Likewise.
* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.

*** gcc/testsuite/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc.target/arm/cmse/cmse-3.c: New.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 
e3697bbcb425999db31ac2b4f47e14bb3f2ffa89..5307ec8f904230db5ea44150ef471d928926ab6d
 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1373,6 +1373,7 @@ enum reg_class
 #define ARM_FT_VOLATILE(1 << 4) /* Does not return.  */
 #define ARM_FT_NESTED  (1 << 5) /* Embedded inside another func.  */
 #define ARM_FT_STACKALIGN  (1 << 6) /* Called with misaligned stack.  */
+#define ARM_FT_CMSE_ENTRY  (1 << 7) /* ARMv8-M non-secure entry function.  
*/
 
 /* Some macros to test these flags.  */
 #define ARM_FUNC_TYPE(t)   (t & ARM_FT_TYPE_MASK)
@@ -1381,6 +1382,7 @@ enum reg_class
 #define IS_NAKED(t)(t & ARM_FT_NAKED)
 #define IS_NESTED(t)   (t & ARM_FT_NESTED)
 #define IS_STACKALIGN(t)   (t & ARM_FT_STACKALIGN)
+#define IS_CMSE_ENTRY(t)   (t & ARM_FT_CMSE_ENTRY)
 
 
 /* Structure used to hold the function stack frame layout.  Offsets are
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 
9903d9cd8c5ff68a2318a643bdf31cf48016eba4..11417ab3c2f7101866ee5d6b100913480e5c336e
 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -134,6 +134,7 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, 
int, bool *);
 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
 #endif
+static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
 static int arm_comp_type_attributes (const_tree, const_tree);
@@ -343,6 +344,9 @@ static const struct attribute_spec arm_attribute_table[] =
   { "notshared",0, 0, false, true, false, arm_handle_notshared_attribute,
 false },
 #endif
+  /* ARMv8-M Security Extensions support.  */
+  { "cmse_nonsecure_entry", 0, 0, true, false, false,
+arm_handle_cmse_nonsecure_entry, false },
   { NULL,   0, 0, false, false, false, NULL, false }
 };
 
@@ -3633,6 +3637,9 @@ arm_compute_func_type (void)
   else
 type |= arm_isr_value (TREE_VALUE (a));
 
+  if (lookup_attribute ("cmse_nonsecure_entry", attr))
+type |= ARM_FT_CMSE_ENTRY;
+
   return type;
 }
 
@@ -6634,6 +6641,110 @@ arm_handle_notshared_attribute (tree *node,
 }
 #endif
 
+/* This function returns true if a function with declaration FNDECL, name
+   NAME and type FNTYPE u

[PATCHv2 1/7, GCC, ARM, V8M] Add support for ARMv8-M's Secure Extensions flag and intrinsics

[Andre Vieira (lists)]

On 25/07/16 14:19, Andre Vieira (lists) wrote:
> This patch adds the support of the '-mcmse' option to enable ARMv8-M's
> Security Extensions and supports the following intrinsics:
> cmse_TT
> cmse_TT_fptr
> cmse_TTT
> cmse_TTT_fptr
> cmse_TTA
> cmse_TTA_fptr
> cmse_TTAT
> cmse_TTAT_fptr
> cmse_check_address_range
> cmse_check_pointed_object
> cmse_is_nsfptr
> cmse_nsfptr_create
> 
> It also defines the mandatory cmse_address_info struct and the
> __ARM_FEATURE_CMSE macro.
> See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
> Extensions: Requirements on Development Tools
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config.gcc (extra_headers): Added arm_cmse.h.
> * config/arm/arm-arches.def (ARM_ARCH):
> (armv8-m): Add FL2_CMSE.
> (armv8-m.main): Likewise.
> (armv8-m.main+dsp): Likewise.
> * config/arm/arm-c.c
> (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
> * config/arm/arm-protos.h
> (arm_is_constant_pool_ref): Define FL2_CMSE.
> * config/arm.c (arm_arch_cmse): New.
> (arm_option_override): New error for unsupported cmse target.
> * config/arm/arm.h (arm_arch_cmse): New.
> * config/arm/arm.opt (mcmse): New.
> * doc/invoke.texi (ARM Options): Add -mcmse.
> * config/arm/arm_cmse.h: New file.
> 
> *** libgcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/cmse.c: Likewise.
> * config/arm/t-arm (HAVE_CMSE): New.
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse.exp: New.
> * gcc.target/arm/cmse/cmse-1.c: New.
> * gcc.target/arm/cmse/cmse-12.c: New.
> * lib/target-supports.exp
> (check_effective_target_arm_cmse_ok): New.
> 

Added more documentation as requested.

This patch adds the support of the '-mcmse' option to enable ARMv8-M's
Security Extensions and supports the following intrinsics:
cmse_TT
cmse_TT_fptr
cmse_TTT
cmse_TTT_fptr
cmse_TTA
cmse_TTA_fptr
cmse_TTAT
cmse_TTAT_fptr
cmse_check_address_range
cmse_check_pointed_object
cmse_is_nsfptr
cmse_nsfptr_create

It also defines the mandatory cmse_address_info struct and the
__ARM_FEATURE_CMSE macro.
See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
Extensions: Requirements on Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* config.gcc (extra_headers): Added arm_cmse.h.
* config/arm/arm-arches.def (ARM_ARCH):
(armv8-m): Add FL2_CMSE.
(armv8-m.main): Likewise.
(armv8-m.main+dsp): Likewise.
* config/arm/arm-c.c
(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
* config/arm/arm-protos.h
(arm_is_constant_pool_ref): Define FL2_CMSE.
* config/arm.c (arm_arch_cmse): New.
(arm_option_override): New error for unsupported cmse target.
* config/arm/arm.h (arm_arch_cmse): New.
* config/arm/arm.opt (mcmse): New.
* doc/invoke.texi (ARM Options): Add -mcmse.
* doc/extend.texi (ARM ARMv8-M Security Extensions): Add section.
* config/arm/arm_cmse.h: New file.

*** libgcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>
* config/arm/cmse.c: Likewise.
* config/arm/t-arm (HAVE_CMSE): New.


*** gcc/testsuite/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc.target/arm/cmse/cmse.exp: New.
* gcc.target/arm/cmse/cmse-1.c: New.
* gcc.target/arm/cmse/cmse-12.c: New.
* lib/target-supports.exp
(check_effective_target_arm_cmse_ok): New.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 
1f75f17877334c2bb61cd16b69539ec7514db8ae..8555bbf19d81b517493c86b38aff31a633ac50eb
 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -320,7 +320,7 @@ arc*-*-*)
 arm*-*-*)
cpu_type=arm
extra_objs="arm-builtins.o aarch-common.o"
-   extra_headers="mmintrin.h arm_neon.h arm_acle.h"
+   extra_headers=&quo

Re: [PATCH 7/7, GCC, ARM, V8M] Added support for ARMV8-M Security Extension cmse_nonsecure_caller intrinsic

[Andre Vieira (lists)]

On 25/07/16 14:28, Andre Vieira (lists) wrote:
> This patch adds support ARMv8-M's Security Extension's
> cmse_nonsecure_caller intrinsic. This intrinsic is used to check whether
> an entry function was called from a non-secure state.
> See Section 5.4.3 of ARM®v8-M Security Extensions: Requirements on
> Development Tools
> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html)
> for further details.
> 
> The FIXME in config/arm/arm_cmse.h is for a diagnostic message that is
> suggested in the ARMv8-M Security Extensions document mentioned above,
> to diagnose the use of the cmse_nonsecure_caller intrinsic outside of
> functions with the 'cmse_nonsecure_entry' attribute.  Checking whether
> the intrinsic is called from within such functions can easily be done
> inside 'arm_expand_builtin'. However, making the warning point to the
> right location is more complicated.  The ARMv8-M Security Extensions
> specification does mention that such a diagnostic might become
> mandatory, so I might have to pick this up later, otherwise it is left
> as a potential extra feature.
> 
> 
> *** gcc/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * config/arm/arm-builtins.c (arm_builtins): Define
> ARM_BUILTIN_CMSE_NONSECURE_CALLER.
> (bdesc_2arg): Add line for cmse_nonsecure_caller.
> (arm_expand_builtin): Handle cmse_nonsecure_caller.
> * config/arm/arm_cmse.h (cmse_nonsecure_caller): New.
> 
> *** gcc/testsuite/ChangeLog ***
> 2016-07-25  Andre Vieira<andre.simoesdiasvie...@arm.com>
> Thomas Preud'homme  <thomas.preudho...@arm.com>
> 
> * gcc.target/arm/cmse/cmse-1.c: Add test for
> cmse_nonsecure_caller.
> 
Added more documentation as requested.

---

This patch adds support ARMv8-M's Security Extension's
cmse_nonsecure_caller intrinsic. This intrinsic is used to check whether
an entry function was called from a non-secure state.
See Section 5.4.3 of ARM®v8-M Security Extensions: Requirements on
Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html)
for further details.

The FIXME in config/arm/arm_cmse.h is for a diagnostic message that is
suggested in the ARMv8-M Security Extensions document mentioned above,
to diagnose the use of the cmse_nonsecure_caller intrinsic outside of
functions with the 'cmse_nonsecure_entry' attribute.  Checking whether
the intrinsic is called from within such functions can easily be done
inside 'arm_expand_builtin'. However, making the warning point to the
right location is more complicated.  The ARMv8-M Security Extensions
specification does mention that such a diagnostic might become
mandatory, so I might have to pick this up later, otherwise it is left
as a potential extra feature.


*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* config/arm/arm-builtins.c (arm_builtins): Define
ARM_BUILTIN_CMSE_NONSECURE_CALLER.
(bdesc_2arg): Add line for cmse_nonsecure_caller.
(arm_expand_builtin): Handle cmse_nonsecure_caller.
* config/arm/arm_cmse.h (cmse_nonsecure_caller): New.
* doc/extend.texi (ARM ARMv8-M Security Extensions): New intrinsic.

*** gcc/testsuite/ChangeLog ***
2016-07-xx  Andre Vieira<andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>

* gcc.target/arm/cmse/cmse-1.c: Add test for
cmse_nonsecure_caller.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 
68b2839879f78e8d819444fbc11d2a91f8d6279a..2589ec2d1233f3daff94a1d35ebf63c8a9b93ecf
 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -515,6 +515,8 @@ enum arm_builtins
   ARM_BUILTIN_GET_FPSCR,
   ARM_BUILTIN_SET_FPSCR,
 
+  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -1789,6 +1791,17 @@ arm_init_builtins (void)
= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
 }
+
+  if (arm_arch_cmse)
+{
+  tree ftype_cmse_nonsecure_caller
+   = build_function_type_list (unsigned_type_node, NULL);
+  arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
+   = add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
+   ftype_cmse_nonsecure_caller,
+   ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
+   NULL, NULL_TREE);
+}
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -2368,6 +2381,12 @@ arm_expand_bu

Re: [PATCHv2, PING 3][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 11/08/16 15:13, Andre Vieira (lists) wrote:
> On 25/07/16 11:52, Andre Vieira (lists) wrote:
>> On 11/07/16 17:56, Andre Vieira (lists) wrote:
>>> On 07/07/16 13:30, mickael guene wrote:
>>>> Hi Andre,
>>>>
>>>>  Another feedback on your purecode patch.
>>>>  You have to disable casesi pattern since then it will
>>>> generate wrong code with -mpure-code option.
>>>>  Indeed it will generate an 'adr rx, .Lx' (aka
>>>> 'subs rx, PC, #offset') which will not work in our
>>>> case since 'Lx' label is put in an .rodata section.
>>>> So offset value is unknown and can be impossible
>>>> to encode correctly.
>>>>
>>>> Regards
>>>> Mickael
>>>>
>>>> On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:
>>>>> Hello,
>>>>>
>>>>> This patch adds the -mpure-code option for ARM. This option ensures
>>>>> functions are put into sections that contain only code and no data. To
>>>>> ensure this throughout compilation we give these sections the ARM
>>>>> processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
>>>>> is only supported for non-pic code for armv7-m targets.
>>>>>
>>>>> This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
>>>>> This target hook enables a target to use the numeric value for elf
>>>>> section attributes rather than their alphabetical representation. If
>>>>> TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
>>>>> 'default_elf_asm_named_section', will print the numeric value of the
>>>>> section attributes for the current section. This target hook has two
>>>>> parameters:
>>>>> unsigned int FLAGS, the input parameter that tells the function the
>>>>> current section's attributes;
>>>>> unsigned int *NUM, used to pass down the numerical representation of the
>>>>> section's attributes.
>>>>>
>>>>> The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
>>>>> false, so existing behavior is not changed.
>>>>>
>>>>> Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
>>>>> arm-none-eabi with a Cortex-M3 target.
>>>>>
>>>>>
>>>>> gcc/ChangeLog:
>>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>> Terry Guo  <terry@arm.com>
>>>>>
>>>>> * target.def (elf_flags_numeric): New target hook.
>>>>> * targhooks.h (default_asm_elf_flags_numeric): New.
>>>>> * varasm.c (default_asm_elf_flags_numeric): New.
>>>>>   (default_elf_asm_named_section): Use new target hook.
>>>>> * config/arm/arm.opt (mpure-code): New.
>>>>> * config/arm/arm.h (SECTION_ARM_PURECODE): New.
>>>>> * config/arm/arm.c (arm_asm_init_sections): Add section
>>>>>   attribute to default text section if -mpure-code.
>>>>>   (arm_option_check_internal): Diagnose use of option with
>>>>>   non supported targets and/or options.
>>>>>   (arm_asm_elf_flags_numeric): New.
>>>>>   (arm_function_section): New.
>>>>>   (arm_elf_section_type_flags): New.
>>>>> * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
>>>>>   for -mpure-code.
>>>>> * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
>>>>> * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.
>>>>>
>>>>>
>>>>>
>>>>> gcc/testsuite/ChangeLog:
>>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>> Terry Guo  <terry@arm.com>
>>>>>
>>>>> * gcc.target/arm/pure-code/ffunction-sections.c: New.
>>>>> * gcc.target/arm/pure-code/no-literal-pool.c: New.
>>>>> * gcc.target/arm/pure-code/pure-code.exp: New.
>>>>>
>>>>
>>> Hi Sandra, Mickael,
>>>
>>> Thank you for your comments. I changed the description of -mpure-code in
>>> invoke.texi to better reflect the error message you get wrt supported
>>> targets.
>>>
>>> As fo

[GCC-6][RFA 1/2]: Don't ignore target_header_dir when deciding inhibit_libc

[Andre Vieira (lists)]

On 27/05/16 15:51, Ulrich Weigand wrote:
> Andre Vieira (lists) wrote:
>> On 07/04/16 10:30, Andre Vieira (lists) wrote:
>>> On 17/03/16 16:33, Andre Vieira (lists) wrote:
>>>> On 23/10/15 12:31, Bernd Schmidt wrote:
>>>>> On 10/12/2015 11:58 AM, Ulrich Weigand wrote:
>>>>>>
>>>>>> Index: gcc/configure.ac
>>>>>> ===
>>>>>> --- gcc/configure.ac(revision 228530)
>>>>>> +++ gcc/configure.ac(working copy)
>>>>>> @@ -1993,7 +1993,7 @@ elif test "x$TARGET_SYSTEM_ROOT" != x; t
>>>>>>   fi
>>>>>>
>>>>>>   if test x$host != x$target || test "x$TARGET_SYSTEM_ROOT" != x; then
>>>>>> -  if test "x$with_headers" != x; then
>>>>>> +  if test "x$with_headers" != x && test "x$with_headers" != xyes; then
>>>>>>   target_header_dir=$with_headers
>>>>>> elif test "x$with_sysroot" = x; then
>>>>>>  
>>>>>> target_header_dir="${test_exec_prefix}/${target_noncanonical}/sys-include"
>>>>>>
>>>>>
>>>>> I'm missing the beginning of this conversation, but this looks like a
>>>>> reasonable change (avoiding target_header_dir=yes for --with-headers).
>>>>> So, approved.
>>>>>
>>>>>
>>>>> Bernd
>>>>>
>>>> Hi there,
>>>>
>>>> I was wondering why this never made it to trunk. I am currently running
>>>> into an issue that this patch would fix.
> 
> Seems I never actually checked this in, even though it was approved.
> Thanks for the reminder, I've now checked the patch in.
> 
> Bye,
> Ulrich
> 

Is it OK to backport this fix to GCC-6? It applies cleanly, builds and
no regressions for arm-none-eabi.

Regards,
Andre

Re: [Patch] Implement std::experimental::variant

[Andre Vieira (lists)]

On 26/08/16 18:56, Tim Shen wrote:
>>
>> Adding '#include ' to
>> 'include/c++/7.0.0/variant' "fixes" that. Not sure its the right
>> approach though.
> 
> Why not?
> 
I'm not saying its the wrong approach, I'm just saying thats the first
thing I tried and it "seemed" to solve it but I didnt really look into
whether it was the right thing to do.

>>
>> For Cortex-M3 it builds but run.cc fails at execution time. I will look
>> further into this.
> 
I only now noticed this execution failure was for our newlib-nano test
run, which does not support exceptions, so ignore that.


> Can you attach testsuite/libstdc++.log? I'll find an arm machine to
> reproduce it.
> 

You can reproduce for the compile failure with:

$ arm-none-eabi-g++
src/gcc/libstdc++-v3/testsuite/20_util/variant/compile.cc -S
-std=gnu++17 -mcpu=cortex-m0 -mthumb

which fails and if you change -mcpu=cortex-m0 to -mcpu=cortex-m3 it builds.


Cheers,
Andre

Re: [PATCH] Define 3-argument overloads of std::hypot for C++17 (P0030R1)

[Andre Vieira (lists)]

Hi Jonathan,

On 27/09/16 16:11, Jonathan Wakely wrote:
> 
> The test might not be very good, but tests some small integer values
> and some other values where accuracy is lost for one or other of the
> alternative implementations mentioned above. If this FAILs for some
> 32-bit targets we might need to adjust the tolerances or the
> dg-options.

On arm-none-eabi I'm seeing a failure for the long double type and inputs:
{ 1e-2l, 1e-4l, 1e-4l, 0.0150004999375l }

The abs(frac) is higher than the toler: 1.73455e-16 vs 1e-16. Is that a
reasonable difference? Should we raise toler3 to 1e-15?

The last line is also too high:
  { 2147483647.l, 2147483647.l, 2147483647.l, 3719550785.027307813987l }
Yields a frac of: 1.28198e-16

Those are the only ones that pass the 1e-16 threshold.

Cheers,
Andre

[PATCH, ARM] PR71607: New approach to arm_disable_literal_pool

[Andre Vieira (lists)]

Hello,

This patch tackles the issue reported in PR71607. This patch takes a
different approach for disabling the creation of literal pools. Instead
of disabling the patterns that would normally transform the rtl into
actual literal pools, it disables the creation of this literal pool rtl
by making the target hook TARGET_CANNOT_FORCE_CONST_MEM return true if
arm_disable_literal_pool is true. I added patterns to split floating
point constants for both SF and DFmode. A pattern to handle the
addressing of label_refs had to be included as well since all
"memory_operand" patterns are disabled when
TARGET_CANNOT_FORCE_CONST_MEM returns true. Also the pattern for
splitting 32-bit immediates had to be changed, it was not accepting
unsigned 32-bit unsigned integers with the MSB set. I believe
const_int_operand expects the mode of the operand to be set to VOIDmode
and not SImode. I have only changed it in the patterns that were
affecting this code, though I suggest looking into changing it in the
rest of the ARM backend.

I added more test cases. No regressions for arm-none-eabi with
Cortex-M0, Cortex-M3 and Cortex-M7.

Is this OK for trunk?

Cheers,
Andre

gcc/ChangeLog:

2016-10-06  Andre Vieira  

PR target/71607
* config/arm/arm.md (use_literal_pool): Remove.
(64-bit immediate split): No longer take cost into consideration
if 'arm_disable_literal_pool' is enabled.
(32-bit const split): Remove SImode from constant, which was
not allowing large unsigned integers to be split.
* config/arm/arm.c (thumb2_legitimate_address_p): Remove handling
of 'arm_disable_literal_pool' here.
(arm_max_const_double_inline_cost): Likewise.
(arm_cannot_force_const_mem): Return false for
'arm_disable_literal_pool'.
(thumb2_legitimate_address_p): Remove check involving
'arm_disable_literal_pool'
that is no longer relevant.
(arm_legitimate_constant_p): Ignore the outcome of
'arm_cannot_force_const_mem'
if 'arm_disable_literal_pool' is enabled.
* config/arm/vfp.md (no_literal_pool_df_immediate): New.
(no_literal_pool_sf_immediate): New.
* config/arm/thumb2.md (*thumb2_movsi_labelref_insn): New.

gcc/testsuite/ChangeLog:

2016-10-06  Andre Vieira  
Thomas Preud'homme  

PR target/71607
* gcc.target/arm/thumb2-slow-flash-data.c: Rename to ...
* gcc.target/arm/thumb2-slow-flash-data-1.c: ... this.
* gcc.target/arm/thumb2-slow-flash-data-2.c: New.
* gcc.target/arm/thumb2-slow-flash-data-3.c: New.


From 88304e3d5507787a5453c9745c42c4c5f4093975 Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira 
Date: Tue, 30 Aug 2016 13:26:49 +0100
Subject: [PATCH 1/2] gcc32rm-709

Fix disabling of literal pool

mend
---
 gcc/config/arm/arm.c   | 30 ++---
 gcc/config/arm/arm.md  | 13 ++--
 gcc/config/arm/thumb2.md   | 11 
 gcc/config/arm/vfp.md  | 34 ++
 .../gcc.target/arm/thumb2-slow-flash-data-1.c  | 73 ++
 .../gcc.target/arm/thumb2-slow-flash-data-2.c  | 27 
 .../gcc.target/arm/thumb2-slow-flash-data-3.c  | 24 +++
 .../gcc.target/arm/thumb2-slow-flash-data.c| 73 --
 8 files changed, 179 insertions(+), 106 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
 delete mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 946f308ca84e232af8af6eca4813464914cbd59c..dce2569a2c3867464039e6a57e11acee2b28c423 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7380,25 +7380,6 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
 		  && thumb2_legitimate_index_p (mode, xop0, strict_p)));
 }
 
-  /* Normally we can assign constant values to target registers without
- the help of constant pool.  But there are cases we have to use constant
- pool like:
- 1) assign a label to register.
- 2) sign-extend a 8bit value to 32bit and then assign to register.
-
- Constant pool access in format:
- (set (reg r0) (mem (symbol_ref (".LC0"
- will cause the use of literal pool (later in function arm_reorg).
- So here we mark such format as an invalid format, then the compiler
- will adjust it into:
- (set (reg r0) (symbol_ref (".LC0")))
- (set (reg r0) (mem (reg r0))).
- No extra register is required, and (mem (reg r0)) won't cause the use
- of literal pools.  */
-  else if (arm_disable_literal_pool && code == SYMBOL_REF
-	   && CONSTANT_POOL_ADDRESS_P (x))
-return 0;
-
   else if (GET_MODE_CLASS (mode) != 

Re: [PATCHv2][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 04/10/16 14:24, mickael guene wrote:
> Hi Andre,
> 
>  I can't see new testsuite files in trunk :
> gcc.target/arm/pure-code/ffunction-sections.c
> gcc.target/arm/pure-code/no-literal-pool.c
> gcc.target/arm/pure-code/pure-code.exp
> 
>  It seems you forgot to include them in your patch.
> Can you post a new one with those files ?
> 
> Regards
> Mickael
> 

Yeah ... forgot to svn add, committed in revision r240746. Thanks for
that catch!

Cheers,
Andre

Re: [PATCHv2, PING 4][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 30/08/16 09:01, Andre Vieira (lists) wrote:
> On 11/08/16 15:13, Andre Vieira (lists) wrote:
>> On 25/07/16 11:52, Andre Vieira (lists) wrote:
>>> On 11/07/16 17:56, Andre Vieira (lists) wrote:
>>>> On 07/07/16 13:30, mickael guene wrote:
>>>>> Hi Andre,
>>>>>
>>>>>  Another feedback on your purecode patch.
>>>>>  You have to disable casesi pattern since then it will
>>>>> generate wrong code with -mpure-code option.
>>>>>  Indeed it will generate an 'adr rx, .Lx' (aka
>>>>> 'subs rx, PC, #offset') which will not work in our
>>>>> case since 'Lx' label is put in an .rodata section.
>>>>> So offset value is unknown and can be impossible
>>>>> to encode correctly.
>>>>>
>>>>> Regards
>>>>> Mickael
>>>>>
>>>>> On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:
>>>>>> Hello,
>>>>>>
>>>>>> This patch adds the -mpure-code option for ARM. This option ensures
>>>>>> functions are put into sections that contain only code and no data. To
>>>>>> ensure this throughout compilation we give these sections the ARM
>>>>>> processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
>>>>>> is only supported for non-pic code for armv7-m targets.
>>>>>>
>>>>>> This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
>>>>>> This target hook enables a target to use the numeric value for elf
>>>>>> section attributes rather than their alphabetical representation. If
>>>>>> TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
>>>>>> 'default_elf_asm_named_section', will print the numeric value of the
>>>>>> section attributes for the current section. This target hook has two
>>>>>> parameters:
>>>>>> unsigned int FLAGS, the input parameter that tells the function the
>>>>>> current section's attributes;
>>>>>> unsigned int *NUM, used to pass down the numerical representation of the
>>>>>> section's attributes.
>>>>>>
>>>>>> The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
>>>>>> false, so existing behavior is not changed.
>>>>>>
>>>>>> Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
>>>>>> arm-none-eabi with a Cortex-M3 target.
>>>>>>
>>>>>>
>>>>>> gcc/ChangeLog:
>>>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>>> Terry Guo  <terry@arm.com>
>>>>>>
>>>>>> * target.def (elf_flags_numeric): New target hook.
>>>>>> * targhooks.h (default_asm_elf_flags_numeric): New.
>>>>>> * varasm.c (default_asm_elf_flags_numeric): New.
>>>>>>   (default_elf_asm_named_section): Use new target hook.
>>>>>> * config/arm/arm.opt (mpure-code): New.
>>>>>> * config/arm/arm.h (SECTION_ARM_PURECODE): New.
>>>>>> * config/arm/arm.c (arm_asm_init_sections): Add section
>>>>>>   attribute to default text section if -mpure-code.
>>>>>>   (arm_option_check_internal): Diagnose use of option with
>>>>>>   non supported targets and/or options.
>>>>>>   (arm_asm_elf_flags_numeric): New.
>>>>>>   (arm_function_section): New.
>>>>>>   (arm_elf_section_type_flags): New.
>>>>>> * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
>>>>>>   for -mpure-code.
>>>>>> * gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
>>>>>> * gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.
>>>>>>
>>>>>>
>>>>>>
>>>>>> gcc/testsuite/ChangeLog:
>>>>>> 2016-06-30  Andre Vieira  <andre.simoesdiasvie...@arm.com>
>>>>>> Terry Guo  <terry@arm.com>
>>>>>>
>>>>>> * gcc.target/arm/pure-code/ffunction-sections.c: New.
>>>>>> * gcc.target/arm/pure-code/no-literal-pool.c: New.
>>>>>> *

Re: [PATCHv3][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 23/09/16 11:04, Jakub Jelinek wrote:
> On Thu, Sep 22, 2016 at 10:37:21PM +0200, Uros Bizjak wrote:
>> diff --git a/gcc/hooks.c b/gcc/hooks.c
>> index 
>> 99ec4014adb6fcbb073bf538dd00fe8695ee6cb2..1e925645c3173f8d97e104b9b2f480fca2ede438
>> 100644
>> --- a/gcc/hooks.c
>> +++ b/gcc/hooks.c
>> @@ -481,3 +481,13 @@ void
>>   hook_void_gcc_optionsp (struct gcc_options *opts ATTRIBUTE_UNUSED)
>>   {
>>   }
>> +
>> +/* Generic hook that takes an unsigned int, an unsigned int pointer and
>> +   returns false.  */
>> +
>> +bool
>> +hook_uint_uintp_false (unsigned int, unsigned int *)
>> +{
>> +  return false;
>> +}
>>
>>
>> The name of this hook doesn't adhere to the convention. It should be named:
>>
>> hook_bool_uint_uintp_false
> 
> You're right, I've committed this as obvious:
> 
> 2016-09-23  Uros Bizjak  
>   Jakub Jelinek  
> 
>   * hooks.h (hook_uint_uintp_false): Rename to...
>   (hook_bool_uint_uintp_false): ... this.
>   * hooks.c (hook_uint_uintp_false): Rename to...
>   (hook_bool_uint_uintp_false): ... this.
>   * target.def (elf_flags_numeric): Use hook_bool_uint_uintp_false
>   instead of hook_uint_uintp_false.
> 
> --- gcc/hooks.h.jj2016-09-23 09:32:13.0 +0200
> +++ gcc/hooks.h   2016-09-23 11:57:28.116738504 +0200
> @@ -76,7 +76,7 @@ extern void hook_void_tree (tree);
>  extern void hook_void_tree_treeptr (tree, tree *);
>  extern void hook_void_int_int (int, int);
>  extern void hook_void_gcc_optionsp (struct gcc_options *);
> -extern bool hook_uint_uintp_false (unsigned int, unsigned int *);
> +extern bool hook_bool_uint_uintp_false (unsigned int, unsigned int *);
>  
>  extern int hook_int_uint_mode_1 (unsigned int, machine_mode);
>  extern int hook_int_const_tree_0 (const_tree);
> --- gcc/hooks.c.jj2016-09-23 09:32:13.0 +0200
> +++ gcc/hooks.c   2016-09-23 11:57:39.938588268 +0200
> @@ -486,8 +486,7 @@ hook_void_gcc_optionsp (struct gcc_optio
> returns false.  */
>  
>  bool
> -hook_uint_uintp_false (unsigned int, unsigned int *)
> +hook_bool_uint_uintp_false (unsigned int, unsigned int *)
>  {
>return false;
>  }
> -
> --- gcc/target.def.jj 2016-09-23 09:32:13.0 +0200
> +++ gcc/target.def2016-09-23 11:59:03.581525303 +0200
> @@ -446,7 +446,7 @@ instead of the normal sequence of letter
>  defined, or if it returns false, then @var{num} will be ignored and the\n\
>  traditional letter sequence will be emitted.",
>   bool, (unsigned int flags, unsigned int *num),
> - hook_uint_uintp_false)
> + hook_bool_uint_uintp_false)
>  
>  /* Return preferred text (sub)section for function DECL.
> Main purpose of this function is to separate cold, normal and hot
> 
> 
>   Jakub
> 

The hook that keeps on giving. Thanks! And one more time, sorry!

Cheers,
Andre

Re: [PATCHv2][ARM] -mpure-code option for ARM

[Andre Vieira (lists)]

On 23/09/16 09:33, Andre Vieira (lists) wrote:
> On 23/09/16 02:21, Sandra Loosemore wrote:
>> On 09/22/2016 07:52 AM, Richard Earnshaw (lists) wrote:
>>> On 11/07/16 17:56, Andre Vieira (lists) wrote:
>>>> +
>>>> diff --git a/gcc/target.def b/gcc/target.def
>>>> index
>>>> a4df363698ce776b51d11c187baed2069ba88a52..a3d46fa48d919a16699c33b2b78236e62a33e025
>>>> 100644
>>>> --- a/gcc/target.def
>>>> +++ b/gcc/target.def
>>>> @@ -432,6 +432,19 @@ this section is associated.",
>>>>void, (const char *name, unsigned int flags, tree decl),
>>>>default_no_named_section)
>>>>
>>>> +/* Tell assembler what section attributes to assign this elf section
>>>> +   declaration, using their numerical value.  */
>>>> +DEFHOOK
>>>> +(elf_flags_numeric,
>>>> + "If the target needs to represent ELF section attributes using
>>>> their\n\
>>>> +numerical value, then this hook should be implemented to return true
>>>> and\n\
>>>> +write the numerical value of @var{flags} in @var{num}.  This
>>>> function is\n\
>>>> +called by @code{default_elf_asm_named_section}, which prints
>>>> @var{num}\n\
>>>> +as the value representing the ELF section attributes if this
>>>> function\n\
>>>> +returns true.",
>>>
>>>
>>> I think this should read something like.
>>>
>>> This hook can be used to encode ELF section flags for which no letter
>>> code has been defined in the assembler.  It is called by
>>> @code{default_asm_named_section} whenever the section flags need to be
>>> emitted in the assembler output.  If the hook returns true, then the
>>> numerical value for ELF section flags should be calculated from
>>> @var{flags} and saved in @var{*num}; the value will be printed out
>>> instead of the normal sequence of letter codes.  If the hook is not
>>> defined, or if it returns false, then @var{num} will be ignored and the
>>> traditional letter sequence will be emitted.
>>
>> Can we please write this in the present tense instead of the future,
>> assuming it describes current behavior (as modified by the patch)?
>>
>> s/will be/is/g
>>
>> -Sandra
>>
> Hi Sandra,
> 
> Is this better?
> 
> Cheers,
> Andre
> 
> gcc/ChangeLog
> 2016-09-23  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> 
> * target.def(elf_flags_numeric): Change documentation to
> present tense.
> 
And here is the patch with the tm.texi regeneration.

Cheers,
Andre

gcc/ChangeLog
2016-09-23  Andre Vieira  <andre.simoesdiasvie...@arm.com>

* target.def(elf_flags_numeric): Change documentation to
present tense.
* doc/tm.texi: Regenerate.
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 
68a77e81aa1e2abcc15bc9088011295df699c4d0..8a98ba43a67eac87c2be8a974f6c0b924e519f52
 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -7574,10 +7574,10 @@ code has been defined in the assembler.  It is called by
 @code{default_asm_named_section} whenever the section flags need to be
 emitted in the assembler output.  If the hook returns true, then the
 numerical value for ELF section flags should be calculated from
-@var{flags} and saved in @var{*num}; the value will be printed out
-instead of the normal sequence of letter codes.  If the hook is not
-defined, or if it returns false, then @var{num} will be ignored and the
-traditional letter sequence will be emitted.
+@var{flags} and saved in @var{*num}; the value is printed out instead of the
+normal sequence of letter codes.  If the hook is not defined, or if it
+returns false, then @var{num} is ignored and the traditional letter sequence
+is emitted.
 @end deftypefn
 
 @deftypefn {Target Hook} {section *} TARGET_ASM_FUNCTION_SECTION (tree 
@var{decl}, enum node_frequency @var{freq}, bool @var{startup}, bool @var{exit})
diff --git a/gcc/target.def b/gcc/target.def
index 
ac693318adaaa230ea300f10bc37282881d9da6f..4adb8aabc6548889b717abc9310e98f0e6fc161b
 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -441,10 +441,10 @@ code has been defined in the assembler.  It is called 
by\n\
 @code{default_asm_named_section} whenever the section flags need to be\n\
 emitted in the assembler output.  If the hook returns true, then the\n\
 numerical value for ELF section flags should be calculated from\n\
-@var{flags} and saved in @var{*num}; the value will be printed out\n\
-instead of the normal sequence of letter codes.  If the hook is not\n\
-defined, or if it returns false, then @var{num} will be ignored and the\n\
-traditional letter sequence will be emitted.",
+@var{flags} and saved in @var{*num}; the value is printed out instead of the\n\
+normal sequence of letter codes.  If the hook is not defined, or if it\n\
+returns false, then @var{num} is ignored and the traditional letter sequence\n\
+is emitted.",
  bool, (unsigned int flags, unsigned int *num),
  hook_uint_uintp_false)