[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:ffb3aca361d2b0e9ba415930a0fc61e8219c635c commit ffb3aca361d2b0e9ba415930a0fc61e8219c635c Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. The 'Optimization' keyword next to freg-struct-return was the only thing that caused flag_pcc_struct_return to be a per-function flag, and ipa-inline relied on that. After making it an alias, the Optimization keyword was no longer operational. I'm not sure it was sensible or desirable for flag_pcc_struct_return to be a per-function setting, but this patch does not intend to change behavior. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Copy Optimization... (freg-struct-return): ... here. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..12d93c76a1e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2406,7 +2406,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: ffb3aca361d... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 60e63cf86f9... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 60e63cf... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- ffb3aca... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:60e63cf86f91608df32377f9ffc7c3f3e9f316fd commit 60e63cf86f91608df32377f9ffc7c3f3e9f316fd Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..12d93c76a1e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2406,7 +2406,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: 60e63cf86f9... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 9d8a2a67a84... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 9d8a2a6... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- 60e63cf... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:9d8a2a67a84deaaf0645a73d17564d68059b2433 commit 9d8a2a67a84deaaf0645a73d17564d68059b2433 Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..f973d767584 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: 9d8a2a67a84... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: e50550cae7e... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- e50550c... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- 9d8a2a6... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:30e8256702cc4dfb56d329ee279e957a10fc962b
commit 30e8256702cc4dfb56d329ee279e957a10fc962b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:e50550cae7e3108d7f7a0ba2f9b8f14c16e29e35 commit e50550cae7e3108d7f7a0ba2f9b8f14c16e29e35 Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..ebef5977451 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(pcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] (2 commits) make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: e50550cae7e... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 68e3d62f56e... add explicit ABI and align options to pr88233.c Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 68e3d62... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- e50550c... make -freg-struct-return visibly a negative alias of -fpcc- 30e8256... add explicit ABI and align options to pr88233.c
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:68e3d62f56eea3a5fa798ec514bd89ddc6668c4a
commit 68e3d62f56eea3a5fa798ec514bd89ddc6668c4a
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..7ea459cb802 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fno-reg-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:f7a0734ee96341645e18e183210deb0d9a0c97d7
commit f7a0734ee96341645e18e183210deb0d9a0c97d7
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:9aad4681cb81920420e3cef32d02acf4bec891d6
commit 9aad4681cb81920420e3cef32d02acf4bec891d6
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:2062c8d2122c4b7dc82af9a7114136ca371da5ff
commit 2062c8d2122c4b7dc82af9a7114136ca371da5ff
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f188faa3ccf 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:4923693ac47e4bb3d6a6d72dd538fbeec68c478d
commit 4923693ac47e4bb3d6a6d72dd538fbeec68c478d
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc/aoliva/heads/testme] (5 commits) add explicit ABI and align options to pr88233.c
The branch 'aoliva/heads/testme' was updated to point to: 68e3d62f56e... add explicit ABI and align options to pr88233.c It previously pointed to: edf330eeb9d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- edf330e... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 960142e... decay vect tests from run to link for pr95401 1dd110c... xfail fetestexcept test - ppc always uses fcmpu cef8842... [testsuite] require sqrt_insn effective target where needed c5fbace... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- 68e3d62... add explicit ABI and align options to pr88233.c 9aad468... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra f7a0734... decay vect tests from run to link for pr95401 2062c8d... xfail fetestexcept test - ppc always uses fcmpu 4923693... [testsuite] require sqrt_insn effective target where needed
[PATCH v2] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Ping?-ish
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619678.html
It's that time of the year again. The good news is that this is the
last patch in my ppc*-vxworks7* set ;-)
On May 25, 2023, Segher Boessenkool wrote:
> On Thu, May 25, 2023 at 10:55:37AM -0300, Alexandre Oliva wrote:
>> I've actually identified the corresponding change to the
>> lp64 tests, compared the effects of the codegen changes, and concluded
>> the tests needed this changing for ilp32 to keep on testing for the same
>> thing after code changes brought about by changes that AFAICT had been
>> well understood when making the lp64 adjustments.
>> /* -m32 target has an 'add' in place of one of the 'addi'. */
>> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } }
>> } */
>> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 }
>> } } */
>> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
> Just {\madd} or more conservative {\maddi?\M} then?
I've made these changes in the v2 below.
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
---
.../powerpc/fold-vec-extract-double.p7.c |5 ++---
.../gcc.target/powerpc/fold-vec-extract-float.p7.c |5 ++---
.../gcc.target/powerpc/fold-vec-extract-float.p8.c |2 +-
.../gcc.target/powerpc/fold-vec-extract-int.p7.c |3 +--
.../gcc.target/powerpc/fold-vec-extract-int.p8.c |2 +-
.../gcc.target/powerpc/fold-vec-extract-short.p7.c |3 +--
.../gcc.target/powerpc/fold-vec-extract-short.p8.c |2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b71..e69d9253e2d28 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457dcb..9ff197a704906 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb462..cd80c5e1b19c6 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ex
[PATCH] decay vect tests from run to link for pr95401
Ping?-ish for the full version of the RFC posted at
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566588.html
On Mar 11, 2021, Richard Biener wrote:
> On Thu, Mar 11, 2021 at 9:03 AM Alexandre Oliva wrote:
>> So I'm leaning towards this proposed change, just extended to other
>> platforms that also decay from run to compile rather than link, and thus
>> run into this problem in g++.dg/vect/pr95401.cc. Would this be
>> acceptable?
> I think that's OK. It's probably difficult to make the test UNSUPPORTED
> when dg-additional-sources is discovered with a dg-do compile test?
Thanks, here's a completed version.
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d98691f..54a55585371b0 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[PATCH v2] xfail fetestexcept test - ppc always uses fcmpu
On Mar 10, 2021, Joseph Myers wrote:
> On Wed, 10 Mar 2021, Alexandre Oliva wrote:
>> operand exception for quiet NaN. I couldn't find any evidence that
>> the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
>> execution xfail marker to this test.
> In my view, such an XFAIL (for a GCC bug as opposed to an environmental
> issue) should have a comment pointing to a corresponding open bug in GCC
> Bugzilla. In this case, that's bug 58684.
Thanks for the suggestion, yeah, that makes sense. Fixed in v2 below.
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566523.html
Ping?-ish
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
---
gcc/testsuite/gcc.dg/torture/pr91323.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa3966c..f188faa3ccf47 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH v2] [testsuite] require sqrt_insn effective target where needed
This patch takes feedback received for 3 earlier patches, and adopts a
simpler approach to skip the still-failing tests, that I believe to be
in line with ppc maintainers' expressed preferences.
https://gcc.gnu.org/pipermail/gcc-patches/2021-February/565939.html
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566617.html
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566521.html
Ping?-ish :-)
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also testing
with gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
---
gcc/testsuite/gcc.dg/cdce3.c |3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c |1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c |1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c |1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c |1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd71..f759a95972e8b 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333a4..7e9bb638106c2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b812..5bfa25925675a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b728..b66d0209a5e54 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb6c..71a1a70c4e7a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
Re: enable sqrt insns for cdce3.c
[Revamped version of this patch, combined with others, to follow]
On Mar 10, 2021, Hans-Peter Nilsson wrote:
> On Wed, 10 Mar 2021, Alexandre Oliva wrote:
>>
>> The test expects shrink-wrapping of the fsqrt call, but that will only
>> occur when there is a usable sqrt insn.
>>
>> Arrange for dejagnu to add the options that enable the sqrt insn, if
>> one is available, and to skip the test otherwise.
>>
>>
>> H-P, this *should* obviate the mmix-specific dg-skip-if.
> Unfortunately it doesn't.
>> Would it be
>> easy for you to confirm that this is the case and, if so, drop it?
> About as easy as for anyone (this is a compile-test), but no
> problem. Unfortunately I get, with your patch applied and the
> dg-skip-if removed:
> FAIL: gcc.dg/cdce3.c scan-tree-dump cdce "cdce3.c:12: [^\n\r]*
> function call is shrink-wrapped into error conditions."
Is mmix a sqrt_insn effective target? proc
check_effective_target_sqrt_insn in
gcc/testsuite/lib/target-supports.exp suggests it shouldn't pass, so I'm
surprised it would still try to run the test despite the added
/* { dg-require-effective-target sqrt_insn } */ directive.
> The dump files and assembly file show no obvious clues to me as
> to what is supposed to happen; attached.
cdce3 is supposed to shrink-wrap the sqrtf(x) call into something like
(x >= 0 ? .SQRT(x) : sqrtf(x)), where .SQRT stands for a square root
instruction.
Since we don't know why it still runs for you, I'm keeping the mmix
explicit skip in the new version of the patch.
Thanks,
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH v2] add explicit ABI and align options to pr88233.c
Ping?
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566530.html
(modified version follows)
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
---
gcc/testsuite/gcc.target/powerpc/pr88233.c |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f79..46a3ebfa28775 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH] ppc: testsuite: vec-mul requires vsx runtime
Ping?
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/593947.html
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d1d..11da86159723f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH] Request check for hw support in ppc run tests with -maltivec/-mvsx
From: Olivier Hainque
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c |2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c |5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f421..755519bfe847d 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4c6..37a324b6f897d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH] adjust vectorization expectations for ppc costmodel 76b
Ping?
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566525.html
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
---
.../gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658f8..0dab2c08acdb4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH] disable ldist for test, to restore vectorizing-candidate loop
Ping?
https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566524.html
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
---
.../gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c |1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a30916..90b5d5a7f400b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[PATCH] [testsuite] [ppc64] expect error on vxworks too
These ppc lp64 tests check for errors or warnings on -mno-powerpc64.
On powerpc64-*-vxworks* we get the same errors as on most other
covered platforms, but the tests did not mark them as expected for
this target. On powerpc-*-vxworks*, the tests are skipped because
lp64 is not satisfied, so I'm naming powerpc*-*-vxworks* rather than
something more specific.
Regstrapped on x86_64-linux-gnu and ppc64el-linux-gnu. Also tested with
gcc-13 on ppc64-vx7r2 and ppc-vx7r2. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr106680-1.c: Error on vxworks too.
* gcc.target/powerpc/pr106680-2.c: Likewise.
* gcc.target/powerpc/pr106680-3.c: Likewise.
---
gcc/testsuite/gcc.target/powerpc/pr106680-1.c |2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-2.c |2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-3.c |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
index d624d43230a7a..aadaa614cfeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
index a9ed73726ef0c..f0758e303350a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
@@ -9,6 +9,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
index b642d5c7a008d..bca012e2cf663 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:edf330eeb9d4832b1972516bcf6b54cd897e5fa9
commit edf330eeb9d4832b1972516bcf6b54cd897e5fa9
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:960142effc3218ccb3463464d3dbe3c0ce3d5280
commit 960142effc3218ccb3463464d3dbe3c0ce3d5280
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:1dd110cf0d45a2716102a53cc42f809e29d909ae
commit 1dd110cf0d45a2716102a53cc42f809e29d909ae
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f188faa3ccf 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c5fbacee0313fb1b760a870964877f343bf4b90e
commit c5fbacee0313fb1b760a870964877f343bf4b90e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:cef88428efe311383bc65c47e4f6c96a8b16452a
commit cef88428efe311383bc65c47e4f6c96a8b16452a
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:9c266e6f78ee2bd8fad3b1310996ba5012a16735
commit 9c266e6f78ee2bd8fad3b1310996ba5012a16735
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:25b2dc8c3befb8a19584f5052db75753fcd78351
commit 25b2dc8c3befb8a19584f5052db75753fcd78351
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:b610d91071d1c8887481b7f5b3ca57342911cdea
commit b610d91071d1c8887481b7f5b3ca57342911cdea
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:06cec5e7261a78413d7ccfeea4c8e85b224d370f
commit 06cec5e7261a78413d7ccfeea4c8e85b224d370f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:5b0e0d473bcd6a06a4dc4876890477a9d30582d8
commit 5b0e0d473bcd6a06a4dc4876890477a9d30582d8
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc/aoliva/heads/testme] (10 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: edf330eeb9d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 650181136ad... [testsuite] require sqrt_insn effective target where needed Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu Summary of changes (added commits): --- edf330e... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 960142e... decay vect tests from run to link for pr95401 1dd110c... xfail fetestexcept test - ppc always uses fcmpu cef8842... [testsuite] require sqrt_insn effective target where needed c5fbace... add explicit ABI and align options to pr88233.c 25b2dc8... ppc: testsuite: vec-mul requires vsx runtime 9c266e6... ppc: testsuite: pr79004 needs -mlong-double-128 b610d91... Request check for hw support in ppc run tests with -maltive 06cec5e... adjust vectorization expectations for ppc costmodel 76b 5b0e0d4... disable ldist for test, to restore vectorizing-candidate lo
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:650181136ad3e9ec7be716f69b4bde29c883cd71
commit 650181136ad3e9ec7be716f69b4bde29c883cd71
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:387ce53fd3fdaeefc7dc9d603df0d66495580fbf
commit 387ce53fd3fdaeefc7dc9d603df0d66495580fbf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:40cc97a1048c76e6f94e7b1b4a39089686ec6a84
commit 40cc97a1048c76e6f94e7b1b4a39089686ec6a84
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:bd7a059057714d60f0b7a3db37152ae898e4a293
commit bd7a059057714d60f0b7a3db37152ae898e4a293
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:762f75a75a192bdc4f7b056a978f9ae37b12bcf7
commit 762f75a75a192bdc4f7b056a978f9ae37b12bcf7
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:de156d08943e343720819a9920ba7e4f67bbd8e4
commit de156d08943e343720819a9920ba7e4f67bbd8e4
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:4aed9893ba8413ee38770d909995f3925659b670
commit 4aed9893ba8413ee38770d909995f3925659b670
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..df5a1457cd1 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:9b0c52b69c85acbceccc5676509cfc0fbb41dd52
commit 9b0c52b69c85acbceccc5676509cfc0fbb41dd52
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:7ef3c86bc8ac48a834a787aad1809e623def6b64
commit 7ef3c86bc8ac48a834a787aad1809e623def6b64
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:f605eecb06d40c99be2d48169c5fafda2df6babb
commit f605eecb06d40c99be2d48169c5fafda2df6babb
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc/aoliva/heads/testme] (10 commits) [testsuite] require sqrt_insn effective target where needed
The branch 'aoliva/heads/testme' was updated to point to: 650181136ad... [testsuite] require sqrt_insn effective target where needed It previously pointed to: c3999e0292d... add explicit ABI and align options to pr88233.c Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime fe3c0a3... ppc: testsuite: pr79004 needs -mlong-double-128 2d28d2a... Request check for hw support in ppc run tests with -maltive ad51db7... decay vect tests from run to link for pr95401 106f3cf... adjust vectorization expectations for ppc costmodel 76b 8e6d181... disable ldist for test, to restore vectorizing-candidate lo 0e8ef1e... xfail fetestexcept test - ppc always uses fcmpu 4488f8d... add sqrt options and test for sqrt support in ppc tests 048689c... enable sqrt insns for cdce3.c 032f38d... add -mpowerpc-gpopt to options for sqrt insn on PowerPC Summary of changes (added commits): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
commit c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:d20a933141e6b8dd34fb578635ccbd49abcab15e
commit d20a933141e6b8dd34fb578635ccbd49abcab15e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan
[gcc/aoliva/heads/testme] (3 commits) add explicit ABI and align options to pr88233.c
The branch 'aoliva/heads/testme' was updated to point to: c3999e0292d... add explicit ABI and align options to pr88233.c It previously pointed to: b6144ccafe3... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- b6144cc... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0197e8f... ppc: testsuite: vec-mul requires vsx runtime 89e5150... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:347b4d5eb8a1418393f6e406d4d052d3c6b0790e
commit 347b4d5eb8a1418393f6e406d4d052d3c6b0790e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:b6144ccafe3acc445ee5b2a23000a37824923d3b
commit b6144ccafe3acc445ee5b2a23000a37824923d3b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:89e5150772d91d129fd4a8ca6ebda361e546
commit 89e5150772d91d129fd4a8ca6ebda361e546
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the expectations to be met.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..c667a28ebfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fno-reg-struct-return" } */
typedef struct { double a[2]; } A;
A
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:0197e8f80932063526f0bd7437c80c9ca420cf38
commit 0197e8f80932063526f0bd7437c80c9ca420cf38
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
commit fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:2d28d2a79906d56cb121c5e08af68c81d7a5dea7
commit 2d28d2a79906d56cb121c5e08af68c81d7a5dea7
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
commit ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ec753b19e2f..b55bd65bdbb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11628,7 +11628,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11658,14 +11658,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11684,7 +11684,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11697,7 +11697,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11710,7 +11710,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11734,7 +11734,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:106f3cf414881d14a285a18919bfec14d2d1ca23
commit 106f3cf414881d14a285a18919bfec14d2d1ca23
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:8e6d1811a6aae7902225fb37a97214c3a2fed32b
commit 8e6d1811a6aae7902225fb37a97214c3a2fed32b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:0e8ef1e608028e5812900b717406d1901d98d4cf
commit 0e8ef1e608028e5812900b717406d1901d98d4cf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] add sqrt options and test for sqrt support in ppc tests
https://gcc.gnu.org/g:4488f8d930768029f3ca3b18709a2652462bd7c5
commit 4488f8d930768029f3ca3b18709a2652462bd7c5
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:06 2024 -0300
add sqrt options and test for sqrt support in ppc tests
Some powerpc tests that require the fsqrt insn to be enabled
explicitly use the -mpowerpc-gpopt option. This fails if the fsqrt
opcode is not available on the target machine.
Switch to dg-add-options sqrt_insn for compile tests, that adds the
option for the feature (pending approval of another patch for the same
PR), and to dg-require-effective-target sqrt_insn for execution tests.
for gcc/testsuite/ChangeLog
PR testsuite/99371
* gcc.target/powerpc/pr46728-10.c: Drop explicit
-mpowerpc-gpopt in favor of dg-require-effective-target sqrt_insn.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
* gcc.target/powerpc/pr46728-15.c: Likewise.
* gcc.target/powerpc/recip-7.c: Likewise.
* gcc.target/powerpc/pr46728-1.c: Drop explicit
-mpowerpc-gpopt in favor of dg-add-options sqrt_insn.
* gcc.target/powerpc/pr46728-2.c: Likewise.
* gcc.target/powerpc/pr46728-3.c: Likewise.
* gcc.target/powerpc/pr46728-4.c: Likewise.
* gcc.target/powerpc/pr46728-5.c: Likewise.
* gcc.target/powerpc/pr46728-7.c: Likewise.
* gcc.target/powerpc/pr46728-8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr46728-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-15.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-2.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-4.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-5.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-7.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-8.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/recip-7.c| 3 ++-
13 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
index fc2cd7d7c9c..b561d8b6e42 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt -fno-ident" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -fno-ident"
} */
+/* { dg-add-options sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..cdde53b8de0 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..62b49b14793 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..3e55fa86e0b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..472b9d5b601 100644
--- a/gcc/testsuite/gcc.t
[gcc(refs/users/aoliva/heads/testme)] add -mpowerpc-gpopt to options for sqrt insn on PowerPC
https://gcc.gnu.org/g:032f38d814d0ba4f8713e616f21b0475d4e61937
commit 032f38d814d0ba4f8713e616f21b0475d4e61937
Author: Eric Botcazou
Date: Sun Apr 21 17:23:56 2024 -0300
add -mpowerpc-gpopt to options for sqrt insn on PowerPC
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (add_options_for_sqrt_insn): For
PowerPC targets, add -mpowerpc-gpopt option.
Diff:
---
gcc/testsuite/gcc.dg/gimplefe-28.c| 1 +
gcc/testsuite/lib/target-supports.exp | 3 +++
2 files changed, 4 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c
b/gcc/testsuite/gcc.dg/gimplefe-28.c
index d2f6b4c5c3d..5f478b32d52 100644
--- a/gcc/testsuite/gcc.dg/gimplefe-28.c
+++ b/gcc/testsuite/gcc.dg/gimplefe-28.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target sqrt_insn } } */
/* { dg-options "-fgimple -O2" } */
/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
double __GIMPLE
f1 (double x)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..ec753b19e2f 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9260,6 +9260,9 @@ proc add_options_for_sqrt_insn { flags } {
if { [istarget arm*-*-*] } {
return [add_options_for_arm_vfp "$flags"]
}
+if { [istarget powerpc*-*-*] } {
+ return "$flags -mpowerpc-gpopt"
+}
return $flags
}
[gcc(refs/users/aoliva/heads/testme)] enable sqrt insns for cdce3.c
https://gcc.gnu.org/g:048689c644c10a99d8618bd0479f727e87e74b90
commit 048689c644c10a99d8618bd0479f727e87e74b90
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:00 2024 -0300
enable sqrt insns for cdce3.c
The test expects shrink-wrapping of the fsqrt call, but that will only
occur when there is a usable sqrt insn.
Arrange for dejagnu to add the options that enable the sqrt insn, if
one is available, and to skip the test otherwise.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Add sqrt insn options.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..218c24d38f1 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
-/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
float sqrtf (float);
float foo (float x)
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [ppc64] expect error on vxworks too
https://gcc.gnu.org/g:6996207325751e10e468d03c9fe492f2ad5161f2
commit 6996207325751e10e468d03c9fe492f2ad5161f2
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:52 2024 -0300
[testsuite] [ppc64] expect error on vxworks too
These ppc lp64 tests check for errors or warnings on -mno-powerpc64.
On powerpc64-*-vxworks* we get the same errors as on most other
covered platforms, but the tests did not mark them as expected for
this target. On powerpc-*-vxworks*, the tests are skipped because
lp64 is not satisfied, so I'm naming powerpc*-*-vxworks* rather than
something more specific.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr106680-1.c: Error on vxworks too.
* gcc.target/powerpc/pr106680-2.c: Likewise.
* gcc.target/powerpc/pr106680-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr106680-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-3.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
index d624d43230a..aadaa614cfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
index a9ed73726ef..f0758e30335 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
@@ -9,6 +9,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
index b642d5c7a00..bca012e2cf6 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:0cbe32956b7bd3c91c90531cff119b6bd97efcc4
commit 0cbe32956b7bd3c91c90531cff119b6bd97efcc4
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:46 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..ac15ae18197 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g
-O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if defined (__ARM_FEATURE_BTI_DEFAULT)
#error "Feature test macro __A
[gcc/aoliva/heads/testme] (40 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: b6144ccafe3... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 8895abceb69... [testsuite] [arm] add effective target and options for pacb Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 8895abc... [testsuite] [arm] add effective target and options for pacb 4c6efa3... [libstdc++] introduce --disable-compat-libstdcxx-abi Summary of changes (added commits): --- b6144cc... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0197e8f... ppc: testsuite: vec-mul requires vsx runtime 89e5150... add explicit ABI and align options to pr88233.c fe3c0a3... ppc: testsuite: pr79004 needs -mlong-double-128 2d28d2a... Request check for hw support in ppc run tests with -maltive ad51db7... decay vect tests from run to link for pr95401 106f3cf... adjust vectorization expectations for ppc costmodel 76b 8e6d181... disable ldist for test, to restore vectorizing-candidate lo 0e8ef1e... xfail fetestexcept test - ppc always uses fcmpu 4488f8d... add sqrt options and test for sqrt support in ppc tests 048689c... enable sqrt insns for cdce3.c 032f38d... add -mpowerpc-gpopt to options for sqrt insn on PowerPC 6996207... [testsuite] [ppc64] expect error on vxworks too 0cbe329... [testsuite] [arm] add effective target and options for pacb f17d31e... Fortran: Detect 'no implicit type' error in right place [PR (*) a44d16e... AVR: target/114794 - Tweak __udivmodqi4 (*) ef23922... Revert "RISC-V: Support highpart register overlap for widen (*) d37b34f... RISC-V: Add xfail test case for incorrect overlap on v0 (*) a7d01a7... Daily bump. (*) 3afcb04... Revert "RISC-V: Fix overlap group incorrect overlap on v0" (*) f9a48fe... PR modula2/112893 full type checking between proctype and p (*) 1690e47... RISC-V: Add xfail test case for wv insn highest overlap (*) f5447ea... Revert "RISC-V: Support highest overlap for wv instructions (*) 9f10005... RISC-V: Add xfail test case for wv insn register overlap (*) 0cbeafe... Revert "RISC-V: Support one more overlap for wv instruction (*) 90ded75... Daily bump. (*) c23db3e... i386: Fix up *avx2_eq3 constraints [PR114783] (*) 2afdecc... c-family: Allow arguments with NULLPTR_TYPE as sentinels [P (*) a39983b... c: Fix ICE with -g and -std=c23 related to incomplete types (*) d86472a... libstdc++: Simplify constraints on <=> for std::reference_w (*) eed7fb1... libstdc++: Support link chains in std::chrono::tzdb::locate (*) e8f0540... Update gcc sv.po (*) 33bf8e5... internal-fn: Fix up expand_arith_overflow [PR114753] (*) 1216460... middle-end: refactory vect_recog_absolute_difference to sim (*) 9451b6c... Enable 'gcc.dg/pr114768.c' for nvptx target [PR114768] (*) ede01df... bpf: remove huge memory waste with string allocation. (*) d7190d0... bpf: support more instructions to match CO-RE relocations (*) 4d4929f... d: Fix ICE in build_deref, at d/d-codegen.cc:1650 [PR111650 (*) 9f29584... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*) 36f4c8a... libgcc: Another __divmodbitint4 bug fix [PR114762] (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testme' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc/aoliva/heads/testbase] (26 commits) Fortran: Detect 'no implicit type' error in right place [PR
The branch 'aoliva/heads/testbase' was updated to point to: f17d31e709a... Fortran: Detect 'no implicit type' error in right place [PR It previously pointed to: 694fa3717a9... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__ Diff: Summary of changes (added commits): --- f17d31e... Fortran: Detect 'no implicit type' error in right place [PR (*) a44d16e... AVR: target/114794 - Tweak __udivmodqi4 (*) ef23922... Revert "RISC-V: Support highpart register overlap for widen (*) d37b34f... RISC-V: Add xfail test case for incorrect overlap on v0 (*) a7d01a7... Daily bump. (*) 3afcb04... Revert "RISC-V: Fix overlap group incorrect overlap on v0" (*) f9a48fe... PR modula2/112893 full type checking between proctype and p (*) 1690e47... RISC-V: Add xfail test case for wv insn highest overlap (*) f5447ea... Revert "RISC-V: Support highest overlap for wv instructions (*) 9f10005... RISC-V: Add xfail test case for wv insn register overlap (*) 0cbeafe... Revert "RISC-V: Support one more overlap for wv instruction (*) 90ded75... Daily bump. (*) c23db3e... i386: Fix up *avx2_eq3 constraints [PR114783] (*) 2afdecc... c-family: Allow arguments with NULLPTR_TYPE as sentinels [P (*) a39983b... c: Fix ICE with -g and -std=c23 related to incomplete types (*) d86472a... libstdc++: Simplify constraints on <=> for std::reference_w (*) eed7fb1... libstdc++: Support link chains in std::chrono::tzdb::locate (*) e8f0540... Update gcc sv.po (*) 33bf8e5... internal-fn: Fix up expand_arith_overflow [PR114753] (*) 1216460... middle-end: refactory vect_recog_absolute_difference to sim (*) 9451b6c... Enable 'gcc.dg/pr114768.c' for nvptx target [PR114768] (*) ede01df... bpf: remove huge memory waste with string allocation. (*) d7190d0... bpf: support more instructions to match CO-RE relocations (*) 4d4929f... d: Fix ICE in build_deref, at d/d-codegen.cc:1650 [PR111650 (*) 9f29584... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*) 36f4c8a... libgcc: Another __divmodbitint4 bug fix [PR114762] (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testbase' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[PATCH v2] [testsuite] [arm] add effective target and options for pacbti tests
.c
index 79dd8010d2dab..a34bb0842b632 100644
--- a/gcc/testsuite/gcc.target/arm/bti-1.c
+++ b/gcc/testsuite/gcc.target/arm/bti-1.c
@@ -1,7 +1,8 @@
/* Check that GCC does bti instruction. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -mthumb -mfloat-abi=softfp
-mbranch-protection=bti --save-temps" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp -mbranch-protection=bti
--save-temps" } */
int
main (void)
diff --git a/gcc/testsuite/gcc.target/arm/bti-2.c
b/gcc/testsuite/gcc.target/arm/bti-2.c
index 33910563849a4..e5bc4d5543a8d 100644
--- a/gcc/testsuite/gcc.target/arm/bti-2.c
+++ b/gcc/testsuite/gcc.target/arm/bti-2.c
@@ -1,8 +1,9 @@
/* { dg-do compile } */
/* -Os to create jump table. */
/* { dg-options "-Os" } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -mthumb -mfloat-abi=softfp
-mbranch-protection=bti --save-temps" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp -mbranch-protection=bti
--save-temps" } */
extern int f1 (void);
extern int f2 (void);
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:8895abceb69b6b8ecef7608923bc4a2849a9302b
commit 8895abceb69b6b8ecef7608923bc4a2849a9302b
Author: Alexandre Oliva
Date: Tue Apr 16 01:26:27 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (v8_1m_main_mve_pacbti): New arm_arch.
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..ac15ae18197 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g
-O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if
[gcc/aoliva/heads/testme] [testsuite] [arm] add effective target and options for pacb
The branch 'aoliva/heads/testme' was updated to point to: 8895abceb69... [testsuite] [arm] add effective target and options for pacb It previously pointed to: 57d1c481239... [testsuite] [arm] add effective target and options for pacb Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 57d1c48... [testsuite] [arm] add effective target and options for pacb Summary of changes (added commits): --- 8895abc... [testsuite] [arm] add effective target and options for pacb
[gcc/aoliva/heads/testme] [testsuite] [arm] add effective target and options for pacb
The branch 'aoliva/heads/testme' was updated to point to: 57d1c481239... [testsuite] [arm] add effective target and options for pacb It previously pointed to: 25268cdcc12... [testsuite] [arm] add effective target and options for pacb Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 25268cd... [testsuite] [arm] add effective target and options for pacb Summary of changes (added commits): --- 57d1c48... [testsuite] [arm] add effective target and options for pacb
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:57d1c481239e2051ff13dfa38510611c4c2fcf51
commit 57d1c481239e2051ff13dfa38510611c4c2fcf51
Author: Alexandre Oliva
Date: Tue Apr 16 01:26:27 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (v8_1m_main_mve_pacbti): New arm_arch.
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..2f898040046 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g -O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:25268cdcc128d18ed7a873046896781d909b7840
commit 25268cdcc128d18ed7a873046896781d909b7840
Author: Alexandre Oliva
Date: Tue Apr 16 01:26:27 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (v8_1m_main_mve_pacbti): New arm_arch.
* g++.target/arm/pac-1.C: Require arch, use its opts, drop skip.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* gcc.target/arm/bti-1.c: Likewise.
* gcc.target/arm/bti-2.c: Likewise.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
gcc/testsuite/lib/target-supports.exp | 2 ++
7 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..4710fbecbac 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_mve_pacbti } */
+/* { dg-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g -O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options &q
[gcc(refs/users/aoliva/heads/testme)] [libstdc++] introduce --disable-compat-libstdcxx-abi
https://gcc.gnu.org/g:4c6efa350d11a66674d85046cc7b7cbc69f6dbe1
commit 4c6efa350d11a66674d85046cc7b7cbc69f6dbe1
Author: Alexandre Oliva
Date: Tue Apr 16 01:26:20 2024 -0300
[libstdc++] introduce --disable-compat-libstdcxx-abi
A number of libstdc++ tests that implicitly instantiate
__to_chars_i and also link floating_to_chars.o in
fail on vxworks kernel mode. The platform doesn't support undefweak
symbols (the kernel module loader fails to load modules containing
them), and because creating such modules doesn't involve final
linking, only -r linking. The vague-linkage weak defs with abi-v2
mangling that get discarded from floating_to_chars.o because the same
comdat section is present in the main executable. But since the
alternate mangling is not defined in the main executable, the weak
definition decays to a weak undefined symbol in the partially-linked
kernel module, and then the kernel module loader barfs.
Since our vxworks toolchains have little use for the compat ABI
symbols, I thought we could work around this problem by getting rid of
them. Absent a configure option to control that, I added one.
for libstdc++-v3/ChangeLog
* acinclude.m4 (GLIBCXX_EXPORT_FLAGS): Split -Wabi=2...
(GLIBCXX_ENABLE_WABI): ... here. Control it with newly added
--disable-compat-libstdcxx-abi.
* configure: Rebuilt.
* doc/html/manual/configure.html: Document it.
Diff:
---
libstdc++-v3/acinclude.m4 | 26 ++-
libstdc++-v3/configure | 49 +++--
libstdc++-v3/doc/html/manual/configure.html | 4 ++-
libstdc++-v3/doc/xml/manual/configure.xml | 4 +++
4 files changed, 72 insertions(+), 11 deletions(-)
diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
index 51a08bcc8b1..2dd5aa2af89 100644
--- a/libstdc++-v3/acinclude.m4
+++ b/libstdc++-v3/acinclude.m4
@@ -707,10 +707,34 @@ AC_DEFUN([GLIBCXX_EXPORT_FLAGS], [
# OPTIMIZE_CXXFLAGS = -O3 -fstrict-aliasing -fvtable-gc
AC_SUBST(OPTIMIZE_CXXFLAGS)
- WARN_FLAGS="-Wall -Wextra -Wwrite-strings -Wcast-qual -Wabi=2"
+ WARN_FLAGS="-Wall -Wextra -Wwrite-strings -Wcast-qual"
AC_SUBST(WARN_FLAGS)
+
+ GLIBCXX_ENABLE_WABI
])
+dnl
+dnl Enable -Wabi=2 if not overridden by --disable-compat-libstdcxx-abi.
+dnl
+AC_DEFUN([GLIBCXX_ENABLE_WABI], [
+ # Default.
+ WARN_FLAGS_WABI=\ -Wabi=2
+ AC_MSG_CHECKING([for --disable-compat-libstdcxx-abi-mangling])
+ AC_ARG_ENABLE([compat-libstdcxx-abi-mangling],
+AC_HELP_STRING([--disable-compat-libstdcxx-abi-mangling],
+ [Disable backward-compatibility mangling ABI symbols]),
+[case "$enableval" in
+ yes) AC_MSG_RESULT(enabled$WARN_FLAGS_WABI) ;;
+ no) WARN_FLAGS_WABI=
+ AC_MSG_RESULT(disabled) ;;
+ *) AC_MSG_RESULT(unsupported)
+ AC_MSG_ERROR([Unsupported argument to enable/disable compat
libstdc++ abi mangling]);;
+ esac], [
+ AC_MSG_RESULT(defaulting to enabled$WARN_FLAGS_WABI)
+ ])
+
+ WARN_FLAGS="$WARN_FLAGS$WARN_FLAGS_WABI"
+])
dnl
dnl All installation directory information is determined here.
diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
index 21abaeb0778..af03d5f96f4 100755
--- a/libstdc++-v3/configure
+++ b/libstdc++-v3/configure
@@ -973,6 +973,7 @@ enable_cet
with_gxx_include_dir
enable_version_specific_runtime_libs
with_toolexeclibdir
+enable_compat_libstdcxx_abi_mangling
with_gcc_major_version_only
'
ac_precious_vars='build_alias
@@ -1689,6 +1690,8 @@ Optional Features:
--enable-version-specific-runtime-libs
Specify that runtime libraries should be installed
in a compiler-specific directory
+ --disable-compat-libstdcxx-abi-mangling
+ Disable backward-compatibility mangling ABI symbols
Optional Packages:
--with-PACKAGE[=ARG]use PACKAGE [ARG=yes]
@@ -12280,7 +12283,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12283 "configure"
+#line 12286 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12386,7 +12389,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12389 "configure"
+#line 12392 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -16182,7 +16185,7 @@ $as_echo "$glibcxx_cv_atomic_long_long" >&6; }
# Fake what AC_TRY_COMPILE does.
cat > conftest.$ac_ext << EOF
-#line 16185 "configure"
+#line 16188 "configure"
int main()
{
typedef bool atomic_type;
@@ -16217,7 +16220,7 @@ $as_echo "$glibcxx_cv_atomic_bool" >&a
[gcc/aoliva/heads/testbase] (49 commits) [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__
The branch 'aoliva/heads/testbase' was updated to point to:
694fa3717a9... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__
It previously pointed to:
46d914d0e0b... LoongArch: Add indexes for some compilation options.
Diff:
Summary of changes (added commits):
---
694fa37... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__ (*)
85c187b... Daily bump. (*)
e498ba9... Add nios2*-*-* to the list of obsolete targets (*)
e243d0f... Fortran: Fix ICE and clear incorrect error messages [PR1147 (*)
7eecc08... [testsuite] [i386] add -msse2 to tests that require it (*)
0ea96af... [testsuite] [i386] work around fails with --enable-frame-po (*)
36d0038... [testsuite] [arm] accept empty init for bfloat16 (*)
ce2dfc5... [c++] [testsuite] adjust contracts9.C for negative addresse (*)
df92df0... [testsuite] [aarch64] Require fpic effective target. (*)
514c6b1... [testsuite] [i386] require fpic for pr111497.C (*)
cc02ebf... [testsuite] xfail pr103798-2 in C++ on vxworks too [PR11370 (*)
e965162... [testsuite] [analyzer] include sys/select.h if available (*)
8a11709... [testsuite] [analyzer] require fork where used (*)
5be4f20... [testsuite] [analyzer] skip access-mode: O_ACCMODE on vxwor (*)
76a1bcc... [testsuite] [analyzer] avoid vxworks libc mode_t (*)
5dfbc05... [testsuite] introduce strndup effective target (*)
dcf0bd1... [libstdc++] [testsuite] disable SRA for compare_exchange_pa (*)
5b17817... [libstdc++] [testsuite] xfail double-prec from_chars for fl (*)
da3504a... [libstdc++] define zoneinfo_dir_override on vxworks (*)
a2f4be3... AArch64: remove reliance on register allocator for simd/gpr (*)
82d6d38... libgcc: Fix up __divmodbitint4 [PR114755] (*)
6c152c9... internal-fn: Temporarily disable flag_trapv during .{ADD,SU (*)
6e62ede... testsuite, rs6000: Fix builtins-6-p9-runnable.c for BE [PR1 (*)
58a0b19... rs6000: Fix bcd test case (*)
69576bc... Daily bump. (*)
7c2a9db... libstdc++: Implement "Printing blank lines with println" fo (*)
5705614... DOCUMENTATION_ROOT_URL vs. release branches [PR114738] (*)
a9fefbf... libcpp: Regenerate aclocal.m4 and configure [PR 114748] (*)
bf2b523... tree-optimization/114749 - reset partial vector decision fo (*)
420ece6... GCN: Enable effective-target 'vect_long_long' (*)
909c6fa... AVR: target/114752 - Fix ICE on inline asm const 64-bit flo (*)
3cfe94a... libstdc++: Add include guard to simd-internal header (*)
0fc7f3c... libstdc++: Avoid ill-formed types on ARM (*)
299d14a... asan: Don't instrument .ABNORMAL_DISPATCHER [PR114743] (*)
9c7cf5d... Daily bump. (*)
eadd05d... PR modula2/114745: const cast causes ICE (*)
f438acf... testsuite: Fix data check loop on vect-early-break_124-pr11 (*)
48024a9... Fortran: ALLOCATE of fixed-length CHARACTER with SOURCE/MOL (*)
4437482... libstdc++: Fix "extact" typos in comments (*)
8eddd87... Document that vector_size works with typedefs [PR92880] (*)
f949481... tree-optimization/114736 - SLP DFS walk issue (*)
45a41ac... tree-optimization/114733 - neg induction fails for 1 elemen (*)
a7578a0... OpenACC 2.7: Adjust acc_map_data/acc_unmap_data interaction (*)
274f6bb... Fix some comment nits (*)
dc17e75... build: Use of cargo not yet supported here in Canadian cros (*)
3ebc789... build: Don't check for host-prefixed 'cargo' program (*)
79ff534... c++: Handle ARRAY_TYPE in check_bit_cast_type [PR114706] (*)
6e925ba... optimize Zicond conditional select cases. (*)
c39dc5b... [strub] improve handling of indirected volatile parms [PR11 (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/aoliva/heads/testbase' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
[gcc/aoliva/heads/testme] (50 commits) [testsuite] [arm] add effective target and options for pacb
The branch 'aoliva/heads/testme' was updated to point to:
25268cdcc12... [testsuite] [arm] add effective target and options for pacb
It previously pointed to:
e84f9abf5f1... [tree-prof] skip if errors were seen [PR113681]
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
---
e84f9ab... [tree-prof] skip if errors were seen [PR113681]
d11ff38... [testsuite] [i386] add -msse2 to tests that require it
d248480... [testsuite] [i386] work around fails with --enable-frame-po
221ab03... [testsuite] [arm] accept empty init for bfloat16
dbb7504... [libstdc++] [testsuite] disable SRA for compare_exchange_pa
b2e888a... [testsuite] [arm] require arm_v8_1m_main for pacbti tests
0b08e8a... [testsuite] [i386] require fpic for pr111497.C
0e6e6eb... [libstdc++] introduce --disable-compat-libstdcxx-abi
2605981... [testsuite] xfail pr103798-2 in C++ on vxworks too [PR11370
4c377a9... [testsuite] [analyzer] include sys/select.h if available
830e318... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__
9437abf... [testsuite] [analyzer] require fork where used
b70fc19... [testsuite] [analyzer] skip access-mode: O_ACCMODE on vxwor
7be5dbe... [testsuite] [analyzer] avoid vxworks libc mode_t
dcf1da0... [testsuite] introduce strndup effective target
eaf15b1... [c++] [testsuite] adjust contracts9.C for negative addresse
e7efbca... [libstdc++] [testsuite] xfail double-prec from_chars for fl
80122a3... [libstdc++] define zoneinfo_dir_override on vxworks
c2a86f4... [testsuite] [aarch64] Require fpic effective target.
Summary of changes (added commits):
---
25268cd... [testsuite] [arm] add effective target and options for pacb
4c6efa3... [libstdc++] introduce --disable-compat-libstdcxx-abi
694fa37... [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__ (*)
85c187b... Daily bump. (*)
e498ba9... Add nios2*-*-* to the list of obsolete targets (*)
e243d0f... Fortran: Fix ICE and clear incorrect error messages [PR1147 (*)
7eecc08... [testsuite] [i386] add -msse2 to tests that require it (*)
0ea96af... [testsuite] [i386] work around fails with --enable-frame-po (*)
36d0038... [testsuite] [arm] accept empty init for bfloat16 (*)
ce2dfc5... [c++] [testsuite] adjust contracts9.C for negative addresse (*)
df92df0... [testsuite] [aarch64] Require fpic effective target. (*)
514c6b1... [testsuite] [i386] require fpic for pr111497.C (*)
cc02ebf... [testsuite] xfail pr103798-2 in C++ on vxworks too [PR11370 (*)
e965162... [testsuite] [analyzer] include sys/select.h if available (*)
8a11709... [testsuite] [analyzer] require fork where used (*)
5be4f20... [testsuite] [analyzer] skip access-mode: O_ACCMODE on vxwor (*)
76a1bcc... [testsuite] [analyzer] avoid vxworks libc mode_t (*)
5dfbc05... [testsuite] introduce strndup effective target (*)
dcf0bd1... [libstdc++] [testsuite] disable SRA for compare_exchange_pa (*)
5b17817... [libstdc++] [testsuite] xfail double-prec from_chars for fl (*)
da3504a... [libstdc++] define zoneinfo_dir_override on vxworks (*)
a2f4be3... AArch64: remove reliance on register allocator for simd/gpr (*)
82d6d38... libgcc: Fix up __divmodbitint4 [PR114755] (*)
6c152c9... internal-fn: Temporarily disable flag_trapv during .{ADD,SU (*)
6e62ede... testsuite, rs6000: Fix builtins-6-p9-runnable.c for BE [PR1 (*)
58a0b19... rs6000: Fix bcd test case (*)
69576bc... Daily bump. (*)
7c2a9db... libstdc++: Implement "Printing blank lines with println" fo (*)
5705614... DOCUMENTATION_ROOT_URL vs. release branches [PR114738] (*)
a9fefbf... libcpp: Regenerate aclocal.m4 and configure [PR 114748] (*)
bf2b523... tree-optimization/114749 - reset partial vector decision fo (*)
420ece6... GCN: Enable effective-target 'vect_long_long' (*)
909c6fa... AVR: target/114752 - Fix ICE on inline asm const 64-bit flo (*)
3cfe94a... libstdc++: Add include guard to simd-internal header (*)
0fc7f3c... libstdc++: Avoid ill-formed types on ARM (*)
299d14a... asan: Don't instrument .ABNORMAL_DISPATCHER [PR114743] (*)
9c7cf5d... Daily bump. (*)
eadd05d... PR modula2/114745: const cast causes ICE (*)
f438acf... testsuite: Fix data check loop on vect-early-break_124-pr11 (*)
48024a9... Fortran: ALLOCATE of fixed-length CHARACTER with SOURCE/MOL (*)
4437482... libstdc++: Fix "extact" typos in comments (*)
8eddd87... Document that vector_size works with typedefs [PR92880] (*)
f949481... tree-optimization/114736 - SLP DFS walk issue (*)
45a41ac... tree-optimization/114733 - neg induction fails for 1 elemen (*)
a7578a0... OpenACC 2.7: Adjust acc_map_data/acc_unmap_data interaction (*)
274f6bb... Fix some comment nits (*)
dc17e75... build: Use of cargo not yet supported here in Canadian cros (*)
3ebc789... build: Don't check for host-prefixed 'cargo' program (*)
79ff534... c++: Handle ARRAY_TYPE in
Re: [PATCH] [testsuite] [arm] require arm_v8_1m_main for pacbti tests
On Apr 16, 2024, "Richard Earnshaw (lists)" wrote:
> The require-effective-target flags test whether a specific set of
> flags will make the compilation work, so they need to be used in
> conjunction with the corresponding dg-add-options flags that then
> apply those options.
*nod*, that's the theory. Problem is the architectures suported by
[add_options_for_]arm_arch_*[_ok] do not match exactly those expected by
the tests, and I can't quite tell whether the subtle changes they would
introduce would change what they intend to test, or even whether the
differences are irrelevant, or would be sensible to add as variants to
the dg machinery. I think it would take someone more familiar than I am
with all of the ARM variants to do this correctly. I don't even know
how these changes would need to be tested to be sure they remain
correct.
Would you be willing to take it from here, or would you accept the patch
as an incremental yet imperfect improvement, or would you prefer to
guide me in making it correct, and in verifying it (there are questions
below)? I don't have a lot of cycles to put into this (we've already
worked around the testsuite bugs we ran into), but it would be desirable
to get a fix into GCC as well, if we can converge on one without
unreasonably burdening anyone.
v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
v8_1m_main_pacbti "-march=armv8.1-m.main+pacbti+fp -mthumb"
"__ARM_ARCH_8M_MAIN__ && __ARM_FEATURE_BTI &&
__ARM_FEATURE_PAUTH
Why do these have +fp in -march but not in the v8_1m* arch name?
gcc/testsuite/g++.target/arm/pac-1.C:
/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
v8_1m_main_pacbti plus +mve minus +fp.
Do we need a dg arch for that?
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c:
/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c:
/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
v8_1m_main_pacbti minus -mthumb.
AFAICT the -mthumb is redundant.
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c:
/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
v8_1m_main minus -mthumb.
AFAICT the -mthumb is redundant.
gcc/testsuite/gcc.target/arm/bti-1.c:
/* { dg-options "-march=armv8.1-m.main -mthumb -mfloat-abi=softfp
-mbranch-protection=bti --save-temps" } */
gcc/testsuite/gcc.target/arm/bti-2.c:
/* { dg-options "-march=armv8.1-m.main -mthumb -mfloat-abi=softfp
-mbranch-protection=bti --save-temps" } */
v8_1m_main minus +fp.
Can these be bumped to +fp, or do we need an extra dg arch?
Are these missing +pacbti?
Thanks,
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[gcc r14-10033] [vxworks] avoid mangling __STDC_VERSION_LIMITS_H__
https://gcc.gnu.org/g:694fa3717a908317e895543d949eb7180911615a
commit r14-10033-g694fa3717a908317e895543d949eb7180911615a
Author: Alexandre Oliva
Date: Fri Apr 19 02:52:21 2024 -0300
[vxworks] avoid mangling __STDC_VERSION_LIMITS_H__
The mangling of the macro name that guards limits.h from reinclusion
was mangling a c23-required macro as well. Make the edit pattern
stricter.
for gcc/ChangeLog
* config/t-vxworks (vxw-glimits.h): Don't mangle c23-required
__STDC_VERSION_LIMITS_H__ define.
Diff:
---
gcc/config/t-vxworks | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/t-vxworks b/gcc/config/t-vxworks
index b89350c3c70..6063943e346 100644
--- a/gcc/config/t-vxworks
+++ b/gcc/config/t-vxworks
@@ -57,7 +57,7 @@ T_GLIMITS_H = vxw-glimits.h
vxw-glimits.h: $(srcdir)/glimits.h
ID=`echo $(BASEVER_c) | sed -e 's/\./_/g'` && \
- sed -e "s/_LIMITS_H__/_LIMITS_H__$${ID}_/" < $< > $@T
+ sed -e "s/_LIMITS_H___/_LIMITS_H__$${ID}_/" < $< > $@T
mv $@T $@
# Arrange to "provide" a tailored version of stdint-gcc.h
Re: [PATCH] [libstdc++] introduce --disable-compat-libstdcxx-abi
On Apr 16, 2024, Jonathan Wakely wrote: >> +dnl >> +dnl Enable -Wabi=2 if not overridden by --disable-compat-libstdcxx-abi. >> +dnl >> +AC_DEFUN([GLIBCXX_ENABLE_WABI], [ >> + # Default. >> + WARN_FLAGS_WABI=\ -Wabi=2 >> + AC_MSG_CHECKING([for --disable-compat-libstdcxx-abi]) >> + AC_ARG_ENABLE([compat-libstdcxx-abi], > We have the GLIBCXX_ENABLE macro to simplify creating new --enable options. *nod*. There was some reason why I didn't use it at first. Maybe it can be used with the patch as it ended up. Will revisit. >> +AC_HELP_STRING([--disable-compat-libstdcxx-abi], >> + [Disable backward-compatibility ABI symbols)]), > There's a stray ')' here. Ugh, thanks >> --- a/libstdc++-v3/doc/html/manual/configure.html >> +++ b/libstdc++-v3/doc/html/manual/configure.html > This should be in doc/xml/manual/configure.xml too, which is used to > generate the HTML using docbook. Oh, right. Doh. So much for grepping for an existing option and jumping to edit the first match :-) > The description here in the docs (and the name of the configure > option) seem much too vague. Libstdc++ has dozens, probably hundreds, > of "backward-compatibility ABI symbols", and this only affects touches > a tiny handful of them. Just the aliases created automatically by the > compiler for mangling changes, right? Yeah. I had used --disable-libstdcxx-Wabi at some point, maybe that's better. FTR, we now have a binutils patch (thanks H.J.Lu) to address the underlying problem, so we'll probably no longer need the workaround that led me to propose this change. I wonder if there's interest in keeping it. I'd be equally happy to make the adjustments, or to withdraw it (or pretty much anything in between ;-). WDYT? -- Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/ Free Software Activist GNU Toolchain Engineer More tolerance and less prejudice are key for inclusion and diversity Excluding neuro-others for not behaving ""normal"" is *not* inclusive
Re: [PATCH] [testsuite] introduce strndup effective target
On Apr 16, 2024, Alexandre Oliva wrote:
> * gcc.dg/builtin-dynamic-object-size-1.c: Likewise.
> * gcc.dg/builtin-dynamic-object-size-2.c: Likewise.
> * gcc.dg/builtin-dynamic-object-size-3.c: Likewise.
> * gcc.dg/builtin-dynamic-object-size-4.c: Likewise.
These hunks were missing from the patch I posted, sorry. I goofed when
resolving the conflicts because the tests had been modified after
gcc-13. I hope the intent was clear from the ChangeLog entry.
Here they are.
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
index ffa59985024f5..76b4f704fed9c 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -Wno-stringop-overread" } */
/* { dg-require-effective-target alloca } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#define __builtin_object_size __builtin_dynamic_object_size
#include "builtin-object-size-1.c"
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-2.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-2.c
index fff32da7aea14..cb757a8d699cf 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-2.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-2.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -Wno-stringop-overread" } */
/* { dg-require-effective-target alloca } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#define __builtin_object_size __builtin_dynamic_object_size
#include "builtin-object-size-2.c"
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-3.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-3.c
index ac223d67b10a4..8a12f023f27bc 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-3.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-3.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -Wno-stringop-overread" } */
/* { dg-require-effective-target alloca } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#define __builtin_object_size __builtin_dynamic_object_size
#include "builtin-object-size-3.c"
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-4.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-4.c
index fdf4284ae1158..0efc2d9858422 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-4.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-4.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -Wno-stringop-overread" } */
/* { dg-require-effective-target alloca } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#define __builtin_object_size __builtin_dynamic_object_size
#include "builtin-object-size-4.c"
--
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity
Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[gcc r14-10029] [testsuite] [i386] add -msse2 to tests that require it
https://gcc.gnu.org/g:7eecc08ccf75679e6ae688d92e50afae935547ab
commit r14-10029-g7eecc08ccf75679e6ae688d92e50afae935547ab
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:43 2024 -0300
[testsuite] [i386] add -msse2 to tests that require it
Without -msse2, an i586-targeting toolchain fails bf16_short_warn.c
because neither type __m128bh nor intrinsic _mm_cvtneps_pbh get
declared.
for gcc/testsuite/ChangeLog
* gcc.target/i386/bf16_short_warn.c: Add -msse2.
Diff:
---
gcc/testsuite/gcc.target/i386/bf16_short_warn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/i386/bf16_short_warn.c
b/gcc/testsuite/gcc.target/i386/bf16_short_warn.c
index 3e47a815200..2e05624bc26 100644
--- a/gcc/testsuite/gcc.target/i386/bf16_short_warn.c
+++ b/gcc/testsuite/gcc.target/i386/bf16_short_warn.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -msse2" } */
#include
typedef struct {
[gcc r14-10028] [testsuite] [i386] work around fails with --enable-frame-pointer
https://gcc.gnu.org/g:0ea96af1150c221092a0880af51dbe66b75ecb03
commit r14-10028-g0ea96af1150c221092a0880af51dbe66b75ecb03
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:40 2024 -0300
[testsuite] [i386] work around fails with --enable-frame-pointer
A few x86 tests get unexpected insn counts if the toolchain is
configured with --enable-frame-pointer. Add explicit
-fomit-frame-pointer so that the expected insn sequences are output.
for gcc/testsuite/ChangeLog
* gcc.target/i386/pr107261.c: Add -fomit-frame-pointer.
* gcc.target/i386/pr69482-1.c: Likewise.
* gcc.target/i386/pr69482-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/i386/pr107261.c | 2 +-
gcc/testsuite/gcc.target/i386/pr69482-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr69482-2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr107261.c
b/gcc/testsuite/gcc.target/i386/pr107261.c
index eb1d232fbfc..b422af9cbf9 100644
--- a/gcc/testsuite/gcc.target/i386/pr107261.c
+++ b/gcc/testsuite/gcc.target/i386/pr107261.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -msse2" } */
+/* { dg-options "-O2 -msse2 -fomit-frame-pointer" } */
typedef __bf16 v4bf __attribute__ ((vector_size (8)));
typedef __bf16 v2bf __attribute__ ((vector_size (4)));
diff --git a/gcc/testsuite/gcc.target/i386/pr69482-1.c
b/gcc/testsuite/gcc.target/i386/pr69482-1.c
index 99bb6ad5a37..7ef0e71b17c 100644
--- a/gcc/testsuite/gcc.target/i386/pr69482-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr69482-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -fno-stack-protector" } */
+/* { dg-options "-O3 -fno-stack-protector -fomit-frame-pointer" } */
static inline void memset_s(void* s, int n) {
volatile unsigned char * p = s;
diff --git a/gcc/testsuite/gcc.target/i386/pr69482-2.c
b/gcc/testsuite/gcc.target/i386/pr69482-2.c
index 58e89a79333..6aabe4fb393 100644
--- a/gcc/testsuite/gcc.target/i386/pr69482-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr69482-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
void bar ()
{
[gcc r14-10027] [testsuite] [arm] accept empty init for bfloat16
https://gcc.gnu.org/g:36d003816352052f610a3f63ab74b6443eb7efb7
commit r14-10027-g36d003816352052f610a3f63ab74b6443eb7efb7
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:37 2024 -0300
[testsuite] [arm] accept empty init for bfloat16
Complete r13-2205, adjusting an arm-specific test that expects a
no-longer-issued error at an empty initializer.
for gcc/testsuite/ChangeLog
* gcc.target/arm/bfloat16_scalar_typecheck.c: Accept C23
empty initializers.
Diff:
---
gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c
b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c
index 8c80c55bc9f..04ede93bda1 100644
--- a/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c
+++ b/gcc/testsuite/gcc.target/arm/bfloat16_scalar_typecheck.c
@@ -42,7 +42,7 @@ bfloat16_t footest (bfloat16_t scalar0)
short initi_1_4 = glob_bfloat; /* { dg-error {invalid conversion from type
'bfloat16_t'} } */
double initi_1_5 = glob_bfloat; /* { dg-error {invalid conversion from type
'bfloat16_t'} } */
- bfloat16_t scalar2_1 = {}; /* { dg-error {empty scalar initializer} } */
+ bfloat16_t scalar2_1 = {};
bfloat16_t scalar2_2 = { glob_bfloat };
bfloat16_t scalar2_3 = { 0 }; /* { dg-error {invalid conversion to type
'bfloat16_t'} } */
bfloat16_t scalar2_4 = { 0.1 }; /* { dg-error {invalid conversion to type
'bfloat16_t'} } */
@@ -94,7 +94,7 @@ bfloat16_t footest (bfloat16_t scalar0)
/* Compound literals. */
- (bfloat16_t) {}; /* { dg-error {empty scalar initializer} } */
+ (bfloat16_t) {};
(bfloat16_t) { glob_bfloat };
(bfloat16_t) { 0 }; /* { dg-error {invalid conversion to type 'bfloat16_t'}
} */
(bfloat16_t) { 0.1 }; /* { dg-error {invalid conversion to type
'bfloat16_t'} } */
[gcc r14-10026] [c++] [testsuite] adjust contracts9.C for negative addresses
https://gcc.gnu.org/g:ce2dfc57b4562fef0d279697d96f672bc903e853
commit r14-10026-gce2dfc57b4562fef0d279697d96f672bc903e853
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:35 2024 -0300
[c++] [testsuite] adjust contracts9.C for negative addresses
The test expected the address of a literal string, converted to long
long, to yield a positive value. That expectation doesn't necessarily
hold, and the test fails where it doesn't.
Adjust the test to use a pointer that will compare as expected.
for gcc/testsuite/ChangeLog
* g++.dg/contracts/contracts9.C: Don't assume string literals
have non-negative addresses.
Diff:
---
gcc/testsuite/g++.dg/contracts/contracts9.C | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/g++.dg/contracts/contracts9.C
b/gcc/testsuite/g++.dg/contracts/contracts9.C
index 09a1a6532c5..58b60aca320 100644
--- a/gcc/testsuite/g++.dg/contracts/contracts9.C
+++ b/gcc/testsuite/g++.dg/contracts/contracts9.C
@@ -27,7 +27,7 @@ int main()
{
fun1(1, -1);
fun1(-1, 1.0);
- fun1(-1, "test");
+ fun1(-1, (const char *)0x1234);
[[ assert: fun1(-1, -5) ]];
[[ assert: test::fun(10, -6) ]];
[gcc r14-10025] [testsuite] [aarch64] Require fpic effective target.
https://gcc.gnu.org/g:df92df0c19f7783519a392f7ac7d4e617250c328
commit r14-10025-gdf92df0c19f7783519a392f7ac7d4e617250c328
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:32 2024 -0300
[testsuite] [aarch64] Require fpic effective target.
Co-authored-by: Olivier Hainque
for gcc/testsuite/ChangeLog
* gcc.target/aarch64/pr94201.c: Add missing
dg-require-effective-target fpic.
* gcc.target/aarch64/pr103085.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/aarch64/pr103085.c | 1 +
gcc/testsuite/gcc.target/aarch64/pr94201.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/pr103085.c
b/gcc/testsuite/gcc.target/aarch64/pr103085.c
index dbc9c15b71f..347280ed42b 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr103085.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr103085.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -fstack-protector-strong -fPIC" } */
+/* { dg-require-effective-target fpic } */
void g(int*);
void
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94201.c
b/gcc/testsuite/gcc.target/aarch64/pr94201.c
index 69176169186..3b9b79059e0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr94201.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr94201.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mcmodel=tiny -mabi=ilp32 -fPIC" } */
+/* { dg-require-effective-target fpic } */
extern int bar (void *);
extern long long a;
[gcc r14-10024] [testsuite] [i386] require fpic for pr111497.C
https://gcc.gnu.org/g:514c6b1cb766dc0a14121016ce84b9f5a1ef4e41
commit r14-10024-g514c6b1cb766dc0a14121016ce84b9f5a1ef4e41
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:29 2024 -0300
[testsuite] [i386] require fpic for pr111497.C
Fix another test that uses -fPIC without requiring fpic support.
for gcc/testsuite/ChangeLog
* g++.target/i386/pr111497.C: Require fpic support.
Diff:
---
gcc/testsuite/g++.target/i386/pr111497.C | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/g++.target/i386/pr111497.C
b/gcc/testsuite/g++.target/i386/pr111497.C
index a645bb95907..30e2e0409ad 100644
--- a/gcc/testsuite/g++.target/i386/pr111497.C
+++ b/gcc/testsuite/g++.target/i386/pr111497.C
@@ -1,5 +1,6 @@
// { dg-do compile { target ia32 } }
// { dg-options "-march=i686 -mtune=generic -fPIC -O2 -g" }
+// { dg-require-effective-target fpic }
class A;
struct B { const char *b1; int b2; };
[gcc r14-10023] [testsuite] xfail pr103798-2 in C++ on vxworks too [PR113706]
https://gcc.gnu.org/g:cc02ebfcfd0755b330c50a840ab713fedd6d8887
commit r14-10023-gcc02ebfcfd0755b330c50a840ab713fedd6d8887
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:26 2024 -0300
[testsuite] xfail pr103798-2 in C++ on vxworks too [PR113706]
pr103798-2.c fails in C++ on targets that provide a ISO C++-compliant
declaration of memchr, because it mismatches the C-compatible builtin,
as per PR113706. Expect the C++ test to fail on vxworks as well.
for gcc/testsuite/ChangeLog
PR testsuite/113706
* c-c++-common/pr103798-2.c: XFAIL in C++ on vxworks too.
Diff:
---
gcc/testsuite/c-c++-common/pr103798-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/c-c++-common/pr103798-2.c
b/gcc/testsuite/c-c++-common/pr103798-2.c
index bc126c205e1..83cdfaa1660 100644
--- a/gcc/testsuite/c-c++-common/pr103798-2.c
+++ b/gcc/testsuite/c-c++-common/pr103798-2.c
@@ -28,4 +28,4 @@ main ()
}
/* See PR c++/113706 for the xfail. */
-/* { dg-final { scan-assembler-not "memchr" { xfail { c++ && *-*-solaris2* } }
} } */
+/* { dg-final { scan-assembler-not "memchr" { xfail { c++ && { *-*-solaris2*
*-*-vxworks* } } } } } */
[gcc r14-10022] [testsuite] [analyzer] include sys/select.h if available
https://gcc.gnu.org/g:e965162bb9de6d2cd68cdc0e26dda56abd25fcdf commit r14-10022-ge965162bb9de6d2cd68cdc0e26dda56abd25fcdf Author: Alexandre Oliva Date: Thu Apr 18 08:01:21 2024 -0300 [testsuite] [analyzer] include sys/select.h if available Test that calls select fails on vxworks because select is only declared in sys/select.h. Include that header if it's present. for gcc/testsuite/ChangeLog * gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c: Include sys/select.h if present. Diff: --- gcc/testsuite/gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c b/gcc/testsuite/gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c index fcbcc740170..f922a52238f 100644 --- a/gcc/testsuite/gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c +++ b/gcc/testsuite/gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c @@ -8,6 +8,9 @@ #include #include #include +#if __has_include() +#include +#endif #include #include #include
[gcc r14-10021] [testsuite] [analyzer] require fork where used
https://gcc.gnu.org/g:8a1170903212ed31fd970d3c1b9fabf50868d01a
commit r14-10021-g8a1170903212ed31fd970d3c1b9fabf50868d01a
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:15 2024 -0300
[testsuite] [analyzer] require fork where used
Mark tests that fail due to the lack of fork, as in vxworks kernel
mode, as requiring fork.
for gcc/testsuite/ChangeLog
* gcc.dg/analyzer/pipe-glibc.c: Require fork.
* gcc.dg/analyzer/pipe-manpages.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/analyzer/pipe-glibc.c| 5 +++--
gcc/testsuite/gcc.dg/analyzer/pipe-manpages.c | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/analyzer/pipe-glibc.c
b/gcc/testsuite/gcc.dg/analyzer/pipe-glibc.c
index 60558a870b9..fe38ddef395 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pipe-glibc.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pipe-glibc.c
@@ -1,6 +1,7 @@
-/* Example of pipe usage from glibc manual. */
-
/* { dg-skip-if "" { "avr-*-*" } } */
+/* { dg-require-fork "" } */
+
+/* Example of pipe usage from glibc manual. */
#include
#include
diff --git a/gcc/testsuite/gcc.dg/analyzer/pipe-manpages.c
b/gcc/testsuite/gcc.dg/analyzer/pipe-manpages.c
index 6b9ae4d2602..ac5805fdba0 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pipe-manpages.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pipe-manpages.c
@@ -1,3 +1,5 @@
+/* { dg-require-fork "" } */
+
/* Example of "pipe" from release 5.13 of the Linux man-pages project.
Copyright (C) 2005, 2008, Michael Kerrisk
[gcc r14-10020] [testsuite] [analyzer] skip access-mode: O_ACCMODE on vxworks
https://gcc.gnu.org/g:5be4f203c491b654ae2b2d5a01b58613f74aba1d
commit r14-10020-g5be4f203c491b654ae2b2d5a01b58613f74aba1d
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:11 2024 -0300
[testsuite] [analyzer] skip access-mode: O_ACCMODE on vxworks
O_ACCMODE is not defined on vxworks, and the test is meaningless and
failing without it, so skip it.
for gcc/testsuite/ChangeLog
* gcc.dg/analyzer/fd-access-mode-target-headers.c: Skip on
vxworks as well.
Diff:
---
gcc/testsuite/gcc.dg/analyzer/fd-access-mode-target-headers.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-access-mode-target-headers.c
b/gcc/testsuite/gcc.dg/analyzer/fd-access-mode-target-headers.c
index b57b9fa2279..9fc32638a3d 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-access-mode-target-headers.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-access-mode-target-headers.c
@@ -1,5 +1,4 @@
-/* { dg-skip-if "" { powerpc*-*-aix* || newlib } } */
-/* { dg-skip-if "" { avr-*-* } } */
+/* { dg-skip-if "" { { powerpc*-*-aix* avr-*-* *-*-vxworks* } || newlib } } */
#include
#include
[gcc r14-10019] [testsuite] [analyzer] avoid vxworks libc mode_t
https://gcc.gnu.org/g:76a1bcc05f152da17770e94eaaf7aa491af2ff01
commit r14-10019-g76a1bcc05f152da17770e94eaaf7aa491af2ff01
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:07 2024 -0300
[testsuite] [analyzer] avoid vxworks libc mode_t
Define macro that prevents mode_t from being defined by vxworks'
headers as well.
for gcc/testsuite/ChangeLog
* gcc.dg/analyzer/fd-4.c: Define macro to avoid mode_t on
vxworks.
Diff:
---
gcc/testsuite/gcc.dg/analyzer/fd-4.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 880de3d7896..d104bfdad54 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -1,4 +1,5 @@
/* { dg-additional-options "-D_MODE_T_DECLARED=1" { target newlib } } */
+/* { dg-additional-options "-D_DEFINED_mode_t" { target *-*-vxworks* } } */
#if defined(_AIX) || defined(__hpux)
#define _MODE_T
#endif
[gcc r14-10018] [testsuite] introduce strndup effective target
https://gcc.gnu.org/g:5dfbc05c4a8da4a177056c57e13e5050c637056e
commit r14-10018-g5dfbc05c4a8da4a177056c57e13e5050c637056e
Author: Alexandre Oliva
Date: Thu Apr 18 08:01:04 2024 -0300
[testsuite] introduce strndup effective target
A number of tests that call strndup fail on vxworks, where there's no
strndup. Some of them already had workarounds to skip the strndup
parts of the tests on platforms that don't offer it. I've changed
them to rely on a strndup effective target instead, and extended the
logic to other tests that were otherwise skipped entirely.
for gcc/ChangeLog
* doc/sourcebuild.texi (strndup): Add effective target.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_strndup): New.
* gcc.dg/builtin-dynamic-object-size-0.c: Skip strndup tests
when the function is not available.
* gcc.dg/builtin-dynamic-object-size-1.c: Likewise.
* gcc.dg/builtin-dynamic-object-size-2.c: Likewise.
* gcc.dg/builtin-dynamic-object-size-3.c: Likewise.
* gcc.dg/builtin-dynamic-object-size-4.c: Likewise.
* gcc.dg/builtin-object-size-1.c: Likewise.
* gcc.dg/builtin-object-size-2.c: Likewise.
* gcc.dg/builtin-object-size-3.c: Likewise.
* gcc.dg/builtin-object-size-4.c: Likewise.
Diff:
---
gcc/doc/sourcebuild.texi | 3 +++
gcc/testsuite/gcc.dg/builtin-dynamic-object-size-0.c | 10 +-
gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c | 2 +-
gcc/testsuite/gcc.dg/builtin-dynamic-object-size-2.c | 2 +-
gcc/testsuite/gcc.dg/builtin-dynamic-object-size-3.c | 2 +-
gcc/testsuite/gcc.dg/builtin-dynamic-object-size-4.c | 2 +-
gcc/testsuite/gcc.dg/builtin-object-size-1.c | 7 ---
gcc/testsuite/gcc.dg/builtin-object-size-2.c | 7 ---
gcc/testsuite/gcc.dg/builtin-object-size-3.c | 7 ---
gcc/testsuite/gcc.dg/builtin-object-size-4.c | 7 ---
gcc/testsuite/lib/target-supports.exp| 11 +++
11 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 7c0df90e822..8e4e59ac44c 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2837,6 +2837,9 @@ can be included without error when @option{-mbig-endian}
is passed.
@item stpcpy
Target provides @code{stpcpy} function.
+@item strndup
+Target provides @code{strndup} function.
+
@item sysconf
Target supports @code{sysconf}.
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-0.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-0.c
index 173e7c755f4..d02e37f79d9 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-0.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-0.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-require-effective-target size20plus } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#include "builtin-object-size-common.h"
@@ -567,6 +567,7 @@ test_strdup (const char *in)
return sz;
}
+#ifndef SKIP_STRNDUP
size_t
__attribute__ ((noinline))
test_strndup (const char *in, size_t bound)
@@ -577,6 +578,7 @@ test_strndup (const char *in, size_t bound)
__builtin_free (res);
return sz;
}
+#endif
size_t
__attribute__ ((noinline))
@@ -589,6 +591,7 @@ test_strdup_min (const char *in)
return sz;
}
+#ifndef SKIP_STRNDUP
size_t
__attribute__ ((noinline))
test_strndup_min (const char *in, size_t bound)
@@ -599,6 +602,7 @@ test_strndup_min (const char *in, size_t bound)
__builtin_free (res);
return sz;
}
+#endif
/* Other tests. */
@@ -788,12 +792,16 @@ main (int argc, char **argv)
const char *str = "hello world";
if (test_strdup (str) != __builtin_strlen (str) + 1)
FAIL ();
+#ifndef SKIP_STRNDUP
if (test_strndup (str, 4) != 5)
FAIL ();
+#endif
if (test_strdup_min (str) != __builtin_strlen (str) + 1)
FAIL ();
+#ifndef SKIP_STRNDUP
if (test_strndup_min (str, 4) != 1)
FAIL ();
+#endif
DONE ();
}
diff --git a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
index ffa59985024..76b4f704fed 100644
--- a/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
+++ b/gcc/testsuite/gcc.dg/builtin-dynamic-object-size-1.c
@@ -1,7 +1,7 @@
/* { dg-do run } */
/* { dg-options "-O2 -Wno-stringop-overread" } */
/* { dg-require-effective-target alloca } */
-/* { dg-skip-if "no strndup" { hppa*-*-hpux* } } */
+/* { dg-additional-options "-DSKIP_STRNDUP" { target { ! strndup } } } */
#define __builtin_object_size __builtin_dynamic_object_size
#include "builtin-object-size-1.c"
diff --git a/gc
[gcc r14-10017] [libstdc++] [testsuite] disable SRA for compare_exchange_padding
https://gcc.gnu.org/g:dcf0bd14cda706be8d0c18963812beefca51df39
commit r14-10017-gdcf0bd14cda706be8d0c18963812beefca51df39
Author: Alexandre Oliva
Date: Thu Apr 18 08:00:59 2024 -0300
[libstdc++] [testsuite] disable SRA for compare_exchange_padding
On arm-vx7r2, the uses of as.load() as initializer get SRAed, so the
padding bits in the tests are not what we might expect from full-word
struct copies.
I tried adding a function to perform bitwise copying, but even taking
the as.load() argument by const&, we'd still construct a temporary
with SRAed field-wise copying. Unable to find another way to ensure
we wouldn't get a temporary, I went for disabling SRA.
for libstdc++-v3/ChangeLog
* testsuite/29_atomics/atomic/compare_exchange_padding.cc:
Disable SRA.
Diff:
---
libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
index 2f18d426e7f..a6081968ca8 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
@@ -1,6 +1,7 @@
// { dg-do run { target c++20 } }
// { dg-require-atomic-cmpxchg-word "" }
// { dg-add-options libatomic }
+// { dg-additional-options "-fno-tree-sra" }
#include
#include
@@ -26,10 +27,10 @@ main ()
s.s = 42;
std::atomic as{ s };
- auto ts = as.load();
+ auto ts = as.load(); // SRA might prevent copying of padding bits here.
VERIFY( !compare_struct(s, ts) ); // padding cleared on construction
as.exchange(s);
- auto es = as.load();
+ auto es = as.load(); // SRA might prevent copying of padding bits here.
VERIFY( compare_struct(ts, es) ); // padding cleared on exchange
S n;
[gcc r14-10016] [libstdc++] [testsuite] xfail double-prec from_chars for float128_t
https://gcc.gnu.org/g:5b178179e85ace01a97def40531e915c180aaeca
commit r14-10016-g5b178179e85ace01a97def40531e915c180aaeca
Author: Alexandre Oliva
Date: Thu Apr 18 08:00:56 2024 -0300
[libstdc++] [testsuite] xfail double-prec from_chars for float128_t
Tests 20_util/from_chars/4.cc and 20_util/to_chars/long_double.cc were
adjusted about a year ago to skip long double on some targets, because
the fastfloat library was limited to 64-bit doubles.
The same problem comes up in similar float128_t tests on
aarch64-vxworks. This patch adjusts them similarly.
Unlike the earlier tests, that got similar treatment for
x86_64-vxworks, these haven't failed there.
for libstdc++-v3/ChangeLog
* testsuite/20_util/from_chars/8.cc: Skip float128_t testing
on aarch64-vxworks.
* testsuite/20_util/to_chars/float128_c++23.cc: Xfail run on
aarch64-vxworks.
Diff:
---
libstdc++-v3/testsuite/20_util/from_chars/8.cc| 3 ++-
libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/testsuite/20_util/from_chars/8.cc
b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
index ee60d88c332..a6343422c5a 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/8.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
@@ -17,6 +17,7 @@
// { dg-do run { target c++23 } }
// { dg-add-options ieee }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* } }
#include
#include
@@ -343,7 +344,7 @@ test06()
#if defined(__STDCPP_FLOAT64_T__) && defined(_GLIBCXX_DOUBLE_IS_IEEE_BINARY64)
test_max_mantissa();
#endif
-#if defined(__GLIBCXX_TYPE_INT_N_0) \
+#if defined(__GLIBCXX_TYPE_INT_N_0) && !defined SKIP_LONG_DOUBLE \
&& defined(__STDCPP_FLOAT128_T__) &&
defined(_GLIBCXX_LDOUBLE_IS_IEEE_BINARY128)
test_max_mantissa();
#endif
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
index 547632817b4..ca00761ee7c 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
@@ -19,6 +19,7 @@
// { dg-require-effective-target ieee_floats }
// { dg-require-effective-target size32plus }
// { dg-add-options ieee }
+// { dg-xfail-run-if "from_chars limited to double-precision" {
aarch64-*-vxworks* } }
#include
#include
[gcc r14-10015] [libstdc++] define zoneinfo_dir_override on vxworks
https://gcc.gnu.org/g:da3504ae4d1e6872585b1107a4932efd3824e943
commit r14-10015-gda3504ae4d1e6872585b1107a4932efd3824e943
Author: Alexandre Oliva
Date: Thu Apr 18 08:00:52 2024 -0300
[libstdc++] define zoneinfo_dir_override on vxworks
VxWorks fails to load kernel-mode modules with weak undefined symbols.
In RTP mode modules, that undergo final linking, weak undefined
symbols are not a problem.
This patch adds kernel-mode VxWorks multilibs to the set of targets
that don't support weak undefined symbols without special flags, in
which tzdb's zoneinfo_dir_override is given a weak definition.
for libstdc++-v3/ChangeLog
* src/c++20/tzdb.cc (__gnu_cxx::zoneinfo_dir_override): Define
on VxWorks non-RTP.
Diff:
---
libstdc++-v3/src/c++20/tzdb.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/libstdc++-v3/src/c++20/tzdb.cc b/libstdc++-v3/src/c++20/tzdb.cc
index 890a4c53e2d..639d1c440ba 100644
--- a/libstdc++-v3/src/c++20/tzdb.cc
+++ b/libstdc++-v3/src/c++20/tzdb.cc
@@ -70,8 +70,9 @@ namespace __gnu_cxx
#else
[[gnu::weak]] const char* zoneinfo_dir_override();
-#if defined(__APPLE__) || defined(__hpux__)
- // Need a weak definition for Mach-O.
+#if defined(__APPLE__) || defined(__hpux__) \
+ || (defined(__VXWORKS__) && !defined(__RTP__))
+ // Need a weak definition for Mach-O et al.
[[gnu::weak]] const char* zoneinfo_dir_override()
{
#ifdef _GLIBCXX_ZONEINFO_DIR
Re: [PATCH] [libstdc++] [testsuite] xfail double-prec from_chars for float128_t
On Apr 16, 2024, Alexandre Oliva wrote: > * testsuite/20_util/to_chars/float128-c++23.cc: Xfail run on > aarch64-vxworks. FTR, here's the fixed ChangeLog entry I'm putting in: (s/-/_/) * testsuite/20_util/to_chars/float128_c++23.cc: Xfail run on aarch64-vxworks. -- Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/ Free Software Activist GNU Toolchain Engineer More tolerance and less prejudice are key for inclusion and diversity Excluding neuro-others for not behaving ""normal"" is *not* inclusive
Re: [PATCH] [testsuite] [arm] accept empty init for bfloat16
On Apr 16, 2024, Mike Stump wrote: > Indeed, I kinda expect coverage already for that feature in > another test case. *nod*, jsm added gcc.dg/c11-empty-init-[123].c (and more) in the patch that implemented this c23 feature. -- Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/ Free Software Activist GNU Toolchain Engineer More tolerance and less prejudice are key for inclusion and diversity Excluding neuro-others for not behaving ""normal"" is *not* inclusive
Re: [PATCH] [strub] improve handling of indirected volatile parms [PR112938]
On Apr 16, 2024, Alexandre Oliva wrote: > I'm going to put it in momentarily. It had been approved for gcc 14, > before it branched off; should I install it there as well? Ermh, nevermind, I'm not sure how I got the idea that we'd already branched, but I was absolutely sure that this was the case. Doh! :-) -- Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/ Free Software Activist GNU Toolchain Engineer More tolerance and less prejudice are key for inclusion and diversity Excluding neuro-others for not behaving ""normal"" is *not* inclusive
[gcc r14-9985] [strub] improve handling of indirected volatile parms [PR112938]
https://gcc.gnu.org/g:c39dc5bb65c492fafc5a0fde83708b8d24e0338d
commit r14-9985-gc39dc5bb65c492fafc5a0fde83708b8d24e0338d
Author: Alexandre Oliva
Date: Tue Apr 16 01:24:59 2024 -0300
[strub] improve handling of indirected volatile parms [PR112938]
The earlier patch for PR112938 arranged for volatile parms to be made
indirect in internal strub wrapped bodies.
The first problem that remained, more evident, was that the indirected
parameter remained volatile, despite the indirection, but it wasn't
regimplified, so indirecting it was malformed gimple.
Regimplifying turned out not to be needed. The best course of action
was to drop the volatility from the by-reference parm, that was being
unexpectedly inherited from the original volatile parm.
That exposed another problem: the dereferences would then lose their
volatile status, so we had to bring volatile back to them.
for gcc/ChangeLog
PR middle-end/112938
* ipa-strub.cc (pass_ipa_strub::execute): Drop volatility from
indirected parm.
(maybe_make_indirect): Restore volatility in dereferences.
for gcc/testsuite/ChangeLog
PR middle-end/112938
* g++.dg/strub-internal-pr112938.cc: New.
Diff:
---
gcc/ipa-strub.cc| 7 +++
gcc/testsuite/g++.dg/strub-internal-pr112938.cc | 12
2 files changed, 19 insertions(+)
diff --git a/gcc/ipa-strub.cc b/gcc/ipa-strub.cc
index dff94222351..8fa7bdf5300 100644
--- a/gcc/ipa-strub.cc
+++ b/gcc/ipa-strub.cc
@@ -1940,6 +1940,9 @@ maybe_make_indirect (indirect_parms_t _parms,
tree op, int *rec)
TREE_TYPE (TREE_TYPE (op)),
op,
build_int_cst (TREE_TYPE (op), 0));
+ if (TYPE_VOLATILE (TREE_TYPE (TREE_TYPE (op)))
+ && !TREE_THIS_VOLATILE (ret))
+ TREE_SIDE_EFFECTS (ret) = TREE_THIS_VOLATILE (ret) = 1;
return ret;
}
}
@@ -2894,6 +2897,10 @@ pass_ipa_strub::execute (function *)
probably drop the TREE_ADDRESSABLE and keep the TRUE. */
tree ref_type = build_ref_type_for (nparm);
+ if (TREE_THIS_VOLATILE (nparm)
+ && TYPE_VOLATILE (TREE_TYPE (nparm))
+ && !TYPE_VOLATILE (ref_type))
+ TREE_SIDE_EFFECTS (nparm) = TREE_THIS_VOLATILE (nparm) = 0;
DECL_ARG_TYPE (nparm) = TREE_TYPE (nparm) = ref_type;
relayout_decl (nparm);
TREE_ADDRESSABLE (nparm) = 0;
diff --git a/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
b/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
new file mode 100644
index 000..5a74becc269
--- /dev/null
+++ b/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-tree-optimized -O2" } */
+/* { dg-require-effective-target strub } */
+
+bool __attribute__ ((__strub__ ("internal")))
+f(bool i, volatile bool j)
+{
+ return (i ^ j) == j;
+}
+
+/* Check for two dereferences of the indirected volatile j parm. */
+/* { dg-final { scan-tree-dump-times {={v} \*j_[0-9][0-9]*(D)} 2 "optimized" }
} */
