On 6/18/24 03:38, Surya Kumari Jangala wrote:
Hi Vladimir,
On 14/06/24 10:56 pm, Vladimir Makarov wrote:
On 6/13/24 00:34, Surya Kumari Jangala wrote:
Hi Vladimir,
With my patch for PR111673 (scale the spill/restore cost of callee-save
register with the frequency of the entry bb in the
On 6/13/24 00:34, Surya Kumari Jangala wrote:
Hi Vladimir,
With my patch for PR111673 (scale the spill/restore cost of callee-save
register with the frequency of the entry bb in the routine assign_hard_reg() :
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631849.html), the
following Li
On 9/7/23 07:21, senthilkumar.selva...@microchip.com wrote:
Hi,
One more execution failure for the avr target, this time from
gcc.c-torture/execute/bitfld-3.c.
Steps to reproduce
Enable LRA in avr.cc by removing TARGET_LRA_P hook, build with
$ make all-host && make install-host
On 8/10/23 07:33, senthilkumar.selva...@microchip.com wrote:
Hi Vlad,
I can confirm your commit
(https://gcc.gnu.org/git?p=gcc.git;a=commit;h=2971ff7b1d564ac04b537d907c70e6093af70832)
fixes the above problem, thank you. However, I see execution failures if a
pseudo assigned to FP ha
On 8/9/23 16:54, Vladimir Makarov wrote:
On 8/9/23 07:15, senthilkumar.selva...@microchip.com wrote:
Hi,
After turning on FP -> SP elimination after Vlad fixed
an elimination issue in
https://gcc.gnu.org/git?p=gcc.git;a=commit;h=2971ff7b1d564ac04b537d907c70e6093af70832,
I&#x
On 8/9/23 16:54, Vladimir Makarov wrote:
On 8/9/23 07:15, senthilkumar.selva...@microchip.com wrote:
Hi,
After turning on FP -> SP elimination after Vlad fixed
an elimination issue in
https://gcc.gnu.org/git?p=gcc.git;a=commit;h=2971ff7b1d564ac04b537d907c70e6093af70832,
I&#x
On 8/9/23 07:15, senthilkumar.selva...@microchip.com wrote:
Hi,
After turning on FP -> SP elimination after Vlad fixed
an elimination issue in
https://gcc.gnu.org/git?p=gcc.git;a=commit;h=2971ff7b1d564ac04b537d907c70e6093af70832,
I'm now running into reload failure if arithmetic is d
On 7/17/23 07:33, senthilkumar.selva...@microchip.com wrote:
Hi,
The avr target has a bunch of patterns that directly set hard regs at expand
time, like so
(define_expand "cpymemhi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(match_operand:BLK 1 "mem
On 7/20/23 07:17, senthilkumar.selva...@microchip.com wrote:
Hi,
The avr backend has this define_insn_and_split
(define_insn_and_split "*tablejump_split"
[(set (pc)
(unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
UNSPEC_INDEX_JMP))
(use (l
On 7/17/23 03:17, senthilkumar.selva...@microchip.com wrote:
On Fri, 2023-07-14 at 09:29 -0400, Vladimir Makarov wrote:
If you send me the preprocessed test, I could start to work on it to fix
the problems. I think it is hard to fix them right for a person having
a little experience with LRA
On 7/13/23 05:27, SenthilKumar.Selvaraj--- via Gcc wrote:
Hi,
I've been spending some (spare) time checking what it would take to
make LRA work for the avr target.
Right after I removed the TARGET_LRA_P hook disabling LRA, building
libgcc failed with a weird ICE.
On the avr,
On 4/19/23 14:53, Surya Kumari Jangala wrote:
...
I have a few queries:
1. A zero cost seems strange for the regs r14-r31. If using a reg in the
set [14..31] has zero cost, then why wasn’t such a reg chosen for r118
in the first place, instead of r3?
I guess it is because assign_hard_reg (s
On 2022-12-09 14:23, Georg-Johann Lay wrote:
There is the following code size regression, filed as
https://gcc.gnu.org/PR90706
I am sorry, I feel your frustration. I was not aware of this PR.
Unfortunately, the PR was marked as P4 and I have too many open PRs and
should prioritize them.
===
--- ChangeLog (revision 279595)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2019-12-19 Vladimir Makarov
+
+ PR target/92905
+ * lra-constraints.c (process_alt_operands): Check offmemok when
+ processing preferred_reload_class.
+
2019-12-19 Andrew Stubbs
* config/gcn/gcn-valu.md
Index: lra
On 2019-08-19 3:35 a.m., John Darrington wrote:
On Fri, Aug 16, 2019 at 10:50:13AM -0400, Vladimir Makarov wrote:
No I meant something like that
(define_special_memory_constraint "a" ...)
(define_predicate "my_sp
On 2019-08-16 7:23 a.m., John Darrington wrote:
On Thu, Aug 15, 2019 at 02:23:45PM -0400, Vladimir Makarov wrote:
> I tried this solution earlier. But unfortunately it makes things
worse. What happens is it libgcc cannot
> even be built -- ICEs occur on a memory from a
On 8/15/19 12:38 PM, Richard Biener wrote:
On August 15, 2019 6:29:13 PM GMT+02:00, Vladimir Makarov
wrote:
On 8/10/19 2:05 AM, John Darrington wrote:
On Fri, Aug 09, 2019 at 01:34:36PM -0400, Vladimir Makarov wrote:
If you provide LRA dump for such test (it is better to use
On 8/15/19 1:35 PM, John Darrington wrote:
On Thu, Aug 15, 2019 at 12:29:13PM -0400, Vladimir Makarov wrote:
Thank you for providing the sources.?? It helped me to understand what is
going on.?? So the test crashes on
/home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture
On 8/10/19 2:05 AM, John Darrington wrote:
On Fri, Aug 09, 2019 at 01:34:36PM -0400, Vladimir Makarov wrote:
If you provide LRA dump for such test (it is better to use
-fira-verbose=15 to output full RA info into stderr), I probably could
say more.
I've attached s
On 2019-08-10 2:05 a.m., John Darrington wrote:
On Fri, Aug 09, 2019 at 01:34:36PM -0400, Vladimir Makarov wrote:
If you provide LRA dump for such test (it is better to use
-fira-verbose=15 to output full RA info into stderr), I probably could
say more.
I've att
On 2019-08-09 4:14 a.m., John Darrington wrote:
On Thu, Aug 08, 2019 at 01:57:41PM -0600, Jeff Law wrote:
Yea, it's certainly designed with the more mainstream architectures in
mind. THe double-indirect case that's being talked about here is well
out of the mainstream and no
On 2019-08-08 12:43 p.m., Paul Koning wrote:
On Aug 8, 2019, at 12:25 PM, Vladimir Makarov wrote:
On 2019-08-04 3:18 p.m., John Darrington wrote:
I'm trying to write a back-end for an architecture (s12z - the ISA you can
download from [1]). This arch accepts indirect memory addr
On 2019-08-04 3:18 p.m., John Darrington wrote:
I'm trying to write a back-end for an architecture (s12z - the ISA you can
download from [1]). This arch accepts indirect memory addresses. That is to
say, those of the form (mem (mem (...))) and although my
TARGET_LEGITIMATE_ADDRESS
function
On 11/01/2018 08:25 PM, Paul Koning wrote:
I'm running the testsuite on the pdp11 target, and I get a failure when using
LRA that works correctly with the old allocator. The issue is that LRA is
producing an insn that is invalid (it violates the constraints stated in the
insn definition).
Th
On 10/05/2018 01:19 PM, Jeff Law wrote:
On 10/5/18 7:04 AM, Andrew Stubbs wrote:
I just tracked down a "reload" bug and was very surprised to find that
can_create_pseudo_p doesn't return false during register allocation when
using LRA.
It's still defined like this:
#define can_create_pseudo_p(
On 03/28/2018 05:31 PM, Sirish Pande wrote:
Hi,
I am interested to know if there is any option that would tell me how many
registers have spilled. I noticed that there is spilled_regs array in
reload1.c - but I can't seem to find where it dumps that information.
Potentially I could build compi
On 03/02/2018 02:45 PM, Peter Bergner wrote:
While debugging the PR84264 ICE caused by the following test case:
void _setjmp ();
void a (unsigned long *);
void
b ()
{
for (;;)
{
_setjmp ();
unsigned long args[9]{};
a (args);
}
}
I n
On 12/18/2017 07:07 PM, Michael Clark wrote:
Hi Leslie,
I suggest adding these 3 papers to your reading list.
Register allocation for programs in SSA-form
Sebastian Hack, Daniel Grund, and Gerhard Goos
http://www.rw.cdl.uni-saarland.de/~grund/papers/cc06-ra_ssa.pdf
On 12/14/2017 10:18 PM, Leslie Zhai wrote:
Hi GCC and LLVM developers,
I am learning Register Allocation algorithms and I am clear that:
* Unlimited VirtReg (pseudo) -> limited or fixed or alias[1] PhysReg
(hard)
* Memory (20 - 100 cycles) is expensive than Register (1 cycle), but
it has
On 10/23/2017 07:44 PM, Kugan Vivekanandarajah wrote:
Hi All,
I am wondering if there is anyway we can prefer certain registers in
register allocations. That is, I want to have some way of recording
register allocation decisions (for loads in loop that are accessed in
steps) and use this to infl
On 10/11/2017 10:43 PM, Martin Sebor wrote:
Hi Vladimir,
On a hunch I backed out r253656. That let the Ada and Go bootstrap
complete. It looks like your fix for bug 82353 is triggering this
ICE.
Martin, thank you for informing me. I used the default bootstrap.
I've reverted LRA changes be
On 02/01/2017 06:52 PM, Matthew Fortune wrote:
Hi all,
I've copied you as you have each made some significant change to a function
in LRA which I guess makes you de-facto experts.
I've spent a while researching the history of simplify_operand_subreg and
in particular the behaviour for subregs
On 01/16/2017 10:47 AM, Matthew Fortune wrote:
Hi Vladimir,
I'm working on PR target/78660 which is looking like a latent LRA bug.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660
I believe the problem is in the same area as a bug was fixed in 2015:
https://gcc.gnu.org/ml/gcc-patches/2015
On 08/02/2016 04:41 PM, shmeel gutl wrote:
I am trying to enable lra for a propriety backend. I ran into one
problem that I can't solve. In lra-constraints.c:split_reg
lra_create_new_reg can be called with a hard code rclass of NO_REGS.
It then queues a move instruction of the type
set TYPE:
On 05/11/2016 01:39 AM, Alexander Monakov wrote:
On Wed, 30 Mar 2016, Bernd Schmidt wrote:
On 03/25/2016 04:43 AM, Aldy Hernandez wrote:
If Bernd is fine with this, I'm happy to retract my patch and any
possible followups. I'm just interested in having no path causing a
possible out of bounds
On 03/23/2016 02:32 AM, Aldy Hernandez wrote:
Howdy!
I'm working on enhancements to our out-of-bounds warnings in VRP, such
that we can warn and isolate conditionally out-of-bound accesses
(similar to what we do in gimple-ssa-isolate-paths.c for NULL accesses).
With my WIP I have found the f
On 10/22/2015 06:05 AM, Dominik Vogt wrote:
On Tue, Oct 13, 2015 at 05:03:36PM -0400, Vladimir Makarov wrote:
[snip]
I checked my article
ftp://ftp.uvsq.fr/pub/gcc/summit/2004/Fighting%20Register%20Pressure.pdf
and GVN gave mostly 0.2% on eon only. The current environment is
quite different
On 10/13/2015 01:06 PM, Jeff Law wrote:
On 10/13/2015 07:12 AM, Dominik Vogt wrote:
In some cases, the work of the cse1 pass is counterproductive, as
we noticed on s390x. The effect described below is present since
at least 4.8.0. Note that this may not become manifest in a
performance issue p
On 10/11/2015 04:18 PM, Mikhail Maltsev wrote:
Hi!
SUSE performs periodic testing of GCC and publishes the results on their site:
http://gcc.opensuse.org/ (many thanks for this great job!).
I hope
https://vmakarov.fedorapeople.org/spec/
could be useful for your purposes too.
I've changed in
On 09/08/2015 02:51 PM, Jeff Law wrote:
On 09/08/2015 12:39 PM, Aditya K wrote:
IIUC, in the haifa-sched.c, the default scheduling algorithm seems to
be top-down (before reload). Is there a way to schedule the other way
(bottom up), or both ways?
Not that I'm aware of. Note that region scheduli
On 09/04/2015 09:02 PM, David Miller wrote:
From: David Miller
Date: Fri, 04 Sep 2015 11:27:31 -0700 (PDT)
From: Vladimir Makarov
Date: Fri, 4 Sep 2015 10:00:54 -0400
I don't think we should add a new LRA code calling process_address
before adding insns for further processing. LRA
On 09/03/2015 06:33 PM, David Miller wrote:
I'm working on converting sparc to LRA, and thanks probably to the
work the powerpc folks did this is going much better than when I
last tried this.
Thanks for working on this, David.
The first major stumbling block I've run into is when LRA forces
a
On 08/24/2015 02:43 PM, shmeel gutl wrote:
are there any guidelines as to what needs to be done in the backend to
enable lra for 5.2?
Unfortunately, switching from reload to LRA can be a difficult task.
Reload pass is driven by many machine target hooks. As LRA uses
different algorithms these
On 07/10/2015 04:09 AM, Richard Biener wrote:
On Thu, 9 Jul 2015, Uros Bizjak wrote:
Hello!
The patch was bootstrapped and tested on x86/x86-64.
Committed as rev. 225618.
2015-07-09 Vladimir Makarov
PR rtl-optimization/66782
* lra-int.h (struct lra_insn_recog_data
On 2015-07-05 7:11 AM, Ajit Kumar Agarwal wrote:
All:
I am wondering allocation of hot data structure closer to the top of the stack
increases the performance of the application.
The data structure are identified as hot and cold data structure and all the
data structures are sorted in decrea
On 07/02/2015 07:06 AM, Ajit Kumar Agarwal wrote:
Sorry for the typo error. I meant exits instead of exists.
The below is corrected.
The Cost Calculation for a candidate to Spill in the Integrated Register
Allocator(IRA) considers only the SESE regions.
The Cost Calculation in the IRA should
On 07/01/2015 01:43 PM, Jakub Jelinek wrote:
On Wed, Jul 01, 2015 at 01:35:16PM -0400, Vladimir Makarov wrote:
Actually it raise a question for me. If we describe that a function
clobbers more than calling convention and then use it as a value (assigning
a variable or passing as an argument
On 07/01/2015 11:27 AM, Andy Lutomirski wrote:
On Wed, Jul 1, 2015 at 8:23 AM, Vladimir Makarov wrote:
On 06/30/2015 05:37 PM, Jakub Jelinek wrote:
On Tue, Jun 30, 2015 at 02:22:33PM -0700, Andy Lutomirski wrote:
I'm working on a massive set of cleanups to Linux's syscall ha
On 07/01/2015 11:31 AM, Jakub Jelinek wrote:
On Wed, Jul 01, 2015 at 11:23:17AM -0400, Vladimir Makarov wrote:
(I'm not necessarily suggesting that we do this for the syscall bodies
themselves. I want to do it for the entry and exit helpers, so we'd
still lose the five cycles i
On 06/30/2015 05:37 PM, Jakub Jelinek wrote:
On Tue, Jun 30, 2015 at 02:22:33PM -0700, Andy Lutomirski wrote:
I'm working on a massive set of cleanups to Linux's syscall handling.
We currently have a nasty optimization in which we don't save rbx,
rbp, r12, r13, r14, and r15 on x86_64 before ca
On 05/21/2015 05:54 AM, Ilya Enkovich wrote:
Thanks. For me it looks like an inheritance bug. It is really hard
>to fix the bug w/o the source code. Could you send me your patch in
>order I can debug RA with it to investigate more.
>
Sure! Here is a patch and a testcase. I applied patch to r
On 20/05/15 04:17 AM, Ilya Enkovich wrote:
On 19 May 11:22, Vladimir Makarov wrote:
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich :
Hi Vladimir,
Could you please comment on this?
Ilya, I think that the idea is worth to try but results might be
On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
2015-05-06 17:18 GMT+03:00 Ilya Enkovich :
2015-04-25 4:32 GMT+03:00 Jan Hubicka :
Hi,
I am adding Vladimir and Richard into CC. I tried to solve similar problem
with FP math years ago by having -mfpmath=sse,i387. The idea was to allow
use of i387 re
On 05/05/2015 12:42 AM, Aditya K wrote:
I was able to successfully bootstrap gcc by using clang as the stage 1
compiler. I configured gcc using the following arguments.
../configure --disable-multilib --enable-bootstrap --enable-languages=c,c++
CC=/work/llvm/install-release/bin/clang
CXX=/wor
On 22/04/15 10:39 AM, Georg-Johann Lay wrote:
Attached is a C test program which produces fine results with
$ avr-gcc -S -O2 -mmcu=atmega8
Also attached is a respective patch against the trunk avr backend that
indicates the transition from clobbers to hard-regs-by-constraint.
I don't actu
On 21/04/15 02:04 AM, Segher Boessenkool wrote:
On Tue, Apr 21, 2015 at 12:27:40AM +0200, Steven Bosscher wrote:
On Mon, Apr 20, 2015 at 10:11 PM, Vladimir Makarov wrote:
I might be wrong but I think you have a bloated code because you use
scratches. I already told several times that usage
On 20/04/15 06:27 PM, Steven Bosscher wrote:
On Mon, Apr 20, 2015 at 10:11 PM, Vladimir Makarov wrote:
I might be wrong but I think you have a bloated code because you use
scratches. I already told several times that usage of scratch is always a
bad idea. It was a bad idea for an old RA and
On 17/04/15 05:58 AM, Georg-Johann Lay wrote:
I allowed me to CC Vladimir; maybe he can propose how the backend can
describe an efficient, constraint-based solution. The problem is
about expanders producing insns with non-fixed hard-regs as in/out
operands or clobbers. This includes move in
On 17/04/15 09:26 AM, Matthew Fortune wrote:
Wilco Dijkstra writes:
While investigating why the IRA preferencing algorithm often chooses
incorrect preferences from the costs, I noticed this thread:
https://gcc.gnu.org/ml/gcc/2011-05/msg00186.html
I am seeing the exact same issue on AArch64 -
On 19/04/15 11:28 AM, Ajit Kumar Agarwal wrote:
Hello All:
To reduce the register pressure, I am proposing the following methods of
reducing the registers.
1. Assigning same registers or sharing same register for the logical registers
having the same value.
To determine the logical register
On 19/04/15 01:11 PM, Jeff Law wrote:
On 04/19/2015 09:28 AM, Ajit Kumar Agarwal wrote:
Hello All:
To reduce the register pressure, I am proposing the following methods
of reducing the registers.
1. Assigning same registers or sharing same register for the logical
registers having the sam
On 2015-03-09 8:10 PM, Ajit Kumar Agarwal wrote:
-Original Message-
From: Jeff Law [mailto:l...@redhat.com]
Sent: Monday, March 09, 2015 11:01 PM
To: Richard Biener
Cc: Ajit Kumar Agarwal; vmaka...@redhat.com; gcc@gcc.gnu.org; Vinod Kathail;
Shail Aditya Gupta; Vidhumouli Hunsigida; N
On 2015-02-05 4:36 PM, sa...@hederstierna.com wrote:
Hi
When reviewing some code from LRA, I just saw some lines that looked a bit
strange,
could it be a possible typo perhaps?
The file "lra.c" from GC5 master branch current date
Line 469:
/* Try x = index_scale; x = x + disp;
On 2015-01-18 12:37 AM, Ajit Kumar Agarwal wrote:
Register allocation with two phase approach does optimal coalescing after the
spilling. Sometime Live range splitting makes
the coalescing non optimal. The splitted Live range are connected by move
instruction. Thus the Live range splitting and
On 2015-01-25 4:55 AM, Ajit Kumar Agarwal wrote:
Hello All:
Looks like Live range splitting and rematerialization are connected to each
other. If the boundary of Live range
Splitting is in the high frequency of the region then the move connected to
splitted live ranges are inside the
High fr
On 2015-01-16 12:30 PM, Andreas Krebbel wrote:
Hi,
on S/390 I see invalid subregs being generated by LRA although
CANNOT_CHANGE_MODE_CLASS is supposed
to prevent these. The reason appears to be the code you've added with:
commit c6a6cdaaea571860c94f9a9fe0f98c597fef7c81
Author: vmakarov
Date
On 2015-01-12 2:25 PM, Jeff Law wrote:
On 01/08/15 04:00, Ajit Kumar Agarwal wrote:
Hello Vladimir:
We have made the changes in the ira-color.c in ira_loop_edge_freq
and move_spill_restore. The main motivation
behind the change is to reduce the memory instruction with respect to
the Loops.
On 2015-01-12 6:33 AM, Ajit Kumar Agarwal wrote:
-Original Message-
From: Richard Biener [mailto:richard.guent...@gmail.com]
Sent: Monday, January 12, 2015 2:33 PM
To: Ajit Kumar Agarwal
Cc: vmaka...@redhat.com; l...@redhat.com; gcc@gcc.gnu.org; Vinod Kathail; Shail
Aditya Gupta; Vidhu
On 2014-12-16 9:53 AM, BELBACHIR Selim wrote:
Hi,
I may have found a bug when I was trying to port my private backend to new LRA
pass (using gcc 4.9.2+patches).
In lra-constraints.c, in function simple_move_p, the target hook
targetm.register_move_cost is called with two badly swapped paramet
On 12/09/2014 04:37 AM, lin zuojian wrote:
> Hi,
> I have read ira/lra code for a while, but still fails to understand
> their relationship. The main question is why ira do color so early?
> lra pass will do the assignment anyway. Sorry if I mess up coloring
> and hard register assi
On 11/24/2014 06:47 AM, Ajit Kumar Agarwal wrote:
> All:
>
> The optimization of reducing save and restore of the callee and caller saved
> register has been the attention Of
> increasing the performance of the benchmark. The callee saved registers is
> saved at the entry and restore at the
> ex
On 2014-11-17 8:13 AM, Ajit Kumar Agarwal wrote:
Hello All:
I was looking at the optimized usage and allocation to argument registers.
There are two aspects to it as follows.
1. We need to specify the argument registers as followed by ABI in the target
specific code. Based on the function
a
On 2014-08-29 2:47 AM, Ilya Enkovich wrote:
Seems your patch doesn't cover all cases. Attached is a modified
patch (with your changes included) and a test where double constant is
wrongly rematerialized. I also see in ira dump that there is still a
copy of PIC reg created:
Initialization of or
On 2014-08-26 5:42 PM, Ilya Enkovich wrote:
Hi,
Here is a patch I tried. I apply it over revision 214215. Unfortunately I do
not have a small reproducer but the problem can be easily reproduced on
SPEC2000 benchmark 175.vpr. The problem is in read_arch.c:701 where float
value is compared w
On 08/26/2014 04:57 AM, Ilya Enkovich wrote:
> 2014-08-26 11:49 GMT+04:00 Ilya Enkovich :
>> 2014-08-25 19:08 GMT+04:00 Vladimir Makarov :
>>> On 2014-08-22 8:21 AM, Ilya Enkovich wrote:
>>>> Hi,
>>>>
>>>> On Cauldron 2014 we had a couple of
On 2014-08-22 8:21 AM, Ilya Enkovich wrote:
Hi,
On Cauldron 2014 we had a couple of talks about relaxation of ebx usage in
32bit PIC mode. It was decided that the best approach would be to not fix ebx
register, use speudo register for GOT base address and let allocator do the
rest. This sho
On 2014-07-01, 3:27 PM, Tom de Vries wrote:
Vladimir,
There are a few patterns which use both the read/write constraint
modifier (+) and the earlyclobber constraint modifier (&):
So my question is: is the combination of '&' and '+' supported ? If so,
what is the exact semantics ? If not, shou
On 2014-06-25, 10:01 AM, Vladimir Makarov wrote:
On 2014-06-24, 10:57 AM, Ramana Radhakrishnan wrote:
I've tried this options too. As I guessed it resulted in GCC
improvement of eon only by 6% which improved overall score by less 0.5%.
No change for LLVM though. Eon is more fp benc
On 2014-06-25, 10:37 AM, Marc Glisse wrote:
On Wed, 25 Jun 2014, Vladimir Makarov wrote:
Maybe. But in this case LLVM did a right thing. The variable
addressing was through a restrict pointer.
Ah, gcc implements (on purpose?) a weak version of restrict, where it
only considers that 2
On 2014-06-25, 10:02 AM, Richard Biener wrote:
On Wed, Jun 25, 2014 at 4:00 PM, Vladimir Makarov wrote:
On 2014-06-25, 5:32 AM, Renato Golin wrote:
On 25 June 2014 10:26, Bingfeng Mei wrote:
Why is GCC code size so much bigger than LLVM? Does -Ofast have more
unrolling
on GCC? It doesn&#
On 2014-06-24, 10:57 AM, Ramana Radhakrishnan wrote:
The ball-park number you have probably won't change much.
I don't think Neon can improve score for SPECInt2000 significantly but
may be I am wrong.
It won't probably improve the overall score by a large amount but some
individual benchmar
On 2014-06-25, 5:32 AM, Renato Golin wrote:
On 25 June 2014 10:26, Bingfeng Mei wrote:
Why is GCC code size so much bigger than LLVM? Does -Ofast have more unrolling
on GCC? It doesn't seem increasing code size help performance (164.gzip &
197.parser)
Is there comparisons for O2? I guess that
On 06/24/2014 10:57 AM, Ramana Radhakrishnan wrote:
>
> The ball-park number you have probably won't change much.
>
>>>
>> Unfortunately, that is the configuration I can use on my system because
>> of lack of libraries for other configurations.
>
> Using --with-fpu={neon / neon-vfpv4} shouldn't cau
On 06/24/2014 10:42 AM, Renato Golin wrote:
> On 24 June 2014 15:11, Vladimir Makarov wrote:
>> A few people asked me about new performance comparison of latest GCC
>> and LLVM. So I've finished it and put it on my site
>>
>> http://vmakarov.fedorapeople.org
On 06/24/2014 10:36 AM, Ramana Radhakrishnan wrote:
>
>
> On 24/06/14 15:11, Vladimir Makarov wrote:
>>A few people asked me about new performance comparison of latest GCC
>> and LLVM. So I've finished it and put it on my site
>>
>> http://vmakar
A few people asked me about new performance comparison of latest GCC
and LLVM. So I've finished it and put it on my site
http://vmakarov.fedorapeople.org/spec/
The comparison is achievable from 2014 link and links under it in
the left frame.
These pages are also achievable as
http://vmak
On 2014-06-16, 2:25 PM, Aaron Sawdey wrote:
On Mon, 2014-06-16 at 14:14 +, Ajit Kumar Agarwal wrote:
Hello All:
I have worked on the Open64 compiler where the Register Pressure Guided Unroll
and Jam gave a good amount of performance improvement for the C and C++ Spec
Benchmark and also F
On 2014-06-16, 10:14 AM, Ajit Kumar Agarwal wrote:
Hello All:
I have worked on the Open64 compiler where the Register Pressure Guided Unroll
and Jam gave a good amount of performance improvement for the C and C++ Spec
Benchmark and also Fortran benchmarks.
The Unroll and Jam increases the re
On 2014-06-06, 10:48 AM, Ajit Kumar Agarwal wrote:
Hello All:
I was looking further the aspect of reducing register pressure based on
Register Allocation and Instruction Scheduling and the
Following observation being made on reducing register pressure based on the
existing papers on reducing r
On 2014-05-23, 3:49 AM, shmeel gutl wrote:
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g
On 05/21/2014 12:25 AM, Ajit Kumar Agarwal wrote:
> Hello All:
>
> Simpson does the Live range shrinking and reduction of register pressure by
> using the computation that are not load and store but the arithmetic
> computation. The computation
> where the operands and registers are live at the e
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
On 20-May-14 06:13 PM, Vladimir Makarov wrote:
On 05/19/2014 02:13 AM, shmeel gutl wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will
On 05/19/2014 02:13 AM, shmeel gutl wrote:
> Are there hooks in gcc to deal with negative latencies? In other
> words, an architecture that permits an instruction to use a result
> from an instruction that will be issued later.
>
Could you explain more on *an example* what are you trying to achiev
On 2014-05-16, 6:23 AM, Kugan wrote:
I would like to know if there is anyway we can use registers from
particular register class just as spill registers (in places where
register allocator would normally spill to stack and nothing more), when
it can be useful.
In AArch64, in some cases, compilin
On 05/15/2014 03:28 AM, Ajit Kumar Agarwal wrote:
>
> On 2014-05-14, 1:33 PM, Ajit Kumar Agarwal wrote:
>
>> Hello All:
>>
>> I am planning to implement the Live range splitting based on the following
>> cases in the Integrated Register Allocator.
>>
>> For a given Live range that spans from from
On 05/15/2014 02:46 AM, Ramana Radhakrishnan wrote:
> On Wed, May 14, 2014 at 5:38 PM, Richard Sandiford
> wrote:
>> Vladimir Makarov writes:
>>> On 2014-05-13, 6:27 AM, Kyrill Tkachov wrote:
>>>> Hi all,
>>>>
>>>> In haifa-sched.c (in r
On 2014-05-14, 1:33 PM, Ajit Kumar Agarwal wrote:
Hello All:
I am planning to implement the Live range splitting based on the following
cases in the Integrated Register Allocator.
For a given Live range that spans from from outer region to inner region of
the loop. Such Live ranges which a
On 2014-05-14, 12:38 PM, Richard Sandiford wrote:
Vladimir Makarov writes:
On 2014-05-13, 6:27 AM, Kyrill Tkachov wrote:
Hi all,
In haifa-sched.c (in rank_for_schedule) I notice that live range
shrinkage is not performed when SCHED_PRESSURE_MODEL is used and the
comment mentions that it
On 2014-05-13, 6:27 AM, Kyrill Tkachov wrote:
Hi all,
In haifa-sched.c (in rank_for_schedule) I notice that live range
shrinkage is not performed when SCHED_PRESSURE_MODEL is used and the
comment mentions that it results in much worse code.
Could anyone elaborate on this? Was it just empiricall
On 03/06/2014 03:14 PM, Paulo J. Matos wrote:
> On 06/03/14 15:15, Vladimir Makarov wrote:
>> On 03/06/2014 08:55 AM, Paulo Matos wrote:
>>> Hi,
>>>
>>> Upon noticing ira-hoist-pressure in `gcc --help=optimizers` and not
>>> ira-loop-pressure,
>>
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