[Bug target/114963] New: RISCV -msave-restore -fno-omit-frame-pointer does not emit save/restore library calls

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- It appears that combining -msave-restore and -fno-omit-frame-pointer results in no save/restore library

[Bug target/113095] RISC-V: movcc no longer used for coremark crc functions with -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095 --- Comment #3 from Craig Topper --- Our FPGA data is showing this as a 5% regression. I'll try to check on an Unmatched board to confirm.

[Bug target/113095] RISC-V: movcc no longer used for coremark crc functions with -mtune=sifive-7-series

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095 --- Comment #2 from Craig Topper --- The branch+mv macrofusion should execute together. The visible latency to other instructions is 1 cycle. The hardware can predicate most ALU instructions, not just mv. So even better would be putting the

[Bug target/113095] New: RISC-V: movcc no longer used for coremark crc functions with -mtune=sifive-7-series

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- In gcc 12, the crc functions in coremark used the "movcc" macrofusion pattern of a branch over a

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #7 from Craig Topper --- Here is my attempt and defining scalar crypto intrinsics https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #3 from Craig Topper --- I don't have a testsuite. I saw that gcc had crypto builtins and I happened to noticed the tests in gcc weren't passing constant arguments. We also have a divergence in names between clang and gcc for some

[Bug target/110201] New: RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- The __builtin_riscv_sm4ks and __builtin_riscv_sm4ed builtins don't enforce that the byte select should

[Bug target/109972] New: RISC-V: Could use umodsi3/udivsi3/divsi3 libcalls for 32-bit division/remainder on RV64 without M extension

: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- There's an opportunity to improve code size for 32-bit division and remainder on RV64

[Bug target/95774] New: __builtin_cpu_is can't detect cooperlake

: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- Cooperlake appears to be defined the enum in libgcc for __builtin_cpu_is, but there is no code to use that enum value when identifying the cpu in libgcc.

[Bug target/95660] New: get_intel_cpu in cpuinfo.c contains unnecessary check for brand_id

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- Brand id or brand index was a feature that briefly existed in some Pentium III and Pentium 4 CPUs. The code will only look

[Bug inline-asm/95121] Wrong code generated: low-byte registers are silently used in place of their corresponding high-byte registers (ah, bh, ch, dh)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95121 Craig Topper changed: What|Removed |Added CC||craig.topper at gmail dot com

[Bug target/94977] New: Some X86 inline assembly modifiers are not documented in the web documentation

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- gcc supports some modifiers for inline assembly on X86 that are not documented in the table at 6.47.2.8 x86 Operand

[Bug target/91704] New: [X86] Codegen for _mm256_cmpgt_epi8 is affected by -funsigned-char

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- This intrinsic should always do a signed compare, but it uses __v32qi in its implementation which uses "char" r

[Bug target/91696] [X86] AVX512 intrinsics that only support SAE should allow (_MM_FOUND_NO_EXC|_MM_FROUND_CUR_DIRECTION) to match icc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91696 --- Comment #1 from Craig Topper --- I've also submitted a patch to clang to do the same. https://reviews.llvm.org/D67289

[Bug target/91696] New: [X86] AVX512 intrinsics that only support SAE should allow (_MM_FOUND_NO_EXC|_MM_FROUND_CUR_DIRECTION) to match icc

: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- The intrinsics that only support SAE like

[Bug libgcc/91695] New: [X86] get_available_features only sets FEATURE_GFNI and FEATURE_VPCLMULQDQ when avx512_usable is true

: UNCONFIRMED Severity: normal Priority: P3 Component: libgcc Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- GFNI has instructions that have legacy SSE-like encodings. It also has VEX and EVEX

[Bug target/86466] New: [X86] gcc checks the range of the immediate to _mm_blend_ps, but not _mm_blend_epi32

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- These intrinsics are both blends of four 32-bit values. gcc seems to check the range for the floating point

[Bug target/86444] New: [X86] Implementation of SSE comi/ucomi intrinsics does not match recent versions of icc, clang, or MSVC

: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- It looks like gcc does not match the behavior of the most recent versions of icc, clang

[Bug target/85530] New: [X86] _mm512_mullox_epi64 and _mm512_mask_mullox_epi64 not implemented

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- icc has these intrinsics which emulate a v8di multiply using multiple pmuludqs when avx512f is enabled, but avx512dq

[Bug target/85511] [X86] Using __builtin_ia32_writeeflags_u32 in 64-bit mode causes internal compiler error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85511 --- Comment #2 from Craig Topper --- Should this builtin even be allowed in 64-bit mode?

[Bug target/85511] New: [X86] Using __builtin_ia32_writeeflags_u32 in 64-bit mode causes internal compiler error

Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- This code void foo(unsigned bar) { return __builtin_ia32_writeeflags_u32(bar); } Throws this error

[Bug target/83618] New: _rdpid_u32 doesn't work on 64-bit targets as gas expects the 64-bit register

: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- Trying to compile the _rdpid_u32 intrinsic on x86-64 causes the assembler to print this /tmp/ccbdTr5q.s: Assembler

[Bug target/83546] New: -march=silvermont doesn't enable rdrnd by default despite what docs say

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- The documentation https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html says 'silvermont' enables rdrnd, but that doesn't appear

[Bug middle-end/80042] gcc thinks sin/cos don't set errno

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80042 --- Comment #3 from Craig Topper --- No -fmath-errno has no effect. It does have effect on other functions such as cosh or acos.

[Bug middle-end/80042] New: gcc thinks sin/cos don't set errno

Assignee: unassigned at gcc dot gnu.org Reporter: craig.topper at gmail dot com Target Milestone: --- Created attachment 40974 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40974=edit Test that uses sin and errno As of glibc version 2.10, sin and cos set errno w

[Bug driver/50740] New: CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not qualified with max_level and doesn't use subleaf

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50740 Bug #: 50740 Summary: CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not qualified with max_level and doesn't use subleaf Classification: Unclassified Product: gcc Version: