-原始邮件-
发件人: "Jeff Law"
发送时间: 2024-03-19 10:54:09 (星期二)
收件人: Jiawei , gcc-patches@gcc.gnu.org
抄送: kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn, shi...@iscas.ac.cn,
shiyul...@iscas.ac.cn, chenyix...@iscas.ac.cn
主题: Re: [P
From: Chen Jiawei
Co-Authored by: Lin Jiawei
This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
gcc/ChangeLog:
* config/riscv/riscv-cores.def
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087
--- Comment #25 from jiawei ---
I had run SPEC2017-v1.1.9 with rv64gcv_zvl256b, it passed the compile and run
on base and validate cases, used qemu 8.1.0.
,
Jiawei
-原始邮件-
发件人: "Jeff Law"
发送时间: 2023-12-12 00:15:44 (星期二)
收件人: Jiawei , gcc-patches@gcc.gnu.org
抄送: kito.ch...@sifive.com, pal...@dabbelt.com, christoph.muell...@vrull.eu
主题: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.
On 11/20/23 12:14, Jiawei wrote:
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles):
New struct.
in the next meeting.
Regards,
Jiawei
Hi all,
We are collecting tomorrow's RISC-V GNU toolchain meeting topics, if you have
any topics want to discuss or share,
please change the angenda/notes doc and let me know.
https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit#
P.S. The meeting
.
Regards,
Jiawei
Hi all,
We are collecting tomorrow's RISC-V GNU toolchain meeting topics, if you have
any topics want to discuss or share,
please change the angenda/notes doc and let me know.
https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit#
P.S. The meeting
Hi all,
We plan to change the meeting schedule from biweekly into monthly，the next
meeting will be held in two weeks,
There are collecting meeting topics, if you have any topics want to discuss or
share, please change the angenda/notes
doc and let me know.
Add ZC* extensions march args tests for error input cases.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/arch-23.c: New test
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
for march args being passed.
Jiawei (3):
RISC-V: Minimal support for ZC* extensions.
RISC-V: Enable compressible features when use ZC* extensions.
RISC-V: Add ZC* test for failed march args being passed.
gcc/common/config/riscv/riscv-common.cc | 38 +++
gcc/config/riscv
Seems there are some indent format problems in the patch, could you fix them :)
```
patch:509: indent with spaces.
x_save_size = riscv_stack_align (num_multi_push * UNITS_PER_WORD);
error: patch failed: gcc/config/riscv/riscv.cc:5652
error: gcc/config/riscv/riscv.cc: patch does not
Sorry for the late, I will send the binutils patch within this week.
- Original Message -
From: "Kito Cheng"
To: "Fei Gao"
Cc: gcc-patches@gcc.gnu.org, pal...@dabbelt.com, jeffreya...@gmail.com,
sinan@linux.alibaba.com, jia...@iscas.ac.cn
Sent: Mon, 5 Jun 2023 16:31:29 +0800
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please change the angenda/notes doc or let me know and I will
update them, thanks.
https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit#
in the next meeting.
GCC 13 released in April 26,you can check changes in the release notes:
https://gcc.gnu.org/gcc-13/changes.html
Best Regards,
Jiawei
> ---
> htdocs/gcc-13/changes.html | 31 ++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> index f6941534..5427f805 100644
> --- a/htdocs/gcc-13/changes.html
> +++
in the next meeting.
Best Regards,
Jiawei
Add Zcmp extension testcases, zcmpe means Zcmp with RVE extension.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Yulong Shi
Co-Authored by: Shihua Liao
Co-Authored by: Sinan Lin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zc-zcmp-push-pop-1.c: New test.
*
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
Add Zcmp extension instructions support. Generate push/pop
with follow steps:
1. preprocessing:
1.1. if there is no push rtx, then just return. e.g.
(note 5 1 22 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 22 5 23 2 (set (reg/f:SI 2 sp)
(plus:SI (reg/f:SI 2 sp)
(const_int
RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
The implementation of the RISC-V Code Size Reduction extension in GCC is
an important
From: Charlie Keaney
Add all ZC* extensions march args tests.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/arch-21.c: New
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
-原始邮件-
发件人: "Jeff Law"
发送时间: 2023-04-05 09:30:43 (星期三)
收件人: "Hans-Peter Nilsson" , Jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
主题: Re: [PATCH v2] RISC-V: Add Z*inx imcom
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109384
--- Comment #8 from jiawei ---
Thank you for this fix, I neglected to confirm the format, sorry for that.
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please change the angenda/notes doc or let me know and I will
update them, thanks.
https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit#
Z*inx is conflict with float extensions, add incompatible check when
z*inx and f extension both enabled.
Since all float extension imply f extension and all z*inx extension
imply zfinx extension, so we just need to check f with zfinx extension
as the base case.
Co-Authored by: Kito Cheng
. Maybe we can add new check function in
the new
version :)
-原始邮件-
发件人: "Kito Cheng"
发送时间: 2023-03-27 16:15:00 (星期一)
收件人: Jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
主题: Re: [PATCH] RIS
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-19.c: New test.
---
gcc/config/riscv/riscv.cc
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
---
gcc/config/riscv/riscv.cc | 4
1 file changed, 4 insertions(+)
diff --git
in the next meeting.
Best Regards,
Jiawei
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please change the angenda/notes doc or let me know and I will
update them, thanks.
https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit#
getVariable(riscv_zk_subext)> +> +Mask(ZKR) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSED) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSH) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKT) in
> TargetVariable(riscv_zk_subext)> +> TargetVari
riable(riscv_zvl_flags)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext
in the next meeting.
Best Regards,
Jiawei
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- RVV gcc support progress
- Intrinsic naming guidelines
- Libsanitizer option support
Hi all,
Tomorrow's RISC-V GNU Toolchain meeting will be canceled, since during the
Spring Festival holiday.
The next RISC-V GNU Toolchain meeting is collecting topics.
Please let me know if you have any topics want to discuss in the next meeting.
BR
Jiawei
Hi all,
Tomorrow's RISC-V GNU Toolchain meeting will be canceled, since there are few
new topics to discuss.
The next RISC-V GNU Toolchain meeting is collecting topics.
Please let me know if you have any topics want to discuss in the next meeting.
BR
Jiawei
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
--- Comment #3 from jiawei ---
(In reply to Kito Cheng from comment #2)
> It seems right to me?
Yes, It have the same behavior with clang, but it could generate better
assemble code like:
vl1re8.vv24,0(a0)
addi a4,a1,800
vs1r.v v24,0
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- RVV gcc support status
- Profile progress discuss
- Sub-extensions support status
-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
jiawei changed:
What|Removed |Added
Version|13.0|fortran-dev
--- Comment #1 from jiawei
: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jiawei at iscas dot ac.cn
Target Milestone: ---
Currently, when use gcc13 to compile follow code with rvv
extension(-march=rv64gcv -O3),
void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int
cond
Hi all,
Tomorrow's meeting will be canceled, since there was few new topics to discuss.
The next RISC-V GNU Toolchain meeting is collecting.
Please let me know if you have any topics want to discuss in the next meeting.
Best Regards,
Jiawei
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- riscv-gnu-toolchain repo's updates
- RVV gcc support & RVV c intrinsic api progress
-
-原始邮件-
发件人: "Jeff Law"
发送时间: 2022-11-21 23:26:37 (星期一)
收件人: "juzhe.zh...@rivai.ai" , schwab
抄送: gcc-patches , "monk.chiang"
, "kito.cheng" , jiawei
主题: Re: [PATCH] RISC-V: Add RVV registers register spilling
On 11/21/22 02
Hi all,
Tomorrow's meeting will be canceled, since there was few new topics to discuss.
The next RISC-V GNU Toolchain meeting will be held on Dec 1.
Please let me know if you have any topics want to discuss in the next meeting.
Best Regards,
Jiawei
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
---
.../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
al to zero, remove redundant insn gen.
```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
ld s0,24(sp)
addisp,sp,32
jr ra
```
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
jiawei (2):
RISC-V: Add spill sp ad
-原始邮件-
发件人: "Kito Cheng"
发送时间: 2022-11-15 09:48:26 (星期二)
收件人: jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@rivosinc.com,
juzhe.zh...@rivai.ai, christoph.muell...@vrull.eu, philipp.toms...@vrull.eu,
wuwei2...@iscas.ac.cn
主题: Re: [PATCH] RISC-V: O
Skip add insn generate if the adjust size equal to zero.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New if control segement.
---
gcc/config/riscv/riscv.cc | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- RISC-V profile progress
- RVV gcc support progress
- Zcmt relaxation and speical section
Add two new function to handle profile input,
"parse_profile" will check if a input into -march is
legal, if it is then "handle_profile" will check the
profile's type[I/M/A], year[20/22] and mode[U/S/M],
set different extensions combine, just deal mandatory
part currently.
gcc/ChangeLog:
Supports RISC-V profiles[1] in -march option, add minimal extension name
supports.
Default input set the profile is before other formal extensions.
Test with -march=RV[I/M/A]2[0/2][U/M/S][64/32]+otherextensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
jiawei (2
This patch just add name support contain in profiles.
Set the extension version as 0.1.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/riscv-opts.h (MASK_ZICCAMOA): New mask.
(MASK_ZICCIF): Ditto.
(MASK_ZICCLSM): Ditto.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357
jiawei changed:
What|Removed |Added
Resolution|--- |FIXED
Status|UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357
--- Comment #2 from jiawei ---
Verified, Thanks!
Assignee: unassigned at gcc dot gnu.org
Reporter: jiawei at iscas dot ac.cn
Target Milestone: ---
When build target riscv with arch "rv64gc_zve32x" or "rv64gc_zve32f" it will
got an error:
/root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8369:
test_vector
From: Jiawei
Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.
Co-Authored-By: Sinan Lin.
gcc/ChangeLog:
* config/riscv/constraints.md
From: Jiawei
Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/riscv
From: Jiawei
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_ZFINX):New target.
(TARGET_ZDINX): Ditto
/zfhmin.
Jiawei (4):
RISC-V: Minimal support of z*inx extension.
RISC-V: Target support for z*inx extension.
RISC-V: Limit regs use for z*inx extension.
RISC-V: Add zhinx/zhinxmin testcases.
gcc/common/config/riscv/riscv-common.cc | 18 +
gcc/config/riscv/arch-canonicalize
From: Jiawei
Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and
'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension
imply 'zicsr'.
Co-Authored-By: Sinan Lin.
gcc
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- RISC-V profile develop plan
- Patchwork for patch initial review
- RISC-V sub-extension
Hi all,
Tomorrow's meeting will be canceled, since there was few new topics to discuss.
The next RISC-V GNU Toolchain meeting will be held on Oct 6.
Please let me know if you have any topics want to discuss in the next meeting.
Best Regards,
Jiawei
LGTM, Maybe we can try is after RVV supported.> We don't yet support
vectorization on RISC-V.
> > gcc/testsuite/ChangeLog> > * gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V
> > targets.> ---> gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +-> 1 file
> > changed, 1 insertion(+), 1 deletion(-)>
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
V2: Add assembler support check info for -mcsr-check. Thanks for Kito's
suggestions.
gcc/ChangeLog:
* config.in: New def
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- Bump riscv-gnu-toolchain repo's submodules
- RISC-V sub-extension supports progress
Hi all,
Tommorrow's meeting will be canceled, since it during 2022 RISC-V Summit China .
The next RISC-V GNU toolchian meeting will be held on Sep 8.
Please let me know if you have any topics want to discuss in the next meeting.
Best Regards,
Jiawei
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586
jiawei changed:
What|Removed |Added
CC||jiawei at iscas dot ac.cn
--- Comment #7 from
BEGIN:VCALENDAR
PRODID:-//zoom.us//iCalendar Event//EN
VERSION:2.0
CALSCALE:GREGORIAN
METHOD:PUBLISH
CLASS:PUBLIC
BEGIN:VTIMEZONE
TZID:Asia/Singapore
LAST-MODIFIED:20220317T223602Z
TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore
X-LIC-LOCATION:Asia/Singapore
BEGIN:STANDARD
TZNAME:+08
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- Call for contributors/maintainers: riscv-gnu-toolchain repo
- Unify interface to query
-原始邮件-
发件人: "Richard Biener"
发送时间: 2022-07-28 15:45:27 (星期四)
收件人: jiawei
抄送: gcc-patches@gcc.gnu.org, ja...@redhat.com, pal...@rivosinc.com,
kito.ch...@gmail.com, jim.wilson@gmail.com, wuwei2...@iscas.ac.cn
主题: Re: [PATCH] testsuite: Add extra RISC-V
This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.
gcc/testsuite/ChangeLog:
* gcc.dg/pr106397.c: New
.
Best wishes,
Jiawei
gcc/ChangeLog
* config.gcc (riscv): Accept rv64e and lp64e.
* config/riscv/arch-canonicalize: Likewise.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Likewise.
* config/riscv/riscv-opts.h (riscv_abi_type): Likewise.
* config/riscv/riscv.cc (riscv_option_override): Likewise
*
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- [RFC] RV64E/lp64e supports
gcc:
Hi all,
Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any
topics want to
discuss or share, please let me know and I will add them to the agenda, thanks.
Agenda:
- RVV supports status
RVV calling convention to aid lazy binding
Hi all,
Tomorrow meeting will cancel since there are few new topics to discuss.
The next meeting will be two weeks later.
Regrads,
PLCT Jiawei
From: Jia-wei Chen
In rv32 regression test, this cases will report an error:
"cc1: error: ABI requires '-march=rv32'"
Add '-mabi' option will fix this.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105666.c: New options.
---
gcc/testsuite/gcc.target/riscv/pr105666.c | 2 +-
1 file
Hi all,
Here is the agenda for tomorrow's meeting. If you have topics to
discuss or share, please let me know and I can add them to the agenda.
Agenda:
- Handling profiles in the tools
comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
jiawei (3):
RISC-V: Minimal support of zfinx
From: Jia-Wei Chen
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT' and 'TARGET_DOUBLE_FLOAT' patterns.
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
From: Jia-Wei Chen
Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when
'zdinx' enable.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS :
((TARGET_ZFINX ||
From: Jia-Wei Chen
Minimal support of zfinx extension, include 'zfinx' and 'zdinx'
corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add z[f/d]inx extension info.
*
comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
jiawei (3):
RISC-V: Minimal support of zfinx
-gnu-toolchain submodule shift PR and make some
disscuss: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1074
FP16 support discuss:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1077
Regrads,
PLCT Jiawei
Similar to patch 593993, RISC-V needs to limit symbols send in sdata.
Thanks for Palmer's help.
gcc/testsuite/ChangeLog:
* g++.dg/opt/const7.C: Don't use small data on RISC-V.
---
gcc/testsuite/g++.dg/opt/const7.C | 1 +
1 file changed, 1 insertion(+)
diff --git
Some compiler target like arm-linux\riscv\power\s390x\xtensa-gcc handle
char as unsigned char, then there are no warnings occur and got FAIL cases.
Just change the type char into explicit signed char to keep the feature
consistency.
gcc/testsuite/ChangeLog:
*
Hi all,
Here is the agenda for tomorrow's meeting. If you have topics to
discuss or share, please let me know and I can add them to the agenda.
Agenda:
- Conventions for vendor extension
- Link https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17
- zicntr and zihpm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892
--- Comment #14 from jiawei ---
(In reply to palmer from comment #13)
> I just posted a patch
> <https://gcc.gnu.org/pipermail/gcc-patches/2022-May/593995.html> that
> removes the undefined behavior from this test case, wit
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94157
--- Comment #11 from jiawei ---
(In reply to Martin Liška from comment #10)
> Seems you are using the latest binutils ld, right?
>
> It's the newly added warning which tells that usage of executable stack is a
> potential se
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94157
jiawei changed:
What|Removed |Added
CC||jiawei at iscas dot ac.cn
--- Comment #9 from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892
jiawei changed:
What|Removed |Added
CC||jiawei at iscas dot ac.cn
--- Comment #11
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