On Mon, Sep 14, 2020 at 08:35:44PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> >> Although this looks/sounds complicated, the advantage is that everything
> >> remains up-to-date. If we instead added a second attribute and only
> >> defined it for instructions like *add__,
Segher Boessenkool writes:
>> Although this looks/sounds complicated, the advantage is that everything
>> remains up-to-date. If we instead added a second attribute and only
>> defined it for instructions like *add__, other instructions
>> (including config/arm instructions) would still have
Hi!
On Mon, Sep 14, 2020 at 10:55:35AM +0100, Richard Sandiford wrote:
> "Qian, Jianhua" writes:
> > - If we cannot resolve it, the existing CPUs' descriptions need
> > to be changed. This is not what I expected.
> > - If we want to add new attribute to resolve this
"Qian, Jianhua" writes:
> Hi Richard and Segher
>
> I don't know if I exactly understood your discussion.
> If I misunderstood, please let me know.
>
> I am trying to test these two cases.
> Case 1. keep the TYPE attribute unchanged, add new attributes
> It works well as below.
>
On 14/09/2020 03:53, Qian, Jianhua wrote:
>> -Original Message-
>> From: Richard Earnshaw
>> Sent: Friday, September 11, 2020 9:30 PM
>> To: Qian, Jianhua/钱 建华 ; gcc@gcc.gnu.org
>> Subject: Re: A problem with one instruction multiple latencies and pipelines
&
- If we want to add new attribute to resolve this problem, why not
use the Case1 directly?
> It is very much not what I am saying. I *am* saying that if people trying to
> improve one CPU's modelling have to edit over 20 models for CPUs that they do
> not care about, mistakes
> -Original Message-
> From: Richard Earnshaw
> Sent: Friday, September 11, 2020 9:30 PM
> To: Qian, Jianhua/钱 建华 ; gcc@gcc.gnu.org
> Subject: Re: A problem with one instruction multiple latencies and pipelines
>
> On 07/09/2020 07:08, Qian, Jianhua wrote:
> >
Hi!
On Fri, Sep 11, 2020 at 08:44:54AM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > Consider cores that do not care about the "subtype" at all: when using
> > just "type", all cores have to test for "foo,foo_subtype", while with
> > a separate attribute they can just test for
On 07/09/2020 07:08, Qian, Jianhua wrote:
> Hi
>
> I'm adding a new machine model. I have a problem when writing the
> "define_insn_reservation" for instruction scheduling.
> How to write the "define_insn_reservation" for one instruction that there are
> different latencies and pipelines
Segher Boessenkool writes:
> On Thu, Sep 10, 2020 at 11:04:26AM +0100, Richard Sandiford wrote:
>> Segher Boessenkool writes:
>> > You can also use some other attributes to classify instructions, you
>> > don't have to put it all in one "type" attribute. This can of course be
>> > done later,
On Thu, Sep 10, 2020 at 11:04:26AM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > You can also use some other attributes to classify instructions, you
> > don't have to put it all in one "type" attribute. This can of course be
> > done later, at a time when it is clearer what a
Segher Boessenkool writes:
> Hi!
>
> On Mon, Sep 07, 2020 at 09:20:59PM +0100, Richard Sandiford wrote:
>> This is just personal opinion, but in general (from the point of view
>> of a new port, or a new subport like SVE), I think the best approach
>> to handling the "type" attribute is to start
ol
> Sent: Thursday, September 10, 2020 5:23 AM
> To: Qian, Jianhua/钱 建华 ; gcc@gcc.gnu.org;
> richard.sandif...@arm.com
> Subject: Re: A problem with one instruction multiple latencies and pipelines
>
> Hi!
>
> On Mon, Sep 07, 2020 at 09:20:59PM +0100, Richard Sandifor
Hi!
On Mon, Sep 07, 2020 at 09:20:59PM +0100, Richard Sandiford wrote:
> This is just personal opinion, but in general (from the point of view
> of a new port, or a new subport like SVE), I think the best approach
> to handling the "type" attribute is to start with the coarsest
> classification
n, Jianhua/钱 建华
> Cc: gcc@gcc.gnu.org
> Subject: Re: A problem with one instruction multiple latencies and pipelines
>
> "Qian, Jianhua" writes:
> > Hi
> >
> > I'm adding a new machine model. I have a problem when writing the
> "define_in
"Qian, Jianhua" writes:
> Hi
>
> I'm adding a new machine model. I have a problem when writing the
> "define_insn_reservation" for instruction scheduling.
> How to write the "define_insn_reservation" for one instruction that there are
> different latencies and pipelines according to parameter.
On Mon, Sep 7, 2020 at 10:46 AM Qian, Jianhua wrote:
>
> Hi Richard
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Monday, September 7, 2020 3:41 PM
> > To: Qian, Jianhua/钱 建华
> > Cc: gcc@gcc.gnu.org
> > Subject: Re: A pr
Hi Richard
> -Original Message-
> From: Richard Biener
> Sent: Monday, September 7, 2020 3:41 PM
> To: Qian, Jianhua/钱 建华
> Cc: gcc@gcc.gnu.org
> Subject: Re: A problem with one instruction multiple latencies and pipelines
>
> On Mon, Sep 7, 2020 at 8:10
On Mon, Sep 7, 2020 at 8:10 AM Qian, Jianhua wrote:
>
> Hi
>
> I'm adding a new machine model. I have a problem when writing the
> "define_insn_reservation" for instruction scheduling.
> How to write the "define_insn_reservation" for one instruction that there are
> different latencies and
Hi
I'm adding a new machine model. I have a problem when writing the
"define_insn_reservation" for instruction scheduling.
How to write the "define_insn_reservation" for one instruction that there are
different latencies and pipelines according to parameter.
For example, the ADD (shifted
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