[Bug tree-optimization/115214] tree-ssa-pre.c(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214 jiawei changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug c/115214] New: tree-ssa-pre.c(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214 Bug ID: 115214 Summary: tree-ssa-pre.c(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #25 from jiawei --- I had run SPEC2017-v1.1.9 with rv64gcv_zvl256b, it passed the compile and run on base and validate cases, used qemu 8.1.0.

[Bug target/109384] [13 Regression] unquoted keyword 'float' in format [-Werror=format-diag]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109384 --- Comment #8 from jiawei --- Thank you for this fix, I neglected to confirm the format, sorry for that.

[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 --- Comment #3 from jiawei --- (In reply to Kito Cheng from comment #2) > It seems right to me? Yes, It have the same behavior with clang, but it could generate better assemble code like: vl1re8.vv24,0(a0) addi a4,a1,800 vs1r.v

[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 jiawei changed: What|Removed |Added Version|13.0|fortran-dev --- Comment #1 from jiawei ---

[Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 Bug ID: 108185 Summary: [RISC-V]RVV assemble not set vsetvli correct. Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/107357] [RISC-V]RVV broken with zve32x/f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 jiawei changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/107357] [RISC-V]RVV broken with zve32x/f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 --- Comment #2 from jiawei --- Verified, Thanks!

[Bug other/107357] New: [RISC-V]RVV broken with zve32x/f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 Bug ID: 107357 Summary: [RISC-V]RVV broken with zve32x/f Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: other

[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #7 from

[Bug tree-optimization/102892] [12/13 Regression] Dead Code Elimination Regression at -O3 (trunk vs 11.2.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892 --- Comment #14 from jiawei --- (In reply to palmer from comment #13) > I just posted a patch > that > removes the undefined behavior from this test case, with that it links on >

[Bug lto/94157] [10 Regression] error: lto-wrapper failed with -Wa,--noexecstack -Wa,--noexecstack since r10-6807-gf1a681a174cdfb82

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94157 --- Comment #11 from jiawei --- (In reply to Martin Liška from comment #10) > Seems you are using the latest binutils ld, right? > > It's the newly added warning which tells that usage of executable stack is a > potential security issue: >

[Bug lto/94157] [10 Regression] error: lto-wrapper failed with -Wa,--noexecstack -Wa,--noexecstack since r10-6807-gf1a681a174cdfb82

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94157 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #9 from

[Bug tree-optimization/102892] [12 Regression] Dead Code Elimination Regression at -O3 (trunk vs 11.2.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102892 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #11

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #59 from jiawei --- Hi Kito, Okay, I will retest the benchmark on gem5. 发自我的小米手机在 "kito at gcc dot gnu.org" ，2020年12月25日 上午11:31写道： https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #58 from

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #56 from jiawei --- Hi Kito, I test the performance data on qemu-riscv64, and compile the benchmark with riscv-unknown-linux-gnu-gcc -Os. All the modify is set in /coremark-pro/util/make/ to change the toolchain and

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #54 from jiawei --- Hi Jim. I had finished the test on the benchmark Coremark-pro.And it shows that the patch doesn't accidentally increase code size. This test with the args "XCMD='-c4' certify-all", and the result shows follow:

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #53 from jiawei --- Hi Jim, Levy had asked me to help about the test. I was resigned on EEMBC and waiting acess for more benchmarks. Now I am testing on csibe and coremax-pro. I think will lineout the result in this

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #4 from jiawei --- I had did some tests with this problem and find: foo.c #include extern volatile bool active; int foo(void) { if (!active) { return 42; } else { return -42; } } code generated in foo.s foo:

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #2 from