[Bug other/113575] [14 Regression] memory hog building insn-opinit.o (i686-linux-gnu -> riscv64-linux-gnu)

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113575 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment

[Bug target/113790] [14 Regression][riscv64] ICE in curr_insn_transform, at lra-constraints.cc:4294 since r14-4944-gf55cdce3f8dd85

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113790 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/113790] [14 Regression][riscv64] ICE in curr_insn_transform, at lra-constraints.cc:4294 since r14-4944-gf55cdce3f8dd85

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113790 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Last

[Bug target/114000] [11/12/13/14 Regression] ICE: in force_nonfallthru_and_redirect, at cfgrtl.cc:1556 with -O2 -freorder-blocks-and-partition -fPIC -mexplicit-relocs

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114000 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/114000] [11/12/13/14 Regression] ICE: in force_nonfallthru_and_redirect, at cfgrtl.cc:1556 with -O2 -freorder-blocks-and-partition -fPIC -mexplicit-relocs

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114000 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug debug/100523] [11/12/13/14 Regression] armv8.1-m.main -fcompare-debug failure with -O -fmodulo-sched -mtune=cortex-a53

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100523 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org

[Bug rtl-optimization/110317] [12/13/14 Regression] ICE at -O2 and -O3 with "-fno-tree-pre -fno-tree-dce -fno-tree-dse -fselective-scheduling2": in move_exprs_to_boundary, at sel-sched.cc:5228

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org

[Bug rtl-optimization/110391] [12/13/14 Regression] wrong code at -O2 and -O3 with "-fsel-sched-pipelining -fselective-scheduling2" on x86_64-linux-gnu

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org

[Bug rtl-optimization/112758] [13/14 Regression] Inconsistent Bitwise AND Operation Result between int and long long int

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112758 --- Comment #19 from Jeffrey A. Law --- Fixed by Jakub's patch on the trunk.

[Bug target/113010] [RISCV] sign-extension lost in comparison with constant embedded in comma-op expression

2024-03-03 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Resolution|--- |FIXED --- Comment #11 from Jeffrey A. Law --- Fixed by Greg's patch on the trunk. No current plans to backport.

[Bug c++/113976] [11/12/13/14 Regression] explicit instantiation of const variable template following implicit instantiation is assembled in .rodata instead of .bss since r8-2857-g2ec399d8a6c9c2

2024-02-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113976 --- Comment #3 from Jeffrey A. Law --- What does the standard say about changing const objects?

[Bug target/84201] 549.fotonik3d_r from SPEC2017 fails verification with recent Intel and AMD CPUs

2024-01-24 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84201 Jeffrey A. Law changed: What|Removed |Added CC||vineetg at gcc dot gnu.org --- Comment

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

2024-01-24 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 113570, which changed state. Bug 113570 Summary: RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 What|Removed

[Bug target/113570] RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build

2024-01-24 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE

[Bug target/113570] RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build

2024-01-24 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 --- Comment #3 from Jeffrey A. Law --- See pr84201 for more details as well as https://www.spec.org/cpu2017/Docs/benchmarks/549.fotonik3d_r.html

[Bug rtl-optimization/113533] New: [14 Regression] Code generation regression after change for pr111267

2024-01-21 Thread law at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- sh3-linux-gnu or sh3eb-linux-gnu is showing a code generation regression after the changes for pr111267. test_01 with -O1

[Bug target/82420] ICE with -malign-int and -m68000

2024-01-21 Thread law at gcc dot gnu.org via Gcc-bugs
|--- |FIXED Target Milestone|--- |14.0 CC||law at gcc dot gnu.org --- Comment #8 from Jeffrey A. Law --- Fixed on the trunk. No plans to backport.

[Bug target/111279] ICE: Segmentation fault with m68k,SJLJ and -malign-int

2024-01-21 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Resolution|--- |FIXED Target Milestone|--- |14.0 --- Comment #7 from Jeffrey A. Law --- Should be fixed on the trunk. No plans to backport.

[Bug target/108640] ICE compiling busybox for m68k in change_address_1, at emit-rtl.cc:2283

2024-01-19 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Status|NEW |RESOLVED --- Comment #9 from Jeffrey A. Law --- Fixed on the trunk. No plans to backport.

[Bug target/110934] m68k: ICE with -fzero-call-used-regs=all compiling openssh 9.3p2

2024-01-19 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Status|NEW |RESOLVED --- Comment #14 from Jeffrey A. Law --- Fixed on the trunk. No plans to backport.

[Bug other/113399] [14 Regression] -ffold-mem-offsets should not be a target option

2024-01-17 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113399 --- Comment #4 from Jeffrey A. Law --- Just something that was missed when this option was changed from target dependent to target independent. It definitely should not be a target option.

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

2024-01-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 --- Comment #5 from Jeffrey A. Law --- I don't think we need to do any significant bit tracking to optimize the original neg8 test. I think we can be handled entirely within the simplify-rtx framework.I've got a junior engineer that's

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

2024-01-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed|2023-11-05 00:00:00 |2024-01-13

[Bug middle-end/111378] Missed optimization for comparing with exact_log2 constants

2024-01-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111378 --- Comment #4 from Jeffrey A. Law --- Whether or not this is an optimization or a pessimization is dependent on the target -- some targets can express the constant trivially in a branch conditions, others can not. Some targets have barrel

[Bug testsuite/113167] [14 Regression] gcc.dg/tree-ssa/gen-vect-26.c started failing many targets after recent change

2023-12-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113167 --- Comment #7 from Jeffrey A. Law --- So far that's the only fallout I've seen on the embedded targets. The qemu emulated natives aren't running as I've got some kind of network problem here and the workers are going offline after a few hours

[Bug tree-optimization/113167] New: [14 Regression] gcc.dg/tree-ssa/gen-vect-26.c started failing many targets after recent change

2023-12-28 Thread law at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- Many targets are now seeing this failure: FAIL: gcc.dg/tree-ssa/gen-vect-26.c scan-tree-dump

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-12-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/112413] Wrong switch jump table offset

2023-12-11 Thread law at gcc dot gnu.org via Gcc-bugs
|RESOLVED CC||law at gcc dot gnu.org --- Comment #9 from Jeffrey A. Law --- Fixed on the trunk. No plans to backport.

[Bug tree-optimization/112848] [14 regression] ICE compiling gcc.dg/tree-ssa/ssa-sink-16.c after r14-6114-gde0ab339a79535

2023-12-04 Thread law at gcc dot gnu.org via Gcc-bugs
||2023-12-04 Ever confirmed|0 |1 CC||law at gcc dot gnu.org --- Comment #2 from Jeffrey A. Law --- Also seeing on microblaze-linux.

[Bug debug/112674] New: [14 Regression] Compare-debug failure after recent change on c6x

2023-11-22 Thread law at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: debug Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This patch: commit 6bf66276e3e41d5d92f7b7260e98b6a111653805 Author: Richard Biener Date: Wed Nov 22 11:10:41 2023 +0100 tree

[Bug debug/112674] [14 Regression] Compare-debug failure after recent change on c6x

2023-11-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112674 --- Comment #1 from Jeffrey A. Law --- And possibly more interesting than the compare-debug failure is this patch seems to be causing Wstringop-overflow-17 to fail on multiple targets, including c6x.

[Bug tree-optimization/112530] [14 Regression] New ICE in gimple->rtl expansion after recent change

2023-11-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112530 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c

2023-11-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #14 from Jeffrey A. Law --- *** Bug 112530 has been marked as a duplicate of this bug. ***

[Bug tree-optimization/112530] New: [14 Regression] New ICE in gimple->rtl expansion after recent change

2023-11-14 Thread law at gcc dot gnu.org via Gcc-bugs
mal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit a5922427c29fad177251d89cc946d1c5bfc135eb Author: Andrew Stubbs Date: Fri Oct 20 16:26:51 2

[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c

2023-11-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment

[Bug target/112478] riscv: asm clobbers not honored

2023-11-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #43 from Jeffrey A. Law --- I would expect allowing larger offsets before reload to be a significant problem. The core issue is integer memory operations allow 14 bits while FP only allows 5. During reloading we don't know if any

[Bug bootstrap/112497] [14 Regression] Bootstrap comparison failure: gcc/analyzer/constraint-manager.o differs on loongarch64-linux-gnu

2023-11-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112497 --- Comment #5 from Jeffrey A. Law --- This failure means the stage1 and stage2 compilers generated different code for the same input. So when I need to debug this I usually start by first getting that source code. Based in the title of this

[Bug bootstrap/112497] [14 Regression] Bootstrap comparison failure: gcc/analyzer/constraint-manager.o differs on loongarch64-linux-gnu

2023-11-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112497 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #3

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #41 from Jeffrey A. Law --- I would agree. In fact,the whole point of the f-m-o pass is to bring those immediates into the memory reference. It'd be really useful to know why that isn't happening. The only thing I can think of

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-09 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #31 from Jeffrey A. Law --- IIRC r21 is call-clobbered. So I guess the question turns into what was the sequence before f-m-o got involved -- was it assuming r21 would be preserved, or did f-m-o make r21 live across the call?

[Bug tree-optimization/112468] New: [14 Regression] Missed phi-opt after recent change

2023-11-09 Thread law at gcc dot gnu.org via Gcc-bugs
Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit 3f176e1adc6bc9cc2c21222d776b51d9f43cb66b (HEAD) Author: Tamar Christina Date: Thu Nov 9 13:59:39 2023 + middle-end: optimize

[Bug target/112462] New: RISC-V zicond cost model enhancements

2023-11-09 Thread law at gcc dot gnu.org via Gcc-bugs
Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- Currently the costing of zicond always returns COSTS_N_INSNS (1) which can be inaccurate. I see two primary issues that need to be fixed. First, for conditions which are not equality

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-08 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #26 from Jeffrey A. Law --- As a compiler junkie, I tend to think compiler first until I can prove it otherwise. I wouldn't get too hung up on aliasing issues and such at this point. Do we already have a dump for the key function?

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-08 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #19 from Jeffrey A. Law --- f-m-o runs post-allocation, so the scope of where it's behavior can change things is narrower. So testing with -fno-schedule-insns isn't going to be useful, but -fno-schedule-insns2 might. I'm a bit

[Bug rtl-optimization/112415] [14 regression] Python 3.11 miscompiled on HPPA with new RTL fold mem offset pass, since r14-4664-g04c9cf5c786b94

2023-11-06 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112415 --- Comment #6 from Jeffrey A. Law --- Do we have assembly code around the faulting point (x/20i $pc) and a register dump (i r)? The biggest concern I'd have with f-m-o on the PA would be the implicit segment selection that happens on the base

[Bug target/111311] RISC-V regression testsuite errors with --param=riscv-autovec-preference=scalable

2023-11-02 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311 --- Comment #14 from Jeffrey A. Law --- As Andrew said, if there's a test that depends on behavior of -INT_MIN, then the test needs to be fixed. That's undefined behavior.

[Bug rtl-optimization/109035] meaningless memory store on RISC-V and LoongArch

2023-11-02 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109035 --- Comment #8 from Jeffrey A. Law --- No spills on rv64 either.

[Bug rtl-optimization/104387] aarch64: Redundant SXTH for “bag of bits” moves

2023-11-01 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104387 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug tree-optimization/112320] [14 Regression] crash from insert_debug_temp_for_var_def since r14-5032-ge3da1d7bb288c8

2023-10-31 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112320 --- Comment #6 from Jeffrey A. Law --- Created attachment 56480 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56480=edit Testcase for fr30-elf -Os -g

[Bug tree-optimization/112320] [14 Regression] crash from insert_debug_temp_for_var_def since r14-5032-ge3da1d7bb288c8

2023-10-31 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Last reconfirmed||2023-11-01 Ever confirmed|0 |1 --- Comment #5 from Jeffrey A. Law --- I've bisected a failure on fr30-elf to the same commit. The failure mode is different, but given it's

[Bug target/112298] Poor code for DImode operations on H8 port

2023-10-30 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112298 Jeffrey A. Law changed: What|Removed |Added Target||h8300 Priority|P3

[Bug target/112298] New: Poor code for DImode operations on H8 port

2023-10-30 Thread law at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- long long foo(long long x) { return x << 1; } Highlights several code inefficiencies WRT DImode values on the H8. I would expect that defining a reasonable adddi3 an

[Bug libstdc++/107885] H8/300: libsupc++/hash_bytes.cc fix shift-count-overflow warning

2023-10-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107885 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org

[Bug target/111466] RISC-V: redundant sign extensions despite ABI guarantees

2023-10-19 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Resolution|--- |FIXED --- Comment #5 from Jeffrey A. Law --- Fixed on the trunk now.

[Bug tree-optimization/111798] New: [14 Regression] Recent change causing testsuite regression and poor code on mcore-elf

2023-10-13 Thread law at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit 6decda1a35be5764101987c210b5693a0d914e58 Author: Richard Biener Date: Thu Oct

[Bug middle-end/111777] [14 regression] build breaks after r14-4558-g400efdddf3d849

2023-10-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111777 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug middle-end/111777] [14 regression] build breaks after r14-4558-g400efdddf3d849

2023-10-11 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111777 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/93062] Failed to generate indirect branch for long branches on riscv

2023-10-10 Thread law at gcc dot gnu.org via Gcc-bugs
|RESOLVED CC||law at gcc dot gnu.org --- Comment #3 from Jeffrey A. Law --- This should be fixed on the trunk now. No plans to backport to the release branches.

[Bug bootstrap/111664] [14 regression] Fails to build with mawk (error in gcc/opt-read.awk) after r14-4354-ge4a4b8e983bac8

2023-10-07 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Resolution|--- |FIXED --- Comment #6 from Jeffrey A. Law --- Fixed on the trunk.

[Bug rtl-optimization/111384] missed optimization: GCC adds extra any extend when storing subreg#0 multiple times

2023-10-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111384 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2023-10-07 Ever confirmed|0

[Bug target/109414] RISC-V: unnecessary sext.w in rv64

2023-10-07 Thread law at gcc dot gnu.org via Gcc-bugs
|RESOLVED CC||law at gcc dot gnu.org --- Comment #5 from Jeffrey A. Law --- These code generation inefficiences have been fixed. I didn't bisect, but I would hazard a guess it was Jivan's work on exposing the widening nature of the 32

[Bug target/106271] Bootstrap on RISC-V on Ubuntu 22.04 LTS: bits/libc-header-start.h: No such file or directory

2023-10-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106271 Jeffrey A. Law changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug target/64215] -Os misses an opportunity to merge two ret instructions

2023-10-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64215 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug target/111670] H8/300 SX uses incorrect code sequences

2023-10-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111670 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4 Target|

[Bug target/111670] New: H8/300 SX uses incorrect code sequences

2023-10-03 Thread law at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- The H8/SX port can create sequences like (set (mem (autoinc (reg sp)) (reg_sp)) Here autoinc is PRE_DECEMENT or PRE_INCREMENT addressing modes. Which is invalid RTL. I believe

[Bug rtl-optimization/111467] REE failing to eliminate redundant extension due to multiple reaching def(s)

2023-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111467 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #2

[Bug target/82666] [11/12/13/14 regression]: sum += (x>128 ? x : 0) puts the cmov on the critical path (at -O2)

2023-08-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82666 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #14

[Bug driver/77576] gcc-ar doesn't work if all options are read from file

2023-07-31 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77576 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org

[Bug target/110748] RISC-V: optimize store of DF 0.0

2023-07-20 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug tree-optimization/105832] [13/14 Regression] Dead Code Elimination Regression at -O3 (trunk vs. 12.1.0)

2023-07-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105832 --- Comment #11 from Jeffrey A. Law --- Looks viable to me. Are you thinking match.pd?

[Bug target/110559] Bad mask_load/mask_store codegen of RVV

2023-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110559 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug tree-optimization/110460] New: [14 Regression] ft32 ICE on 931110-1.c with new TYPE_PRECISION checking

2023-06-28 Thread law at gcc dot gnu.org via Gcc-bugs
: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- commit fe48f2651334bc4d96b6df6b2bb6b29fcb732a83 Author: Richard Biener Date: Fri Jun 9 09:31:14 2023 +0200

[Bug rtl-optimization/110423] Redundant constants not getting eliminated on RISCV.

2023-06-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110423 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #2

[Bug debug/110308] [14 Regression] ICE on audiofile-0.3.6: RTL: vartrack: Segmentation fault in mode_to_precision(machine_mode)

2023-06-20 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110308 --- Comment #9 from Jeffrey A. Law --- Right. It's fairly common with fold-mem-offsets to end up rewriting the address arithmetic such that we'll have an sp->gpr copy of some sort in the IL. We'd really like to be able to cprop that copy

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-06-19 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #4 from Jeffrey A. Law --- Yea, the tests aren't great. They'll be better shortly. They'll test non-constant arguments and out-of-range constants, expecting a suitable diagnostic. They'll also test the extrema of valid constants.

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

2023-06-19 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/110264] internal compiler error: riscv_vector::vector_insn_info::get_avl_reg_rtx

2023-06-17 Thread law at gcc dot gnu.org via Gcc-bugs
||2023-06-17 Ever confirmed|0 |1 CC||law at gcc dot gnu.org --- Comment #5 from Jeffrey A. Law --- Note that Pan can cherry pick it into gcc-13. Typically folks wait a week or so after the patch

[Bug middle-end/79173] add-with-carry and subtract-with-borrow support (x86_64 and others)

2023-06-17 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79173 --- Comment #23 from Jeffrey A. Law --- risc-v doesn't have any special instructions to implement add-with-carry or subtract-with-borrow. Depending on who you talk do, it's either a feature or a mis-design.

[Bug tree-optimization/110218] sink pass heuristic not working in practice

2023-06-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110218 --- Comment #2 from Jeffrey A. Law --- So what I think was happening was that we would sink past a bunch of conditionals that were never going to be true thinking that we were moving to a deeper control nest. So the idea was to use the

[Bug rtl-optimization/110163] [14 Regression] Comparing against a constant string is inefficient on some targets

2023-06-09 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110163 --- Comment #2 from Jeffrey A. Law --- It is a regression for rv64. So probably P4 would be most appropriate.

[Bug rtl-optimization/110163] New: [14 Regression] Comparing against a constant string is inefficient on some targets

2023-06-07 Thread law at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- Comparing against a constant string is expanded by inline_string_cmp and on some targets the generated code

[Bug target/110109] RISC-V: ICE when build the Intrinsic code

2023-06-04 Thread law at gcc dot gnu.org via Gcc-bugs
||law at gcc dot gnu.org Resolution|--- |FIXED --- Comment #4 from Jeffrey A. Law --- Should be fixed on the trunk.

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-30 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #10 from Jeffrey A. Law --- Created attachment 55218 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55218=edit (Incomplete) Patch

[Bug tree-optimization/108041] ivopts results in extra instruction in simple loop

2023-05-30 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108041 --- Comment #4 from Jeffrey A. Law --- Patch was for a different problem. Sorry.

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-30 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #9 from Jeffrey A. Law --- Weird, I don't see the attachment either. I'll extract & upload it again. WRT costing. fwprop and combine will both query the target rtx costs and will reject when the target costing model indicates the

[Bug tree-optimization/108041] ivopts results in extra instruction in simple loop

2023-05-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108041 --- Comment #3 from Jeffrey A. Law --- Created attachment 55185 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55185=edit (Incomplete) Patch

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #7 from Jeffrey A. Law --- Attached is what I cobbled together. It doesn't use magic numbers. But it doesn't yet handle zero extensions in the simplify-rtx code. But I think it shows the overall direction fairly well.

[Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c

2023-05-19 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug tree-optimization/109848] New: [14 Regression] Recent change causing testsuite ICE on csky port

2023-05-13 Thread law at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This patch: commit cc0e22b3f25d4b2a326322bce711179c02377e6c Author: Richard Biener Date: Fri May 12 13:43:27 2023 +0200

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-05-11 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #6 from Jeffrey A. Law --- I would still rather not introduce special cases for SUBREGs if we can avoid it. I think the question remains whether or not patching simplify-rtx's canonicalize_shift is sufficient to fix this problem

[Bug target/109777] [14 regression] Compare-debug failure after recent changes

2023-05-08 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109777 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4 --- Comment #4 from Jeffrey A. Law

[Bug testsuite/109776] [14 Regression] pr81192 fails on some targets after recent propagator changes

2023-05-08 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109776 --- Comment #7 from Jeffrey A. Law --- Thanks. That took care of the xstormy16 issues.

[Bug tree-optimization/109777] New: [14 regression] Compare-debug failure after recent changes

2023-05-08 Thread law at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit 21e2ef2dc25de318de29ec32d5390350c6717c6a (refs/bisect/bad) Author: Andrew Pinski Date: Tue May 2 00:10:46

[Bug testsuite/109776] New: [14 Regression] pr81192 fails on some targets after recent propagator changes

2023-05-08 Thread law at gcc dot gnu.org via Gcc-bugs
: normal Priority: P3 Component: testsuite Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- pr81192 is failing on some targets (xstormy16-elf for example) after this change: commit

[Bug tree-optimization/109721] New: [14 Regression] predcom-2 fails after recent changes

2023-05-03 Thread law at gcc dot gnu.org via Gcc-bugs
Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- arc-elf target. FAIL: gcc.dg/tree-ssa/predcom-2.c scan-tree-dump-times pcom "Unrolling 2 times." 2 Bisect

[Bug tree-optimization/109672] [14 regression] many ICEs after r14-323-g977a43f5ba778b

2023-04-29 Thread law at gcc dot gnu.org via Gcc-bugs
||2023-04-29 CC||law at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jeffrey A. Law --- Similar failures on arc-elf: arc-sim: gcc.c-torture/execute/pr36691.c -O3 -fomit-frame-pointer -funroll

[Bug testsuite/109549] [14 Regression] Conditional move regressions after r14-53-g675b1a7f113adb1d737adaf78b4fd90be7a0ed1a

2023-04-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109549 Jeffrey A. Law changed: What|Removed |Added Target|x86_64-*-* |s390 Summary|[14

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

2023-04-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #11 from Jeffrey A. Law --- Coming back to this. WRT extension elimination. I've been pondering if we want a late pass to do a bit of this that can't be handled by REE. So let's take the case of a Zbs instruction operating on a

[Bug rtl-optimization/109592] Failure to recognize shifts as sign/zero extension

2023-04-28 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592 --- Comment #4 from Jeffrey A. Law --- If we need to handle subregs here, I would suggest something like this if (SUBREG_P (XEXP (op0, 0)) && subreg_lowpart_p (op0) ... other tests ... That way we know we're extracting the low word of

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