[Bug target/51838] Inefficient add of 128 bit quantity represented as 64 bit tuple to 128 bit integer.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51838 --- Comment #3 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #2) > The interest thing is when i remove addti3 and ashlti3 from i386.md, GCC > generates optimal code. Yes, we had this situation with _doubleword instructions, and it

[Bug target/102057] [12 Regression] ICE at -O2 in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102057 Uroš Bizjak changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/102057] [12 Regression] ICE at -O2 in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102057 --- Comment #4 from Uroš Bizjak --- Oooh, default argument! --cut here-- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 41d85623ad6..528116dfe2d 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@

[Bug target/102057] [12 Regression] ICE at -O2 in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102057 Uroš Bizjak changed: What|Removed |Added CC||sayle at gcc dot gnu.org --- Comment #3

[Bug target/102057] ICE at -O2 in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102057 --- Comment #1 from Uroš Bizjak --- A recently added peephole is converting: (insn 229 108 280 22 (parallel [ (set (reg:CCZ 17 flags) (compare:CCZ (ashiftrt:SI (reg:SI 0 ax [orig:90 _12 ] [90])

[Bug target/102027] [11/12 Regression] ABI break when using vector type in function arg/return value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102027 --- Comment #2 from Uroš Bizjak --- gcc-11 does: : 0: 55 push %rbp 1: 48 89 e5mov%rsp,%rbp 4: 48 8b 05 00 00 00 00mov0x0(%rip),%rax# b

[Bug target/102027] [11/12 Regression] ABI break when using vector type in function arg/return value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102027 --- Comment #1 from Uroš Bizjak --- (In reply to Marek Polacek from comment #0) > We have an ABI break. Discovered by > Running > /root/rpmbuild/BUILD/gcc-11.2.1-20210728/gcc/testsuite/gcc.dg/compat/struct- > layout-1.exp ... > FAIL:

[Bug target/101930] [12 Regression] ICE in extract_insn, at recog.c:2769 since r12-2888-g8c8df06e46493f6c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101930 --- Comment #2 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #1) > (> Maybe similar to PR101860. > > No, it's a different issue. > > Should be fixed by > > { > rtx op2 = gen_reg_rtx (mode); > > - if

[Bug target/101812] [12 Regression] ICE: Segmentation fault (in ix86_expand_sse_movcc) since r12-731-gb1f7fd8a2a5558da

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101812 Uroš Bizjak changed: What|Removed |Added CC|uros at gcc dot gnu.org| Resolution|---

[Bug fortran/101660] [12 Regression] FAIL: gfortran.dg/bind_c_array_params_3.f90

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101660 Uroš Bizjak changed: What|Removed |Added CC||ubizjak at gmail dot com --- Comment #7

[Bug libfortran/101820] fatal error: ISO_Fortran_binding.h: No such file or directory

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101820 Uroš Bizjak changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW

[Bug libfortran/101820] New: fatal error: ISO_Fortran_binding.h: No such file or directory

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101820 Bug ID: 101820 Summary: fatal error: ISO_Fortran_binding.h: No such file or directory Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/101812] [12 Regression] ICE: Segmentation fault (in ix86_expand_sse_movcc) since r12-731-gb1f7fd8a2a5558da

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101812 Uroš Bizjak changed: What|Removed |Added Target Milestone|--- |12.0 Status|NEW

[Bug target/101797] ICE on valid code at -O2 and -O3: in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101797 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/101797] ICE on valid code at -O2 and -O3: in extract_constrain_insn, at recog.c:2670

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101797 Uroš Bizjak changed: What|Removed |Added Target Milestone|--- |12.0 Assignee|unassigned at

[Bug c++/100977] [C++23] Implement C++ Identifier Syntax using Unicode Standard Annex 31

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100977 --- Comment #8 from Uroš Bizjak --- (In reply to Jakub Jelinek from comment #7) > True, but is it worth changing on a tool that is one twice in a decade? Well, the question is self-answering ;)

[Bug c++/100977] [C++23] Implement C++ Identifier Syntax using Unicode Standard Annex 31

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100977 --- Comment #6 from Uroš Bizjak --- (In reply to Jakub Jelinek from comment #3) > - printf ("{ %s|%s|%s|%s|%s|%s|%s|%s|%s, %3d, %#06x },\n", > + printf ("{ %s|%s|%s|%s|%s|%s|%s|%s|%s|%s|%s, %3d, %#06x },\n", BTW: You can also use

[Bug target/101761] Random hang with 29_atomics/atomic_ref/wait_notify.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101761 --- Comment #2 from Uroš Bizjak --- (In reply to H.J. Lu from comment #0) > 29_atomics/atomic_ref/wait_notify.cc in 64-bit on Skylake server: > > It happens about once a few weeks. while true ; do ./a.out ; done will hang immediately.

[Bug target/101761] Random hang with 29_atomics/atomic_ref/wait_notify.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101761 --- Comment #1 from Uroš Bizjak --- Probably related to PR97936.

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 --- Comment #39 from Uroš Bizjak --- Please open a new bugreport, failures in Comment 37 and Comment 38 have nothing with r7-1112-gbeed3701c796842abbfb27d7484b35bd82818740 which was fully reverted. (FTR, fixed peepholes were ineffective, so

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|REOPENED

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 --- Comment #31 from Uroš Bizjak --- (In reply to H.J. Lu from comment #30) > (In reply to Uroš Bizjak from comment #29) > > (In reply to H.J. Lu from comment #28) > > > 29_atomics/atomic_ref/wait_notify.c has the same issue on Linux/x86-64 >

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 --- Comment #29 from Uroš Bizjak --- (In reply to H.J. Lu from comment #28) > 29_atomics/atomic_ref/wait_notify.c has the same issue on Linux/x86-64 with > -m32: Are you sure? The mentioned peephole2 patterns now emit only x87 or SSE DFmode

[Bug target/101346] ICE: maximum number of generated reload insns per insn achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101346 Uroš Bizjak changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com Ever

[Bug tree-optimization/101434] vector-by-vector left shift expansion for char/short is not optimal

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101434 --- Comment #3 from Uroš Bizjak --- (In reply to Richard Biener from comment #1) > Probably low priority if not doable nicely w/o XOP. -mxop can be substituted with -mavx512bw -mavx512vl for the same effect.

[Bug tree-optimization/101434] New: vector-by-vector left shift expansion for char/short is not optimal

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101434 Bug ID: 101434 Summary: vector-by-vector left shift expansion for char/short is not optimal Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/101424] [12 Regression] ICE in extract_insn, at recog.c:2771 since r12-2085-gf65878178ab05180

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101424 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/101424] [12 Regression] ICE in extract_insn, at recog.c:2771 since r12-2085-gf65878178ab05180

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101424 Uroš Bizjak changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com

[Bug rtl-optimization/55278] [9/10/11/12 Regression] Botan performance regressions, other compilers generate better code than gcc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55278 --- Comment #28 from Uroš Bizjak --- (In reply to Jakub Jelinek from comment #12) > (force gcc to avoid xorw memory, %hireg and instead use movzwl memory, > %sireg; ... xorl %sireg, %sireg2) and p2 was something similar for *xorqi_1. > >

[Bug c/101346] ICE: maximum number of generated reload insns per insn achieved (90)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101346 --- Comment #1 from Uroš Bizjak --- (In reply to G. Steinmetz from comment #0) > $ gcc-12-20210704 -c z1.c -O0 -m32 -fprofile-generate Also needs -msse. It looks that: (insn 38 37 39 6 (set (subreg:SI (reg:TD 83 [ _2 ]) 0)

[Bug target/100637] [i386] Vectorize 4-byte vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100637 --- Comment #11 from Uroš Bizjak --- The master branch has been updated by Uros Bizjak : https://gcc.gnu.org/g:be8749f939a933bca6de19d9cf1a510d5954c2fa commit r12-2036-gbe8749f939a933bca6de19d9cf1a510d5954c2fa Author: Uros Bizjak Date: Mon

[Bug target/101044] -ABS(A) produces two neg instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101044 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Target Milestone|---

[Bug rtl-optimization/101044] -ABS(A) produces two neg instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101044 --- Comment #3 from Uroš Bizjak --- The compound nabs insn also needs to be handled in the STV pass.

[Bug rtl-optimization/101044] -ABS(A) produces two neg instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101044 Uroš Bizjak changed: What|Removed |Added Last reconfirmed||2021-06-29 Ever confirmed|0

[Bug target/101185] [12 Regression] pr96814.c failed after r12-1669 on non-avx512 platform

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101185 --- Comment #10 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #9) > (In reply to Jakub Jelinek from comment #8) > > Yeah, ideally main including the cpuid check should be compiled with the > > least possible target and if the check

[Bug target/101185] [12 Regression] pr96814.c failed after r12-1669 on non-avx512 platform

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101185 --- Comment #6 from Uroš Bizjak --- (In reply to Richard Biener from comment #5) > Of course I wonder why the RA even chooses registers that are not available > on the architecture. I suppose there's no real way to turn regs on/off but > the

[Bug target/101175] builtin_clz generates wrong bsr instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101175 Uroš Bizjak changed: What|Removed |Added Target Milestone|--- |9.5 Status|ASSIGNED

[Bug target/101185] pr96814.c failed after r12-1669 on non-avx512 platform

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101185 --- Comment #4 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #1) > So would the solution of increasing one more unit(or maybe more) for cost of > mask->integer and integer->mask as compensation for changing alloca order be >

[Bug target/101175] builtin_clz generates wrong bsr instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101175 --- Comment #3 from Uroš Bizjak --- (In reply to Mikael Pettersson from comment #2) > (In reply to Iru Cai from comment #0) > > Built with '-march=x86-64-v3 -O1', the following code generates a bsr > > instruction, which has undefined behavior

[Bug target/101175] builtin_clz generates wrong bsr instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101175 Uroš Bizjak changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com Last

[Bug tree-optimization/101097] Vectorizer is too eager to use vec_unpack

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101097 --- Comment #8 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #6) > > I just to want to classify the test is used to test another optimization > which rely on either loop vectorization or slp. it means it's ok to add > unroll

[Bug tree-optimization/101097] Vectorizer is too eager to use vec_unpack

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101097 --- Comment #3 from Uroš Bizjak --- Created attachment 51031 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=51031=edit Pack/unpack patterns for 8-byte vectors FYI, this patch adds pack/unpack patterns for 8-byte vectors. It will fail:

[Bug tree-optimization/101097] New: Vectorizer is too eager to use vec_unpack

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101097 Bug ID: 101097 Summary: Vectorizer is too eager to use vec_unpack Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/101096] New: AVX512 VPMOV instruction should be used to downconvert vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101096 Bug ID: 101096 Summary: AVX512 VPMOV instruction should be used to downconvert vectors Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/101058] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-1215-g8d7dae0eb366a88a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101058 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/101058] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-1215-g8d7dae0eb366a88a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101058 --- Comment #9 from Uroš Bizjak --- (In reply to Jakub Jelinek from comment #8) > Though, when this *punpckwd define_insn_and_split handles all possible > constant permutations for V2HImode, shouldn't ix86_vectorize_vec_perm_const > say so: >

[Bug target/101058] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-1215-g8d7dae0eb366a88a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101058 --- Comment #6 from Uroš Bizjak --- (In reply to Jakub Jelinek from comment #5) We can split directly to sse2_pshuflw_1, avoiding mmx_pshufw_1. These two actually generate the same instruction (PSHUFLW) when XMM registers are involved.

[Bug target/101058] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-1215-g8d7dae0eb366a88a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101058 Uroš Bizjak changed: What|Removed |Added Last reconfirmed||2021-06-14 Assignee|unassigned

[Bug rtl-optimization/101044] -ABS(A) produces two neg instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101044 --- Comment #1 from Uroš Bizjak --- The first neg also sets sign flag (SF) for the following CMOVS.

[Bug target/101021] PSHUFB is emitted instead of PSHUFD, PSHUFLW and PSHUFHW with -msse4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101021 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/101023] [11/12 Regression] wrong code with -mstackrealign

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101023 Uroš Bizjak changed: What|Removed |Added CC||hjl.tools at gmail dot com --- Comment

[Bug target/101021] PSHUFB is emitted instead of PSHUFD, PSHUFLW and PSHUFHW with -msse4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101021 Uroš Bizjak changed: What|Removed |Added Last reconfirmed||2021-06-11 Ever confirmed|0

[Bug target/101021] New: PSHUFB is emitted instead of PSHUFD, PSHUFLW and PSHUFHW with -msse4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101021 Bug ID: 101021 Summary: PSHUFB is emitted instead of PSHUFD, PSHUFLW and PSHUFHW with -msse4 Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/100936] %p and %P modifiers should not emit segment overrides

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100936 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Assignee|unassigned at

[Bug target/43526] ICE: in construct_container, at config/i386/i386.c:5733 with -m96bit-long-double at x86_64-linux

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43526 Uroš Bizjak changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug target/100936] %p and %P modifiers should not emit segment overrides

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100936 --- Comment #1 from Uroš Bizjak --- Proposed patch: --cut here-- diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 04649b42122..0773a4a9ba8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -13531,7 +13531,7

[Bug target/100936] New: %p and %P modifiers should not emit segment overrides

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100936 Bug ID: 100936 Summary: %p and %P modifiers should not emit segment overrides Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug middle-end/100880] New: The build should error out for define_insn without insn template

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100880 Bug ID: 100880 Summary: The build should error out for define_insn without insn template Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/100626] [11/12 Regression] ICE Segmentation fault (during RTL pass: split1) since r11-165-geb72dc663e9070b2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100626 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/100722] [12 Regression] ice in extract_insn with many vector_size(4) arguments

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100722 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug c/100722] ice in extract_insn, at recog.c:2770

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100722 Uroš Bizjak changed: What|Removed |Added Last reconfirmed||2021-05-22 Target Milestone|---

[Bug tree-optimization/100696] mult_higpart is not vectorized

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100696 Uroš Bizjak changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Comment

[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701 Uroš Bizjak changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[Bug tree-optimization/100696] New: mult_higpart is not vectorized

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100696 Bug ID: 100696 Summary: mult_higpart is not vectorized Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/100626] [11/12 Regression] ICE Segmentation fault (during RTL pass: split1) since r11-165-geb72dc663e9070b2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100626 Uroš Bizjak changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com

[Bug target/100637] [i386] Vectorize 4-byte vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100637 Uroš Bizjak changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assignee|unassigned

[Bug target/100637] New: [i386] Vectorize 4-byte vectors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100637 Bug ID: 100637 Summary: [i386] Vectorize 4-byte vectors Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/100626] [11/12 Regression] ICE Segmentation fault (during RTL pass: split1) since r11-165-geb72dc663e9070b2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100626 --- Comment #3 from Uroš Bizjak --- *di3_doubleword calls split_double_mode with: op0: (subreg:DI (reg/v:SI 89 [ li_18 ]) 0) op1: (reg:DI 90 [ uc_4 ]) op2: (mem/c:DI (plus:SI (reg/f:SI 19 frame) (const_int -4 [0xfffc]))

[Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 --- Comment #16 from Uroš Bizjak --- (In reply to David Binderman from comment #15) > Bug first appears sometime between git hash 21dfb22920ce32fc, > dated yesterday and git hash 097fde5e7514e909, dated today. Fixed by PR100581.

[Bug target/100581] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-731-gb1f7fd8a2a5558da

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100581 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/100581] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-731-gb1f7fd8a2a5558da

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100581 --- Comment #3 from Uroš Bizjak --- (In reply to Alex Coplan from comment #1) > Is it valid to create a vector type with total size less than the element > size? Shouldn't this be rejected? No, the generated code is: vmovq

[Bug target/100581] [12 Regression] ICE in extract_insn, at recog.c:2770 since r12-731-gb1f7fd8a2a5558da

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100581 Uroš Bizjak changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com

[Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 --- Comment #13 from Uroš Bizjak --- (In reply to Uroš Bizjak from comment #12) > Yeah, this is a non-existent SSE "cmove". I tried to find all paths where > this should divert to a sequence of logic instructions or PBLENDB, but due > to

[Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 --- Comment #12 from Uroš Bizjak --- (In reply to David Binderman from comment #11) > I might be seeing something similar: > > caxcpy.f: In function 'caxcpy': > caxcpy.f:53:72: error: unrecognizable insn: >53 | end subroutine >

[Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 Uroš Bizjak changed: What|Removed |Added Assignee|ubizjak at gmail dot com |unassigned at gcc dot gnu.org ---

[Bug other/98375] [meta bug] GCC 12 pending patches

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98375 Bug 98375 depends on bug 98218, which changed state. Bug 98218 Summary: [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 What|Removed

[Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector compares (AVX512 masked compares missing)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 Uroš Bizjak changed: What|Removed |Added Summary|[TARGET_MMX_WITH_SSE] Miss |[TARGET_MMX_WITH_SSE]

[Bug target/100461] [11/12 Regression] mingw build broken due to change of rdtsc implementation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100461 Uroš Bizjak changed: What|Removed |Added CC||hjl.tools at gmail dot com --- Comment

[Bug target/100445] [12 Regression] ice during RTL pass: vregs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100445 --- Comment #10 from Uroš Bizjak --- Following patch fixes the failures: --cut here-- diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 4dfe7d6c282..61b2f921f41 100644 --- a/gcc/config/i386/i386-expand.c +++

[Bug target/100445] [12 Regression] ice during RTL pass: vregs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100445 --- Comment #9 from Uroš Bizjak --- ix86_use_mask_cmp_p should be refined, it has an early return for 64bit modes: if (GET_MODE_SIZE (mode) == 64) return true;

[Bug target/100445] [12 Regression] ice during RTL pass: vregs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100445 --- Comment #6 from Uroš Bizjak --- (In reply to Uroš Bizjak from comment #5) > ix86_expand_sse_movcc has special TARGET_XOP path, so the following patch is > needed: Ah, you beat me by the second ;) Anyway, I have no XOP target, so probably

[Bug target/100445] [12 Regression] ice during RTL pass: vregs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100445 --- Comment #5 from Uroš Bizjak --- ix86_expand_sse_movcc has special TARGET_XOP path, so the following patch is needed: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 347295afbb5..667dd057e0d 100644 ---

[Bug target/98218] [TARGET_MMX_WITH_SSE] Miss vec_cmpmn/vcondmn expander for 64bit vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug other/98375] [meta bug] GCC 12 pending patches

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98375 Bug 98375 depends on bug 98218, which changed state. Bug 98218 Summary: [TARGET_MMX_WITH_SSE] Miss vec_cmpmn/vcondmn expander for 64bit vector https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98218 What|Removed

[Bug rtl-optimization/100342] [10/11 Regression] wrong code with -O2 -fno-dse -fno-forward-propagate -mno-sse2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100342 --- Comment #8 from Uroš Bizjak --- FYI, this whole analysis was done with Fedora 33 system compiler: gcc version 10.3.1 20210422 (Red Hat 10.3.1-1) (GCC)

[Bug rtl-optimization/100342] [10/11 Regression] wrong code with -O2 -fno-dse -fno-forward-propagate -mno-sse2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100342 --- Comment #7 from Uroš Bizjak --- I have traced a bit where (insn 2275) and (insn 2287) come from. In _.ira, we have: 613: r125:QI=r2067:DI#0 ... 659: zero_extract(r2080:DI,0x8,0x8)=r125:QI#0 And in _.reload, a DImode reload is

[Bug rtl-optimization/100342] [10/11 Regression] wrong code with -O2 -fno-dse -fno-forward-propagate -mno-sse2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100342 --- Comment #5 from Uroš Bizjak --- The problem can be seen in _.pro_and_epilogue pass: Starting with: _.cmpelim 2741: r14:DI=[sp:DI+0x38] ... 368: di:DI=r14:DI ... 613: si:QI=r14:QI ... 2737: bp:DI=r14:DI ... 658:

[Bug rtl-optimization/100342] [10/11 Regression] wrong code with -O2 -fno-dse -fno-forward-propagate -mno-sse2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100342 --- Comment #4 from Uroš Bizjak --- The problematic insn is: 401cec: 44 89 f6mov%r14d,%esi This one should be 64 bit wide, movl%r14d, %esi # 613 [c=4 l=3] *movqi_internal/2 but is actually a

[Bug rtl-optimization/100342] [10/11 Regression] wrong code with -O2 -fno-dse -fno-forward-propagate -mno-sse2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100342 --- Comment #3 from Uroš Bizjak --- For some reason the *input* value at BSWAP insn is truncated to 32bits. v256u128 v256u128_1 = SHLV (SHLSV (__builtin_bswap64 (u128_0), (v256u128) (0 < v256u128_0)) <= 0, v256u128_0); u128_0

[Bug testsuite/100355] gcc.c-torture/execute/ieee/cdivchkld.c needs fmaxl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100355 --- Comment #3 from Uroš Bizjak --- (In reply to Christophe Lyon from comment #2) > Tried that, but it's not taken into account. > > ieee.exp uses c-torture-execute, maybe that function does not honor dg > directives? (none of the tests under

[Bug other/98375] [meta bug] GCC 12 pending patches

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98375 Bug 98375 depends on bug 98060, which changed state. Bug 98060 Summary: Failure to optimize cmp+setnb+add to cmp+sbb https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98060 What|Removed |Added

[Bug target/98060] Failure to optimize cmp+setnb+add to cmp+sbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98060 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/100312] __builtin_ia32_maskloadpd256 and friends should be pure

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100312 Uroš Bizjak changed: What|Removed |Added Assignee|rguenth at gcc dot gnu.org |ubizjak at gmail dot com

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/82735] _mm256_zeroupper does not invalidate previously computed registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82735 --- Comment #11 from Uroš Bizjak --- (In reply to Uroš Bizjak from comment #9) > (In reply to Richard Biener from comment #4) > > Indeed as far as I understand an unspec volatile isn't sth clobbering > > registers (not even memory?!). The insn

[Bug target/82735] _mm256_zeroupper does not invalidate previously computed registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82735 --- Comment #9 from Uroš Bizjak --- (In reply to Richard Biener from comment #4) > Indeed as far as I understand an unspec volatile isn't sth clobbering > registers (not even memory?!). The insn is missing inputs/outputs > (we might be able to

[Bug target/82735] _mm256_zeroupper does not invalidate previously computed registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82735 --- Comment #8 from Uroš Bizjak --- (In reply to Hongtao.liu from comment #7) > Confirmed, let me fix this. Please note that the current definition of vzeroupper does not model effects of the instruction at all. The current definition is

[Bug target/100041] ICE in curr_insn_transform, at lra-constraints.c:4022

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100041 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/100182] [8/9/10/11/12 Regression] Miscompilation of atomic_float/1.cc and atomic_float/wait_notify.cc on i686

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100182 Uroš Bizjak changed: What|Removed |Added Attachment #50649|0 |1 is obsolete|

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