[Bug target/114809] New: [RISC-V RVV] Counting elements might be simpler

2024-04-22 Thread wojciech_mula at poczta dot onet.pl via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114809 Bug ID: 114809 Summary: [RISC-V RVV] Counting elements might be simpler Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug c++/114747] New: [RISC-V RVV] Wrong SEW set for mixed-size intrinsics

2024-04-16 Thread wojciech_mula at poczta dot onet.pl via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114747 Bug ID: 114747 Summary: [RISC-V RVV] Wrong SEW set for mixed-size intrinsics Product: gcc Version: 13.2.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/114172] [13 only] ICE with riscv rvv VSETVL intrinsic

2024-03-28 Thread wojciech_mula at poczta dot onet.pl via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114172 Wojciech Mula changed: What|Removed |Added CC||wojciech_mula at poczta dot onet.p

[Bug target/88798] AVX512BW code does not use bit-operations that work on mask registers

2022-02-07 Thread wojciech_mula at poczta dot onet.pl via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88798 --- Comment #8 from Wojciech Mula --- Thank you for the answer. Thus my question is: is it possible to delay conversion from kmasks into ints? I'm not a language lawyer, but I guess a `x binop y` has to be treated as `(int)x binop (int)y`. If

[Bug target/88798] AVX512BW code does not use bit-operations that work on mask registers

2022-01-31 Thread wojciech_mula at poczta dot onet.pl via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88798 --- Comment #6 from Wojciech Mula --- Hongtao, thank you for your patch and for pinging back! I checked the code from this issue against version 11.2.0 (Debian 11.2.0-14), but still, there are KMOVQs before performing any bit ops. Here is the