https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89411
Bug ID: 89411 Summary: RISC-V backend will generate wrong instruction for longlong type like lw a3,-2048(a5) Product: gcc Version: 7.3.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: liuyingying19 at huawei dot com Target Milestone: --- Hi Experts, We are having below problem in the RISC-V backend. https://sourceware.org/bugzilla/show_bug.cgi?id=24226 We can confirm it is a compiler bug at this point. In our testcase, we are using the option –mcmodel = medlow and -mexplicit_relocs, but we got the similar problem that binutils will generate wrong instruction like lw a3,-2048(a5). When compiled to .S file, the result is correct: lui a5,%hi(g_3030) lw a4,%lo(g_3030)(a5) srli a4,a4,8 lw a3,%lo(g_3030+4)(a5) After link, the result is not correct: 1db2a: 0002a7b7 lui a5,0x2c 1db2e: 7fc7a703 lw a4,2044(a5) # 2c7fc <g_3030> 1db32: 8321 srli a4,a4,0x8 1db34: 8007a683 lw a3,-2048(a5) The result of %lo(g_3030+4) should be 2044 + 4 = 2048, but the value 2048 overflowed the 12 bit signed value, turn to -2048 and cause problem. Would you please git some advise on a workaround that is not going to affect the code size.