https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #9 from Andrew Pinski ---
Even for pre-LRA with reload in GCC 4.7.0:
t.c: In function ‘f’:
t.c:91:1: note: unable to find a register to spill in class ‘GR_REGS’
t.c:91:1: note: this is the insn:
(insn 33 32 34 2 (set (reg:DI 198)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
Andrew Pinski changed:
What|Removed |Added
Known to fail||7.3.0
--- Comment #8 from Andrew
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
Andrew Pinski changed:
What|Removed |Added
Ever confirmed|0 |1
Target|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
Andrew Pinski changed:
What|Removed |Added
Attachment #54791|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #6 from Andrew Pinski ---
Oh if we add back the s0 case, it fails at -O1 and above too.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #5 from Andrew Pinski ---
Created attachment 54794
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54794=edit
testcase for riscv32-elf
Here is a testcase which also fails for riscv32-elf. Note it only fails at -O0.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #4 from Andrew Pinski ---
Created attachment 54793
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54793=edit
Fixed up riscv64 testcase
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #3 from Andrew Pinski ---
On the trunk I get:
t.c: In function ‘f’:
t.c:94:1: error: s0 cannot be used in ‘asm’ here
94 | }
| ^
First with the RISCV example.
After removing the s0 variable usage I still get the ICE.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #2 from Andrew Pinski ---
(In reply to Piggy NL from comment #0)
> The assertion was introduced in e3b3b59683c1.
r11-5002-ge3b3b59683c1e7
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
--- Comment #1 from Piggy NL ---
Created attachment 54792
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54792=edit
Reproduce for mips64
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